Patent Application
20250192669
The present disclosure relates to a power converter (alternating current/direct current (AC/DC) converter) which converts AC voltage to DC voltage.
In recent years, electrification of automobiles, such as electric vehicles and hybrid vehicles, has become significantly active. These vehicles that run on electric power are equipped with high-output batteries as their power source. To charge the batteries, these vehicles are also equipped with charging systems (On Board Chargers: OBCs) that convert commercial AC power into DC power.
Many OBCs use AC/DC converters equipped with power factor correction circuits (PFC circuits) to solve power factor reduction caused by distortion of an input current waveform (e.g., JP2021-069253A). One type of PFC circuits that is widely used is a bridgeless PFC circuit in which diodes of a full-wave rectifier circuit with high loss is replaced with a switching element (MOSFET) to improve efficiency.
The AC/DC converter equipped with such a bridgeless PFC circuit generally adopts an average current mode control since there is no need to apply slope compensation in the control method.
However, the average current mode control has a disadvantage in which a reactor becomes large in size since the current control becomes unstable when the capacity of the reactor is small. In addition, since the switching frequency is basically the same as the control frequency, it is also disadvantageous in that it is difficult to increase the switching frequency.
For the disclosed technology, JP2022-129664A discloses a bridgeless PFC circuit, in which every time a polarity of input voltage changes between positive and negative, the polarity is determined and two MOSFETs (Nch) are controlled to switch between an active switch and a synchronous rectification switch. With this method, due to the complex polarity determination, the circuit and control are likely to become complicated.
One possible solution to the above-mentioned disadvantages of the average current mode control is adoption of a peak current mode control. By adopting the peak current mode control, the pulsation of the reactor current can be made larger than that of the average current mode control, and the current control is relatively stable even if the capacity of the reactor is small. Therefore, the reactor can be made smaller in size. However, in the case of the peak current mode control, the slope compensation is necessary to ensure stable operation.
In this regard, electronic components such as integrated circuits (ICs) and microcomputers that perform the function of slope compensation are commercially available. Therefore, these electronic components (slope compensation function components) are considered to be used as the AC/DC converters equipped with the bridgeless PFC circuits.
However, those commercially-available slope compensation function components have been developed for DC/DC converters which handle DC power, and therefore are structured to only process signals for positive slope compensation. In contrast, the AC/DC converters that handle AC power require signal processing with negative slope compensation, and therefore the peak current mode control is not possible by simply using the commercially-available slope compensation function components as they are. This is likely a significant reason why the average current mode control has become the mainstream in the AC/DC converters equipped with the bridgeless PFC circuits.
Thus, the present disclosure discloses a technique which enables an AC/DC converter provided with a bridgeless PFC circuit to perform a peak current mode control using commercially-available slope compensation function components.
The present disclosure relates to a power converter configured to convert AC input voltage into DC output voltage, including a converter mechanism having a bridgeless PFC circuit and a controller which controls the converter mechanism, that is, an AC/DC converter.
The bridgeless PFC circuit includes a pair of input-side wirings which inputs the AC input voltage, a pair of output-side wirings which outputs the DC output voltage, a capacitor connected to the pair of input-side wirings, a reactor disposed in at least one of the pair of input-side wirings at a position on an output side of a connecting position with the capacitor, and a first switching element and a second switching element each disposed between one of the pair of input-side wirings and one of the pair of output-side wirings, and on which a switching operation is performed by the controller.
The controller includes a peak current control unit which executes a peak current mode control by using a first slope compensation circuit corresponding to a positive polarity of the AC input voltage, and a second slope compensation circuit corresponding to a negative polarity of the AC input voltage. The second slope compensation circuit has an inverting circuit which inverts the polarity of the AC input voltage, and is structured using a same slope compensation circuit as the first slope compensation circuit.
In other words, according to the power converter, the second slope compensation circuit corresponding to the negative polarity includes the inverting circuit which inverts the polarity of the input voltage, and is structured using the same slope compensation circuit as the first slope compensation circuit. Thus, the peak current mode control can be performed using commercially-available slope compensation function components, making it possible to reduce the size of the reactor and providing an AC/DC converter which is inexpensive and high in performance.
The controller may further include a DC voltage control unit which outputs a first input current command value corresponding to the maximum value of the input current flowing in the input-side wirings on the output side from the connecting positions with the capacitor. The first input current command value may be converted to a second input current command value corresponding to an instantaneous value based on a phase of the AC input voltage. A peak current command value output to the peak current control unit may be set by adding a given current correction amount to the second input current command value.
Thus, the peak current mode control can be performed with a relatively simple circuit.
The controller may further include an AC current control unit which receives the second input current command value and outputs a third input current command value corresponding to an instantaneous value of the input current flowing in the input-side wirings at the connecting positions with the capacitor. The peak current command value received by the peak current control unit may be set by adding the current correction amount to the third input current command value.
Thus, improvements in responsiveness and a distortion rate of the reactor current can be expected. In detail, crossover distortion can be suppressed. As a result, a total harmonic distortion rate of the reactor current can be improved. Therefore, it is possible to provide an AC/DC converter with higher performance.
The bridgeless PFC circuit may include various configurations.
For example, the bridgeless PFC circuit may further include a first diode and a second diode, and a first leg and a second leg connected in parallel to each other between the pair of output-side wirings. The first leg may be provided with the first switching element and the first diode in series so that the current flows in directions away from each other, and the second leg may be provided with the second switching element and the second diode symmetrically to the first switching element and the first diode. An output end of one of the input-side wirings may be connected to the first leg between the first switching element and the first diode, and an output end of the other one of the input-side wirings may be connected to the second leg between the second switching element and the second diode.
Alternatively, the bridgeless PFC circuit may further include a first diode and a second diode, and a first leg and a second leg connected in parallel to each other between the pair of output-side wirings. The first leg may be provided with the first diode and the second diode in series so that the current flows in the same direction, and the second leg may be provided with the first switching element and the second switching element in series so that the current flows opposite from the first diode and the second diode. An output end of one of the input-side wirings may be connected to the first leg between the first diode and the second diode, and an output end of the other one of the input-side wirings may be connected to the second leg between the first switching element and the second switching element.
Alternatively, the bridgeless PFC circuit may further include a first diode, a second diode, a third diode, and a fourth diode, a first leg and a second leg connected in parallel to each other between the pair of output-side wirings, and a third leg connected to the pair of input-side wirings therebetween, on the output side from the reactor. The first leg may be provided with the first diode and the second diode in series so that the current flows in the same direction, and the second leg may be provided with the third diode and the fourth diode symmetrically to the first diode and the second diode. The third leg may be provided with the first switching element and the second switching element in series so that the current flows against each other. An output end of one of the input-side wirings may be connected to the first leg between the first diode and the second diode, and an output end of the other one of the input-side wirings may be connected to the second leg between the third diode and the fourth diode.
The present disclosure can be applied effectively to the AC/DC converters including such configurations of bridgeless PFC circuits.
Hereinafter, one embodiment of the present disclosure is described with reference to the accompanying drawings. Note that the following description is essentially merely illustrative. Components of circuits are annotated with specific marks along with alphanumeric codes to identify them. For the sake of convenience, the circuit components may be described or illustrated using only those marks. The capital letter “I” for current indicates its maximum value (amplitude value), and the lowercase letter “i” for current indicates its instantaneous value.
The top part of
As illustrated in the middle part of
The DC/DC converter 5 converts DC voltage into different DC voltage. The DC/DC converter 5 converts the DC voltage (Vdc) converted by the AC/DC converter 6 into given DC voltage (Vdc′) and outputs it to the battery 4 side.
As illustrated in the lower part of
The current sensor 10 is a Hall element type sensor and is installed at a given position of an input-side wiring 21, as described below. The current sensor 10 directly measures input current (reactor current iinv) flowing through a reactor 24 and outputs it to the controller 14. The input voltage sensor 11 is also installed at a given position of the input-side wiring 21, and directly measures the AC input voltage einv inputted to the AC/DC converter 6 and outputs it to the controller 14. The output voltage sensor 12 is installed at a given position of an output-side wiring 22 and directly measures the DC output voltage Vdc outputted from the AC/DC converter 6 and outputs it to the controller 14.
Based on these measurement values, the controller 14 performs an ON/OFF control by outputting drive voltage to two switching elements S1 and S2 of the bridgeless PFC circuit 20. That is, the controller 14 switches the switching elements S1 and S2 between a conducting state (ON) and a non-conducting state (OFF) at a given timing.
That is, each of the A-C bridgeless PFC circuits 20 has a pair of input-side wirings 21 (an N input-side wiring 21a on the ground side and an L input-side wiring 21b on the non-ground side), a pair of output-side wirings 22 (an N output-side wiring 22a on the negative side and a P output-side wiring 22b on the positive side), an input-side capacitor 23 (Cinv), the reactor 24 (Linv), a first switching element 25 (S1), and a second switching element 26 (S2).
The pair of input-side wirings 21 is disposed on the side of the commercial power source 2, and the AC input voltage einv is inputted to input terminals thereof. On the other hand, the pair of output-side wirings 22 is disposed on the side of the battery 4, and the DC output voltage Vdc is outputted from output terminals thereof. The input-side capacitor 23 is connected between the pair of input-side wirings 21 near the input terminals.
The reactor 24 is disposed at least in one of the input-side wiring 21 at a position on the output side from a connecting point of the input-side capacitor 23. In this embodiment, the reactor 24 is disposed in the L input-side wiring 21b. While the first switching element 25 and the second switching element 26 have different positional arrangements depending on the type, they are disposed between the input-side wirings 21 and the output-side wirings 22.
Each of the first switching element 25 and the second switching element 26 is made of a known MOSFET having gate, source, and drain terminals. Each of the first switching element 25 and the second switching element 26 is turned ON by receiving a given drive voltage in the gate terminal. Both the first switching element 25 and the second switching element 26 include a flyback diode 27 connected in inverse parallel to the electrical load.
In the case of the type A bridgeless PFC circuit 20, in addition to the basic circuit described above, it further includes a first diode 31 (D1), a second diode 32 (D2), a first leg 33, a second leg 34, an output-side capacitor 35 (Cdc), and a second reactor 36. The second reactor 36 is arranged in the N input-side wiring 21a symmetrically to the reactor 24. Note that the second reactor 36 may be omitted.
The output-side capacitor 35 is connected between the pair of output-side wirings 22a and 22b near output terminals thereof. The first leg 33 and the second leg 34 are connected in parallel to each other between the pair of output-side wirings 22a and 22b on the input side of the output-side capacitor 35. Further, the first switching element 25 and the first diode 31 are arranged in series in the first leg 33 so that the current flows in the direction away from each other.
Specifically, the first switching element 25 and the first diode 31 are arranged in this order from the N output-side wiring 22a side to the P output-side wiring 22b side. In the ON state, the first switching element 25 is arranged so that the current flows from the P output-side wiring 22b side to the N output-side wiring 22a side, and the first diode 31 is arranged so that the current flows from the N output-side wiring 22a side to the P output-side wiring 22b side.
The second switching element 26 and the second diode 32 are arranged in the second leg 34 symmetrically to the first switching element 25 and the first diode 31.
Specifically, the second switching element 26 and the second diode 32 are arranged in this order from the N output-side wiring 22a side to the P output-side wiring 22b side. In the ON state, the second switching element 26 is arranged so that the current flows from the P output-side wiring 22b side to the N output-side wiring 22a side, and the second diode 32 is arranged so that the current flows from the N output-side wiring 22a side to the P output-side wiring 22b side.
An output end of the N input-side wiring 21a is connected to the first leg 33 between the first switching element 25 and the first diode 31. An output end of the L input-side wiring 21b is connected to the second leg 34 between the second switching element 26 and the second diode 32.
In the case of the type B bridgeless PFC circuit 20, in addition to the basic circuit described above, it further includes a first diode 41, a second diode 42, a third diode 43 (D3), a fourth diode 44 (D4), a first leg 45, a second leg 46, a third leg 47, and an output-side capacitor 48.
The output-side capacitor 48 is connected between the pair of output-side wirings 22a and 22b near output terminals thereof. The first leg 45 and the second leg 46 are connected in parallel to each other between the pair of output-side wirings 22a and 22b on the input side of the output-side capacitor 48. The third leg 47 is connected between the pair of input-side wirings 21a and 21b on the output side of the reactor 24. The first diode 41 and the second diode 42 are arranged in series in the first leg 45 to have the same conductive direction.
Specifically, the second diode 42 and the first diode 41 are arranged in this order from the N output-side wiring 22a side to the P output-side wiring 22b side. Further, the first diode 41 and the second diode 42 are arranged so that the current flows from the N output-side wiring 22a side to the P output-side wiring 22b side.
The third diode 43 and the fourth diode 44 are arranged in the second leg 46 symmetrically to the first diode 41 and the second diode 42. Specifically, the fourth diode 44 and the third diode 43 are arranged in this order from the N output-side wiring 22a side to the P output-side wiring 22b side. The third diode 43 and the fourth diode 44 are arranged so that the current flows from the N output-side wiring 22a side to the P output-side wiring 22b side.
The first switching element 25 and the second switching element 26 are arranged in series in the third leg 47 to have opposing conductive directions to each other. Specifically, the second switching element 26 and the first switching element 25 are arranged in this order from the N input-side wiring 21a side to the L input-side wiring 21b side. The second switching element 26 in the ON state is arranged so that the current flows from the N input-side wiring 21a side to the L input-side wiring 21b side, and the first switching element 25 in the ON state is arranged so that the current flows from the L input-side wiring 21b side to the N input-side wiring 21a side.
The output end of the N input-side wiring 21a is connected to the first leg 45 between the first diode 41 and the second diode 42. The output end of the L input-side wiring 21b is connected to the second leg 46 between the third diode 43 and the fourth diode 44.
In the case of the type C bridgeless PFC circuit 20, in addition to the basic circuit described above, it further includes a first diode 51, a second diode 52, a first leg 53, a second leg 54, and an output-side capacitor 55.
The output-side capacitor 55 is connected between the pair of output-side wirings 22a and 22b near output terminals thereof. The first leg 53 and the second leg 54 are connected in parallel to each other between the pair of output-side wirings 22a and 22b on the input side of the output-side capacitor 55.
The first diode 51 and the second diode 52 are arranged in series in the first leg 53 to have the same conductive direction. Specifically, the second diode 52 and the first diode 51 are arranged in this order from the N output-side wiring 22a side to the P output-side wiring 22b side. Both of the first diode 51 and the second diode 52 are arranged so that the current flows from the N output-side wiring 22a side to the P output-side wiring 22b side.
The first switching element 25 and the second switching element 26 are arranged in series in the second leg 54 so that the current flows opposite from that in the first diode 51 and the second diode 52. Specifically, the second switching element 26 and the first switching element 25 are arranged in this order from the N output-side wiring 22a side to the P output-side wiring 22b side. Further, both of the first switching element 25 and the second switching element 26 are arranged so that the current flows from the P output-side wiring 22b side to the N output-side wiring 22a side in the ON state.
Further, the output terminal of the N input-side wiring 21a is connected to the first leg 53 between the first diode 51 and the second diode 52. The output terminal of the L input-side wiring 21b is connected to the second leg 54 between the first switching element 25 and the second switching element 26.
A specific operation of the AC/DC converter 6 by the control of the controller 14 is described with reference to
A reference character R illustrated in
In
In other words, the controller 14 executes a switching operation of the first switching element S1 and the second switching element S2 according to the polarity of the input voltage einv, which changes periodically, in order to change the target of the switching operation. Specifically, when the polarity of the input voltage einv is positive, as illustrated in parts (a) and (b), the first switching element S1 is turned OFF and the switching operation of the second switching element S2 is performed. When the polarity of the input voltage einv is negative, as illustrated in parts (c) and (d), the second switching element S2 is turned OFF and the switching operation of the first switching element S1 is performed.
As illustrated in part (a), when the polarity of the input voltage einv is positive and the second switching element S2 is turned ON, input current iac flows from the L input-side wiring 21b. Then, as indicated by a dashed arrow Y1, the input current iac flows through a current path comprised of an intermediate position of the second leg 54, the second switching element S2, the N output-side wiring 22a, the first switching element S1 (the flyback diode 27), an intermediate position of the first leg 53, and the N input-side wiring 21a. In other words, the input current iac does not flow to the battery 4 side.
As illustrated in part (b), when the polarity of the input voltage einv is positive and the second switching element S2 is turned OFF, as indicated by a dashed arrow Y2, the input current iac flowing in from the L input-side wiring 21b flows through a current path comprised of the intermediate position of the second leg 54, the second diode 52, the P output-side wiring 22b, the load resistor R, the N output-side wiring 22a, the first switching element S1 (the flyback diode 27), the intermediate position of the first leg 53, and the N input-side wiring 21a. In other words, the input current iac flows to the battery 4 side.
As illustrated in part (c), when the polarity of the input voltage einv is negative and the first switching element S1 is turned ON, the input current iac flows in from the N input-side wiring 21a. Then, as indicated by a dashed arrow Y3, the input current iac flows through a current path comprised of the intermediate position of the first leg 53, the first switching element S1, the N output-side wiring 22a, the second switching element S2 (the flyback diode 27), the intermediate position of the second leg 54, and the N input-side wiring 21a. In other words, the input current iac does not flow to the battery 4 side.
As illustrated in part (d), when the polarity of the input voltage einv is negative and the first switching element S1 is turned OFF, as illustrated by a dashed arrow Y4, the input current iac flowing in from the N input-side wiring 21a flows through a current path comprised of the intermediate position of the first leg 53, the first diode 51, the P output-side wiring 22b, the load resistor R, the N output-side wiring 22a, the second switching element S2 (the flyback diode 27), the intermediate position of the second leg 54, and the N input-side wiring 21a. That is, the input current iac flows to the battery 4 side.
As described above, the controller 14 outputs required output voltage Vdc by switching between the first switching element S1 and the second switching element S2. One example of a block diagram of the control circuit provided to the controller 14 for this is illustrated in
The controller 14 is configured with a DC voltage control unit 60 which controls the output voltage Vdc according to a given transfer function Gdc(s) so that a given level of the output voltage Vdc is outputted in response to an output voltage command value Vdc*, and a peak current control unit 80 which controls an ON/OFF timing of the first switching element S1 and the second switching element S2 based on a first current command value Iinv* obtained from the DC voltage control unit 60. The controller 14 is also configured with a phase locked loop 61, a multiplier 62, and an adder 63.
The DC voltage control unit 60 receives the command value Vdc* of the output voltage and an actual value Vdc of the output voltage measured by the output voltage sensor 12. Further, the DC voltage control unit 60 outputs a command value (the first input current command value Iinv*) corresponding to a maximum value of the input current (a reactor current iinv) flowing in the input-side wiring 21 on the output side of a connecting position of the input-side capacitor 23, that is, the reactor 24. The actual value Vdc of the output voltage is used as a feedback value, and the DC voltage control unit 60 controls the first input current command value Iinv* so that the actual value Vdc coincides with the command value Vdc*.
The first input current command value Iinv* is inputted to the multiplier 62, where it is converted into a command value (a second input current command value iinv*) corresponding to an instantaneous value based on the phase of the input voltage einv.
Specifically, the actual value of the input voltage einv measured by the input voltage sensor 11 is inputted to the phase synchronization circuit 61. The phase angle θinv of the input voltage einv is calculated based on the actual value, and a given signal (a phase signal, sin(θinv)) is outputted from the phase synchronization circuit 61 based on the phase angle θinv and received by the multiplier 62. In the multiplier 62, the first input current command value Iinv* is multiplied by the phase signal sin(θinv) to calculate the second input current command value iinv*, and this value is outputted.
The second input current command value iinv* is inputted to the adder 63, where a given current correction amount Δiinv is added. In this way, a peak current command value iinv*.p is set as an instantaneous value to be received by the peak current control unit 80. The current correction amount Δiinv is an estimated value of a pulsation component of the reactor current, and is calculated by Equation (1) illustrated in
In Equations (1) to (3), “Linv” indicates an inductance of the reactor 24. As described later, the PWM method which changes a duty ratio is used for the switching operation of the first switching element S1 and the second switching element S2. “TPWM” is a cycle signal indicating a timing corresponding to the switching cycle (a preset constant value) in the PWM control (see FIG. 8). “Ks” of Equation (2) is a value of a slope used for slope compensation in a peak current mode control described later. “d” of Equation (3) is a ratio of the input voltage to the output voltage.
In addition to the peak current command value iinv*.p, the actual value iinv of the reactor current measured by the voltage sensor is introduced as a feedback value to the peak current control unit 80. Further, TPWM, Ks, and TZRO are also introduced to the peak current control unit 80. “TZRO” is a set signal indicating a timing corresponding to 0 degree of the switching cycle in the PWM control.
As a result, the peak current control unit 80 outputs control signals Q1 and Q2 indicating a timing to turn ON/OFF the first switching element S1 and the second switching element S2.
Specifically, the improved controller 14A is further configured with the AC current control unit 70 which introduces a second input current command value iinv*, and outputs a command value (a third input current command value iac*) corresponding to the instantaneous value of the input current (AC current iac) flowing on the input side of the connecting position of the input-side wiring 21 with the input-side capacitor Cinv. By adding the third input current command value iac* inputted to the adder 63 with the current correction amount Δiinv, the peak current command value iinv*.p to be introduced to the peak current control unit 80 is set. Here, the second current command value iinv* illustrated in
The AC current control unit 70 has a subtractor 71, an AC current compensator 72, and a second adder 73. The AC current control unit 70 introduces the reactor current value iinv measured by the current sensor 10 together with the second input current command value iinv*. The subtractor 71 calculates a current difference value Δi by subtracting the reactor current value iinv from the second input current command value iinv*.
The current difference value Δi is inputted to the AC current compensator 72 configured with a given transfer function Ginv(s), and an output value obtained thereby is added to the second input current command value iinv* by the second adder 73. In this manner, the AC current control unit 70 calculates and outputs the third input current command value iac*.
As described later, since the peak current control unit 80 has a function of performing a feedback control, there is essentially no need to provide such an AC current control unit 70, and since the peak current control unit 80 also performs a control based on the instantaneous value, there is also a problem where the AC current control unit 70 and the peak current control unit 80 tend to interfere with each other. Therefore, providing such an AC current control unit 70 is not commonly considered.
However, by providing such an AC current control unit 70, improvements in responsiveness and a distortion rate of the reactor current iinv can be expected. In detail, crossover distortion, which is an inherent problem of the PFC circuit, can be suppressed. As a result, as described later, a total harmonic distortion rate of the reactor current iinv can be improved. Incidentally, the interference between the AC current control unit 70 and the peak current control unit 80 can be avoided by appropriately designing the AC current compensator 72.
This controller 14 (or the improved controller 14A, omitted below) is devised to be usable of inexpensive, commercially-available electronic components in order to provide the slope compensation function essential for the peak current mode control.
In other words, electronic components (slope compensation function components) such as integrated circuits (ICs) and microcomputers bearing the slope compensation function are commercially available, but these slope compensation function components have been developed for DC/DC converters which handle DC power, and are therefore structured to only be able to process signals for positive slope compensation.
In contrast, the controller 14 handles AC power also requiring signal processing for negative slope compensation, and therefore the peak current mode control cannot be achieved by simply using the commercially-available slope compensation function components as they are.
In this regard, in the controller 14, the peak current control unit 80 executes the peak current mode control by using a first slope compensation circuit corresponding to the positive polarity of the input voltage einv and a second slope compensation circuit corresponding to the negative polarity of the input voltage einv. The second slope compensation circuit includes an inversion circuit which inverts the polarity of the input voltage einv, and is configured using the same slope compensator as the first slope compensation circuit, that is, the slope compensator corresponding to the positive polarity.
Therefore, in the case of the controller 14, the peak current mode control can be achieved by using only the commercially-available slope compensation function components for the slope compensator. This allows the peak current mode control to be achieved with a simple and inexpensive circuit configuration. As a result, the stable operation can be achieved even if the reactor 24 is made smaller in size.
Specifically, the peak current control unit 80 has a first slope compensator 81, a first comparator 82, a second slope compensator 83, a second comparator 84, an inverting amplifier circuit 85, a pulse width modulation (PWM) control unit 86, the determination unit 87, a gate driver 88, etc. The first slope compensator 81 and the first comparator 82 constitute the first slope compensation circuit, and the second slope compensator 83, the second comparator 84, and the inverting amplifier circuit 85 constitute the second slope compensation circuit.
As described above, the first slope compensator 81 and the second slope compensator 83 have the same function supporting the positive polarity of the input voltage einv, and are constructed using the commercially-available slope compensation function components, such as analog ICs and control microcomputers.
The first slope compensator 81 receives a positive peak current command value iinv*.p corresponding to the positive half cycle, and Ks. “Ks” corresponds to a given slope value which is applied to the positive peak current control command value iinv*.p. Ks is generally used to suppress occurrence of low-frequency oscillation which occurs when the duty ratio exceeds 50%.
The first slope compensator 81 also receives a pulse-shaped set signal TZRO and a first reset signal TripA. As illustrated in
The set signal TZRO is inputted from the PWM control unit 86 based on the cycle signal. The first reset signal TripA is outputted from the first comparator 82 and then fed back to the first slope compensator 81. The first slope compensator 81 sets or resets the positive peak current command value iinv*.p based on the set signal TZRO and the first reset signal TripA.
The first slope compensator 81 applies the slope to the positive peak current command value iinv*.p based on the positive peak current command value iinv*.p and Ks, and outputs a result thereof to the first comparator 82 (the sloped dashed line portion in Part (a) of
The first comparator 82 compares its output value with the value of the reactor current iinv. When the output value of the first comparator 82 matches the value of the reactor current iinv (the matching portion in Part (a) of
The second slope compensator 83 receives a negative peak current command value −iinv*.p corresponding to the negative half cycle and Ks. As with the first slope compensator 81, the second slope compensator 83 also receives the set signal TZRO and the second reset signal TripB. The second slope compensator 83 sets or resets the negative peak current command value −iinv*.p based on the set signal TZRO and the second reset signal TripB.
The second slope compensator 83 applies a slope to the negative peak current command value −iinv*.p based on the negative peak current command value −iinv*.p and Ks, and outputs a result thereof to the second comparator 84 (the sloped dashed line portion in Part (b) of
The inverting amplifier circuit 85 receives the reactor current iinv and inverts the reactor current to a negative value (the negative reactor current value −iinv).
The second comparator 84 compares the output value from the second slope compensator 83 with the negative reactor current value −iinv. When the output value of the second comparator 84 matches the negative reactor current value −iinv (the matching portion in Part (b) of
The determination unit 87 has a lookup table set as illustrated in the table in
Specifically, as illustrated in Part (a) of
Further, as illustrated in Part (b) of
As illustrated in
The gate driver 88 turns the first switching element S1 ON/OFF based on the first control signal Q1, and turns the second switching element S2 ON/OFF based on the second control signal Q2. Specifically, when the first control signal Q1 is in the high state, the gate driver 88 outputs drive voltage to the first switching element S1 to turn the first switching element S1 ON. When the first control signal Q1 is in the low state, the gate driver 88 turns the first switching element S1 OFF without outputting the drive voltage thereto. The gate driver 88 turns the second switching element S2 ON/OFF in a similar manner depending on the state of the second control signal Q2.
While the present disclosure is realized using the controller 14 as illustrated in
Simulations were performed for two scenarios to verify the effect(s) of miniaturizing the reactor 24. The inductance of the reactor 24 in Scenario 1 was set to 340 μH. In Scenario 2, the inductance of the reactor 24 was set to the half of Scenario 1, 170 μH.
The circuit parameters used in the simulations of Scenarios 1 and 2 are as follows.
In other words, according to the present disclosure, it is possible to reduce the inductance of the reactor 24 to 170 μH or less.
Furthermore, the effect of the improved controller 14A was also verified. That is, the effects were compared between the cases where the AC current control unit 70 is provided and not provided. Specifically, simulations were performed in the circuit used for the situation of Scenario 2 described above, for the cases where the AC current control unit 70 is provided and not provided.
The results are illustrated in
As a result, it was confirmed that the total harmonic distortion (THDi) of the reactor current iinv was also improved by approximately 0.5% from 3.12%.
Thus, according to the present disclosure, the peak current mode control can be performed using a simple and inexpensive circuit, making it possible to reduce the size of the reactor 24 and improving the total harmonic distortion of the reactor current iinv.
It should be understood that the embodiments herein are illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalence of such metes and bounds thereof, are therefore intended to be embraced by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-206348 | Dec 2023 | JP | national |
