Patent Grant
10454364
The present invention relates to a power conversion device that converts the power of input from an AC power supply to obtain desired DC power.
Power conversion devices that convert AC power supplied from an AC power supply to DC power and supply the DC power to a DC load are increasingly required to have high efficiency, while power conversion devices for achieving high efficiency are proposed (see, for example, Patent Document 1). A power conversion device disclosed in Patent Document 1 is composed of: a rectification circuit connected to an AC power supply; a smoothing capacitor connected to the rectification circuit; a first switching circuit connected to the rectification circuit via the smoothing capacitor; a transformer provided with a resonance capacitor and a resonance inductor; and a second switching circuit provided on a DC load side with respect to the transformer. In the power conversion device, switching operation of the second switching circuit is controlled, whereby switching loss is reduced and high efficiency is achieved.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2012-249375
In the conventional power conversion device described above, since a current smoothing reactor is not provided at a DC output portion, it is difficult to perform high-power-factor control of AC current and adjustment of DC power outputted to the DC load at the same time. Therefore, ripple components of unspecified frequencies are inputted to the DC load, and in the case of using a battery as the DC load, ripple components of unspecified frequencies are mixed into battery current, whereby the battery might be deteriorated, leading to reduction in the life thereof.
The present invention has been made to solve the above problem, and an object of the present invention is to obtain a power converter capable of performing high-power-factor control of AC current and control of output power to the DC load.
A power conversion device according to the present invention includes: a first rectification circuit which rectifies AC power inputted from an AC power supply; an inverter circuit having a first leg, a second leg, and a DC capacitor connected in parallel to each other, the first leg having a first switching element and a second switching element connected in series to each other, a positive-side DC terminal of the first rectification circuit being connected to a first AC end which is a connection point between the first switching element and the second switching element, the second leg having a third switching element and a fourth switching element to which diodes are respectively connected in antiparallel, the third switching element and the fourth switching element being connected in series to each other, the inverter circuit having a negative-side DC bus connected to a negative-side DC terminal of the first rectification circuit; a transformer having a primary winding and a secondary winding, one end of the primary winding being connected to the first AC end of the inverter circuit, and another end of the primary winding being connected to a second AC end which is a connection point between the third switching element and the fourth switching element; a second rectification circuit having one end connected to the secondary winding of the transformer and another end connected to a DC load via a smoothing capacitor, the second rectification circuit rectifying AC power inputted from the transformer, and outputting the resultant power to the DC load; and a control circuit which controls operation of the inverter circuit, wherein the control circuit controls an ON period for the first leg, thereby controlling current outputted from the first rectification circuit, and the control circuit controls an ON period for the second leg and a phase shift amount between the ON period for the first leg and the ON period for the second leg, thereby controlling voltage of the DC capacitor to be constant.
The power conversion device according to the present invention makes it possible to achieve high-power-factor control and output power control at the same time by a single stage of full-bridge inverter circuit. Thus, in the case where a battery is connected as a DC load and a charging operation is performed, it becomes possible to supply charge power while reducing ripple components of unspecified frequencies which are mixed in battery current, whereby battery life deterioration can be prevented.
The configuration of a power conversion device according to embodiment 1 of the present invention will be described with reference to the drawings.
The power conversion device is composed of a main circuit for converting AC power inputted from the AC power supply 1 to DC power, and a control circuit for controlling the main circuit. The main circuit includes a transformer 6 having at least two windings. In the following description, of the main circuit, a side connected to the AC power supply 1 with respect to the transformer is assumed as a primary side, and a side connected to the DC load 10 is assumed as a secondary side. On the primary side of the main circuit, provided are: a rectification circuit (first rectification circuit) 200 for rectifying AC power; a reactor 3 operating as a current limiting circuit; and an inverter circuit 400 which converts DC power rectified by the rectification circuit 200 to AC power having desired voltage, and outputs the AC power to the transformer 6. On the secondary side of the main circuit, provided are: a rectification circuit (second rectification circuit) 700 for rectifying AC power outputted from the transformer 6 into DC power; and a smoothing reactor 8 and a smoothing capacitor 9 for smoothing DC power outputted from the rectification circuit 700.
The rectification circuit 200 as the first rectification circuit is connected to the AC power supply 1, and rectifies input from the AC power supply 1 so as to be converted to DC power. The rectification circuit 200 is a full-bridge circuit composed of four diode elements 201 to 204. A DC terminal of the rectification circuit 200 is connected to the inverter circuit 400 via the reactor 3. Here, of the two DC terminals of the rectification circuit 200, the positive-side terminal is referred to as a positive-side DC terminal, and the negative-side terminal is referred to as a negative-side DC terminal. It is noted that the rectification circuit 200 is not limited to the above configuration but may be any circuit that rectifies AC power into DC power. For example, some or all of the diode elements in the rectification circuit 200 may be replaced with active elements such as switching elements.
The reactor 3 is a current limiting reactor having an end connected to the positive-side DC terminal of the rectification circuit 200, and another end connected to the inverter circuit 400. The connection point between the reactor 3 and the inverter circuit 400 is connected to the primary-side terminal of the transformer 6. It is noted that the reactor 3 may be connected to the negative-side DC terminal of the rectification circuit 200, or reactors 3 may be distributed and connected to the two DC terminals of the rectification circuit 200.
The inverter circuit 400 is a full-bridge inverter circuit having four semiconductor switching elements 401a to 404a, and each semiconductor switching element performs switching operation on the basis of a gate signal from the control circuit 11. For the semiconductor switching elements 401a to 404a, diodes 401b to 404b are respectively connected in antiparallel thereto, and capacitors 401c to 404c are connected in parallel thereto. For the semiconductor switching elements 401a to 404a, semiconductor elements such as MOSFETs may be used.
The semiconductor switching element 401a (first switching element) and the semiconductor switching element 402a (second switching element) are connected in series, and the semiconductor switching element 403a (third switching element) and the semiconductor switching element 404a (fourth switching element) are connected in series. Here, the semiconductor switching element 401a and the semiconductor switching element 402a connected in series are referred to as a first leg, and the semiconductor switching element 403a and the semiconductor switching element 404a connected in series are referred to as a second leg. The semiconductor switching element 401a is diagonal to the semiconductor switching element 404a, and the semiconductor switching element 402a is diagonal to the semiconductor switching element 403a.
The connection point (first AC end) between the semiconductor switching element 401a and the semiconductor switching element 402a is connected to the positive-side DC terminal of the rectification circuit 200 via the reactor 3, and is also connected to the primary-side terminal of the transformer 6. The inverter circuit 400 includes a DC capacitor 5, and the DC capacitor 5, the first leg, and the second leg are connected in parallel between DC buses (P and N buses). The negative-side bus of the inverter circuit 400 is connected to the negative-side DC terminal of the rectification circuit 200.
The transformer 6 is an isolation transformer composed of two windings (primary winding and secondary winding). One end of the primary winding is connected to the first AC end of the inverter circuit 400, and the other end is connected to a second AC end which is the connection point between the semiconductor switching element 403a and the semiconductor switching element 404a. Here, a leakage inductance of the transformer 6 is used as a resonance element. However, an external reactor may be used therefor.
The rectification circuit 700 as the second rectification circuit is a full-bridge circuit composed of four diode elements, as in the rectification circuit 200. The AC terminal of the rectification circuit 700 is connected to the secondary-side output terminal of the transformer 6, and rectifies AC power outputted from the transformer 6 and outputs the resultant power from the DC terminal of the rectification circuit 700. It is noted that the rectification circuit 700 is a full-bridge diode rectification type, but may be any circuit that rectifies AC power outputted from the transformer 6. For example, some or all of the diode elements in the rectification circuit 700 may be replaced with active elements such as semiconductor switching elements.
The positive-side DC terminal of the rectification circuit 700 is connected to the smoothing reactor 8, and the smoothing capacitor 9 is connected between the subsequent stage of the smoothing reactor 8 and the negative-side DC terminal of the rectification circuit 700. The DC load 10 is connected to the smoothing capacitor 9, and DC power outputted from the rectification circuit 700 is supplied to the DC load.
The DC load 10 is, for example, a storage battery (battery). Other than this, the DC load 10 may be a DC load needed to be isolated from the AC input, and for example, may be an electric double-layer capacitor.
The power conversion device shown in
Next, operation of the power conversion device shown in embodiment 1 of the present invention, i.e., operation of converting AC power inputted from the AC power supply 1 to DC power and outputting the DC power to the DC load 10, will be described with reference to the drawings.
Here, T is the drive cycle of the semiconductor switching elements 401a, 402a, 403a, 404a, and t2 is a switching time of the semiconductor switching elements 401a and 402a with which current control is performed. In addition, t1 is an OFF timing of the semiconductor switching element 404a, and t3 is an OFF timing of the semiconductor switching element 403a. In this case, operation modes can be classified into operation modes for four periods of 0 to t1 (first operation mode), t1 to t2 (second operation mode), t2 to t3 (third operation mode), and t3 to T (fourth operation mode). The current routes for the respective four operation modes are shown in
Operation of the power conversion device in the first operation mode, i.e., during the period of 0 to t1 shown in
Operation of the power conversion device in the second operation mode, i.e., during the period of t1 to t2 shown in
Operation of the power conversion device in the third operation mode, i.e., during the period of t2 to t3 shown in
Operation of the power conversion device in the fourth operation mode, i.e., during the period of t3 to T shown in
As described above, in the first operation mode and the third operation mode, current is inputted to the transformer 6 and power is supplied to the secondary side, while the polarity of the current is inverted between the first operation mode and the third operation mode. By changing these operation modes, AC current is inputted to the transformer 6. The AC power inputted to the primary side of the transformer 6 is subjected to voltage transformation in accordance with the ratio of the numbers of winding turns, and then outputted to the secondary side. At the stage subsequent to the transformer 6, AC power is converted to DC power by the rectification circuit 700, the DC power is smoothed by the smoothing reactor 8 and the smoothing capacitor 9, and the smoothed DC power is supplied to the DC load 10. That is, during the periods of the first operation mode and the third operation mode, DC power can be supplied to the DC load 10.
In the power conversion device shown in embodiment 1 of the present invention, the ON period for the first leg, i.e., the time ratio between the first and second operation modes which correspond to the ON period of the semiconductor switching element 401a, and the third and fourth operation modes which correspond to the ON period of the semiconductor switching element 402a, is controlled. That is, through control of time t2 in
In addition, the ON period of the second leg, i.e., the time ratio between the second and third operation modes which correspond to the ON period of the semiconductor switching element 403a, and the first and fourth operation modes which correspond to the ON period of the semiconductor switching element 404a, is controlled. In addition, a phase shift amount between the ON period for the first leg and the ON period for the second leg, i.e., an amount (phase shift amount) by which the phase of a drive signal for the semiconductor switching element 403a is shifted relative to the semiconductor switching element 401a, and an amount by which the phase of a drive signal for the semiconductor switching element 404a is shifted relative to the semiconductor switching element 402a, are controlled, whereby the charge amount and the discharge amount of the DC capacitor 5 are adjusted and thus voltage Vdc of the DC capacitor 5 can be controlled to be constant. Alternatively, the difference between AC power taken through the current control as described above and power supplied to the DC load 10 is adjusted, whereby voltage Vdc of the DC capacitor 5 is controlled to be constant. This means controlling time t1 and time t3 in
As described above, in the power conversion device shown in embodiment 1, current control using the semiconductor switching element 401a and the semiconductor switching element 402a, and voltage control for Vdc, using the semiconductor switching element 403a and the semiconductor switching element 404a, are performed individually, whereby it is possible to supply DC power to the DC load 10 while achieving current control and voltage control at the same time. Therefore, by performing current control, high-power-factor control for AC power can be performed, i.e., the power factor can be controlled to be approximately 1. In addition, by controlling voltage Vdc of the DC capacitor 5 to be constant, output power to the DC load 10 can be controlled. Therefore, in the case where a battery is connected as the DC load, ripple components of unspecified frequencies in the battery current can be reduced, so that charge power with high quality can be supplied.
Here, the way of determining t1, t2, t3 in
Here, vac is the voltage of the AC power supply 1, and Vdc is the voltage of the DC capacitor 5. Thus, the semiconductor switching element 401a and the semiconductor switching element 402a are driven with the time ratios based on expression (1) and expression (2), respectively.
First, in the initial state, i.e., a state at the start of battery charge control operation, the phase shift amount for the second leg is set to zero. In the initial state, for making the phase shift amount be zero, rising of the ON state of the semiconductor switching element 403a is synchronized with rising of the ON state of the semiconductor switching element 401a. Similarly, rising of the ON state of the semiconductor switching element 404a is synchronized with rising of the ON state of the semiconductor switching element 402a. That is, the ON period (gate pulse width) and the phase for the third switching element are set to be equal to those for the first switching element, and the ON period (gate pulse width) and the phase for the fourth switching element are set to be equal to those for the second switching element. In this case, only operations in the second and fourth operation modes are performed, while the periods of the first and third operation modes become zero. The control circuit 11 controls the phase shift amount from this initial state. Thus, in the initial state, supply of power can be mildly started.
For making the phase shift amount be zero, rising of the ON state of the semiconductor switching element 404a may be synchronized with rising of the ON state of the semiconductor switching element 401a. At this time, rising of the ON state of the semiconductor switching element 403a may be synchronized with rising of the ON state of the semiconductor switching element 402a. That is, the ON period (gate pulse width) and the phase for the fourth switching element are set to be equal to those for the first switching element, and the ON period (gate pulse width) and the phase for the third switching element are set to be equal to those for the second switching element. In this case, only operations in the first and third operation modes are performed, while the periods of the second and fourth operation modes become zero. The control circuit 11 controls the phase shift amount from this initial state. Thus, supply of power can be started sharply from the initial state. It is noted that it is not always necessary to make the phase shift amount be zero, but a phase shift amount defined in advance in accordance with requirements in the initial state may be set for the initial state.
As described above, currents with opposite polarities flow through the transformer 6 in the period of the first operation mode and the period of the third operation mode, respectively. Therefore, in order to suppress magnetic bias of the isolation transformer, the overlap period (period of first operation mode) between the semiconductor switching elements 401a and 404a, and the overlap period (period of third operation mode) between the semiconductor switching elements 402a and 403a, are controlled to be equal to each other. That is, the period of 0 to t1 and the period of t2 to t3 in
Next, the phase shift amount for the second leg will be described. The phase shift amount for the second leg corresponds to the length of the period of the first operation mode (t0 to t1) in
In the power conversion device shown in the present embodiment, D403 needs to be always smaller than D401 and D402. That is, t1 needs to satisfy a relationship of 0≤t1≤t2, and t3 needs to satisfy a relationship of t2≤t3≤T.
If D403 is smaller than Dlimit, the current conduction periods of 0 to t1 and t2 to t3 for the transformer 6 can be optionally adjusted and the Vdc control can be achieved. In the present embodiment, the control-allowed condition for controlling voltage Vdc of the DC capacitor to be constant is that D403 is smaller than Dlimit at the peak phase, i.e., Dlimit_p. This means that expression (5) is the control-allowed condition.
At a phase near zero, since Dlimit is in principle infinitely close to zero, the relationship of expression (5) cannot be satisfied. In this case, the command value D403 is controlled so as to be equal to or smaller than Dlimit. In this case, the trajectory of D403 is as shown in
As described above, the phase shift amount D403 for the semiconductor switching element 403a and the semiconductor switching element 404a is set to be equal to or smaller than the limit Dlimit based on D401 and D402 defined by the current control using the semiconductor switching element 401a and the semiconductor switching element 402a, whereby the control for making Vdc constant is enabled, and thus the high-power-factor control and the output power control can be achieved with a single full-bridge inverter circuit.
It is noted that, even if only the ON periods are controlled for the semiconductor switching elements 403a, 404a, the high-power-factor control and the output power control can be achieved, but a through current occurs in the semiconductor switches and the loss increases. However, by controlling also the phase shift amount for the second leg, the through current can be suppressed and high-efficiency operation by soft-switching operation is enabled.
Since charging and discharging of the DC capacitor 5 are performed in the drive cycle T of the inverter circuit 400, voltage ripple based on the drive cycle occurs. In particular, the voltage ripple is prescribed by the voltage ripple during the charge period in the second operation mode. In general, in a single-phase inverter connected to a single-phase system, voltage ripple having a frequency twice as high as the AC frequency occurs at the DC part. However, in the power conversion device shown in the present embodiment, such voltage ripple having the two-fold frequency does not occur. Therefore, the capacitance of the DC capacitor 5 can be greatly reduced and the DC capacitor 5 can be downsized.
In the power conversion device of the present embodiment, voltage and current of the AC power supply where the power factor becomes 1 are represented as shown by expressions (6), (7). In addition, power Pac of the AC power supply 1 is represented as shown by expression (8). In the power conversion device shown in the present embodiment, Pac represented by expression (8) is entirely transferred to the DC load 10. If the voltage of the DC load 10 is controlled to be constant voltage Vbat, current Ibat supplied to the DC load is defined by expression (9). Therefore, the current flowing into the DC load 10 has a pulsating component having a two-fold AC frequency.
Next, the details of a method for the current control using the semiconductor switching element 401a and the semiconductor switching element 402a, i.e., controlling current iac so as to be a predetermined target sinewave current so that the power factor becomes approximately 1, will be described.
A feedforward term 23 is added to the duty command value 22. Here, the feedforward term 23 is a value represented by expression (2) and is determined per drive cycle in accordance with the phase of the AC power supply 1. A duty command value 24 obtained by adding the feedforward term 23 is used as a duty command value for the semiconductor switching element 402a. In addition, a duty command value 25 obtained by subtracting the duty command value 24 for the semiconductor switching element 402a from 1 is used as a duty command value for the semiconductor switching element 401a.
First, a difference 29 between a predetermined DC voltage command value Vdc* for the DC capacitor 5 and voltage Vdc detected by the voltage detector is calculated. Here, the DC voltage command value Vdc* is set to a voltage value higher than the peak voltage of AC voltage inputted from the AC power supply. Using this difference 29 as a feedback amount, PI control is performed to obtain an output current command value 30 for the DC load 10. Using a difference value 31 between the output current command value 30 and a detection value Ibat of DC current as a feedback amount, PI control is performed and a calculation result 32 thereof is inputted to a gain adjuster 33, to generate the D403 command value 34.
Next, processes for generating a gate signal for the semiconductor switching element 401a generated from the duty command value 25 for D401, a gate signal for the semiconductor switching element 402a generated from the duty command value 24 for D402, and gate signals for the semiconductor switching element 403a and the semiconductor switching element 404a generated from the phase shift amount command value 37 for D403, will be described. In the present embodiment, the case of generating these gate signals using a saw-tooth wave as a carrier wave will be described.
As shown in
As shown in
The calculation block diagrams shown in
In the present embodiment, the case of not providing a dead time between the ON period of the semiconductor switching element 401a and the ON period of the semiconductor switching element 402a has been shown. However, the dead time may be provided. Similarly, a dead time may be provided between the semiconductor switching element 403a and the semiconductor switching element 404a.
In the present embodiment, one terminal of the reactor 3 is connected to the positive-side DC output terminal of the rectification circuit 200, and the other terminal of the reactor 3 is connected to the first AC end which is the connection point between the semiconductor switching element 401a and the semiconductor switching element 402a, whereby high-power-factor control is performed using the semiconductor switching elements 401a, 402a. However, the other terminal of the reactor 3 may be connected to the connection point between the semiconductor switching elements 403a and 404a, to perform high-power-factor control using the semiconductor switching elements 403a, 404a. In this case, it suffices that the gate signal to be inputted to the semiconductor switching element 401a is inputted to the semiconductor switching element 403a, and the gate signal to be inputted to the semiconductor switching element 402a is inputted to the semiconductor switching element 404a.
In the case where the reactor 3 is connected to the negative side output DC terminal of the diode rectification circuit or the reactors 3 are distributed and connected to the positive-side and negative-side output DC terminals of the diode rectification circuit, high-power-factor control is performed using the semiconductor switching elements 401a, 402a, and output power control is performed using the semiconductor switching element 403a and the semiconductor switching element 404a.
In the present embodiment, as described above, the ON duties for the semiconductor switching element 401a and the semiconductor switching element 402a are controlled in accordance with the current command value, whereby input current from the AC power supply 1 is adjusted to a predetermined current value and thus the power factor can be controlled to be approximately 1. At the same time, the phase shift amount for the semiconductor switching element 403a and the semiconductor switching element 404a is changed so that DC voltage Vdc of the DC capacitor 5 follows target voltage, whereby DC voltage of the DC capacitor 5 is controlled to be constant, and thus the output power to the DC load can be controlled.
In the configuration of a single full-bridge inverter, the functions of high-power-factor control and output power control are separated for the respective legs, whereby it becomes possible to achieve both high-power-factor control and output power control by a single full-bridge inverter, and thus the entire circuit can be downsized as compared to a conventional method in which two general power converters are provided to achieve high-power-factor control and output power control individually.
The power pulsation pulsating at a frequency twice as high as the AC power supply frequency occurring at the AC power supply 1 is entirely transferred to the DC load 10, and at the DC capacitor 5, voltage ripple occurs only by charging and discharging due to the switching cycle T. In this case, the DC capacitor 5 does not need to bear the power pulsation having a frequency twice as high as the AC power supply frequency, and as compared to the method in which two general power converters are provided and a capacitor is provided at a link portion between the two power converters, the DC capacitor 5 only has to bear charging and discharging due to the switching cycle T. Therefore, the capacitance needed for the DC capacitor 5 can be greatly reduced and the DC capacitor 5 can be downsized.
In addition, the period during which the ON states of the semiconductor switching element 401a and the semiconductor switching element 404a overlap each other, and the period during which the ON states of the semiconductor switching element 402a and the semiconductor switching element 404a overlap each other, are set to be equal to each other, so as to suppress magnetic bias of the transformer 6, whereby more reliable control can be achieved.
In embodiment 1, a saw-tooth wave is used as the carrier signal for ON period control in generation of the gate signals for the semiconductor switching elements 401a to 404a. In embodiment 2, the case of using a triangular wave as the carrier signal for ON period control will be described.
The circuit configuration of the power conversion device and the control method in the present embodiment are the same as those shown in embodiment 1, and the description thereof is omitted. In addition, the duty command value 25 for D401, the duty command value 24 for D402, and the phase shift amount command value 37 for D403 are calculated by the same method as in embodiment 1. That is, the present embodiment is the same as embodiment 1 except for the operation for generating gate signals for the semiconductor switching elements shown in
Processes for generating a gate signal for the semiconductor switching element 401a generated from the duty command value 25 for D401, a gate signal for the semiconductor switching element 402a generated from the duty command value 24 for D402, and gate signals for the semiconductor switching element 403a and the semiconductor switching element 404a generated from the phase shift amount command value 37 in the present embodiment, will be described.
On the basis of the magnitude relationship between the triangular wave 47, and a rectangular wave 48 of which the amplitude from the duty command value 24 for D402 as a reference is equal to the phase shift amount command value for D403, the phase for the semiconductor switching element 403a is shifted relative to the semiconductor switching element 401a, and the phase for the semiconductor switching element 404a is shifted relative to the semiconductor switching element 402a. The value of the rectangular wave is switched between the mountain and valley of the triangular wave. In this case, the first to fourth operation modes defined in
Instead of the rectangular wave 48, two DC signals having the same values as the rectangular wave amplitudes may be used, and the signal to be used for magnitude comparison is switched at the mountain/valley timing of the triangular wave 47, so as to realize a pseudo rectangular wave.
In the present embodiment, since the configuration and the control as described above are used, it is possible to achieve high-power-factor control and output power control at the same time by a single stage of full-bridge inverter circuit, as in the power conversion device shown in embodiment 1.
In the power conversion devices shown in embodiments 1 and 2, during the flow-back period (second operation mode or fourth operation mode) in which the semiconductor switching elements 401a and 403a or the semiconductor switching elements 402a and 404a become ON, since a potential difference occurring between both ends of the transformer 6 is small, the amount of output to the secondary side is small and therefore is not taken into consideration. In the present embodiment, a power conversion device that enables more stable operation while considering a potential difference occurring between both ends of the transformer 6 will be described. It is noted that the configuration of the power conversion device shown in the present embodiment is the same as that shown in
As shown in
The control circuit 11 calculates the time ratio (duty cycle) D401 for the semiconductor switching element 401a, the time ratio (duty cycle) D402 for the semiconductor switching element 402a, and the phase shift amount D403 for the second leg, by the same method as in embodiment 1 and embodiment 2. In the power conversion device shown in the present embodiment, these calculated values are corrected.
By suppressing deviation of the time integral value of current of the smoothing reactor 8, deviation of a product of voltage of the transformer 6 and time is also suppressed. Therefore, the control method using the time integral value of current of the smoothing reactor 8 will be described.
As shown in
A time integral value of current of the smoothing reactor 8 over the period during which the semiconductor switching elements 401a and 404a are ON is defined as ΔTint1, and a time integral value of current of the smoothing reactor 8 over the period during which the semiconductor switching elements 402a and 403a are ON is defined as ΔTint2.
The above four operation mode periods can be represented as shown by the following expressions (11) to (14). It is noted that the initial time t02 is set at 0.
In this case, initial current iLf of the smoothing reactor 8 in each operation mode can be represented as follows.
From the above, each time integral value of current of the smoothing reactor 8 can be represented by expression (19) and expression (20).
From expression (19) and expression (20), deviation ΔIint of the time integral value of current of the smoothing reactor 8 is represented as follows.
In order to suppress magnetic bias of the transformer 6, ΔIint needs to be zero. Therefore, from expression (21), the correction period ΔT1 can be represented as follows.
It is noted that β1 in expression (22) is defined as follows.
Next, the case of considering a correction period ΔT2 for the power transmission period in the second operation sub mode in
The above four operation mode periods can be represented as shown by expressions (24) to (27). It is noted that the initial time t03 is set at 0.
As in the above first operation sub mode, deviation ΔIint of the time integral value of current of the smoothing reactor 8 in the second operation sub mode is represented by expression (28).
As in the above first operation sub mode, in order to suppress magnetic bias of the transformer 6, ΔIint needs to be zero. Therefore, from expression (28), the correction period ΔT2 is represented as follows.
It is noted that β2 and γ2 in expression (29) are defined as follows.
The correction periods of expression (22) and expression (29) can be calculated from detected values of voltage (Vdc) of the DC capacitor 5 and voltage (Vbat) of the smoothing capacitor 9, and calculated values of a current value (iLf) of the smoothing reactor 8, the duty cycle D401 for the semiconductor switching element 401a, the duty cycle D402 for the semiconductor switching element 402a, and the phase shift amount D403 for the second leg, during the device operation. It is noted that the voltage value (Vdc) of the DC capacitor 5 and the voltage value (Vbat) of the smoothing capacitor 9 do not necessarily need to be detected values, but may be target voltages for the respective voltage values, or may be calculated values. In addition, the current value (iLf) of the smoothing reactor 8 does not necessarily need to be a calculated value, but may be a detected value detected by a current detector.
In the above description, the case of correcting the phase shift amount D403 for the second leg has been described. However, the duty cycle (ON period) for the first leg composed of the semiconductor switching element 401a and the semiconductor switching element 402a may be corrected. Also in this case, the duty cycles for the semiconductor switching element 401a and the semiconductor switching element 402a are corrected using similar correction values as in expression (22) and expression (29). That is, the correction of the ON period for the first leg is performed on the basis of the voltage value of the DC capacitor, the voltage value of the smoothing capacitor, the current value of the smoothing reactor, the calculated value of the duty cycle for the first switching element, the duty cycle for the second switching element, and the calculated value of the phase shift amount for the second leg. It is noted that, as described in embodiment 1, the upper limit value of the phase shift amount D403 depends on the duty cycles D401 and D402 for the semiconductor switching elements 401a and 402a, and therefore, in the case where D401 and D402 are corrected, the upper limit value of the phase shift amount D403 is also to be corrected accordingly.
In the present embodiment, processes for generating the gate signal for the semiconductor switching element 401a generated from the duty command value 25 for D401 and the gate signal for the semiconductor switching element 402a generated from the duty command value 24 for D402 are the same as in embodiments 1 and 2, and the description thereof is omitted. In the case where a saw-tooth wave is used as a carrier wave as in embodiment 1, processes for generating the gate signals for the semiconductor switching element 403a and the semiconductor switching element 404a generated from the phase shift amount command value 37 and the correction period for the power transmission period, will be described.
As shown in
In the above gate signal generation processes, a saw-tooth wave is used for a carrier wave as in embodiment 1. However, as shown in embodiment 2, a triangular wave may be used for a carrier wave.
In the present embodiment, the case of not providing a dead time between the ON period of the semiconductor switching element 401a and the ON period of the semiconductor switching element 402a, has been shown. However, the dead time may be provided. Similarly, a dead time may be provided between the semiconductor switching element 403a and the semiconductor switching element 404a.
In the present embodiment, owing to the above configuration, a stable operation in which a magnetic bias phenomenon in the transformer 6 is suppressed is achieved, and in the above configuration and control, as in the power conversion devices shown in embodiments 1 and 2, it is possible to achieve high-power-factor control and output power control at the same time by a single stage of full-bridge inverter circuit.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-015524 | Jan 2017 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2017/002759 | 1/26/2017 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2017/131096 | 8/3/2017 | WO | A |
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