Patent Application
20070279068
The above and other objects, features, and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawing. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following figures:
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. A detailed description of known functions and configurations incorporated herein will be omitted when it may obscure the subject matter of the present invention.
One aspect of the present invention provides a power diagnostic system and method capable of detecting and identifying power cable arcing faults. For parallel and ground-fault arcing, as depicted in
Series fault is detected based on when an open-circuit occurs in the power cables, DC voltage level at the load will decrease. This decrease happens even when the DC voltage at the load is kept constant by a bypass capacitor. For example, the loss of the “hot” side of a 28 VDC load input, with 1000 μF bypass capacitance and with 1 A load current, will drop the DC voltage level by 1 Volt per millisecond, a substantial change that can be detected with even low-precision instrumentation.
Central diagnostic unit 100 includes a processor unit 103, a sampling block 105, and a clock generator 102.
Processor unit 103 executes computer-executable process steps, interfacing with a plurality of sampling blocks (105, 125, 135, and 145), performing sample comparison, fault identification, data logging, and other general “house keeping” functions, as described below.
Clock generator 102 provides a clock reference signal for each of the sampling blocks 105, 125, 135 and 145 to facilitate synchronous sampling action. The sampling blocks 105125, 135 and 145 are phase-locked to the clock reference signal.
Individual sampling blocks 125, 135 and 145, are connected to each load 121, 131 and 141, through power terminals 121A, 131A and 141A respectively forming FRUs 120, 130 and 140. The sampling blocks 105, 125, 135 and 145 are identical in principal, although differences in implementation are possible to make them more adaptable to a particular load.
Sampling blocks 105, 125, 135 and 145 collect voltage and current measurements, synchronously, as controlled by clock generator 102 generated reference signals. The measurements are sent to processor 103 via power cables 104. Processor 103 sums the current measurements and compares that sum to its own measured output current. Processor 103 also compares each of the measured load voltages and compares them, individually, to its own measured output voltage. If either the sum of the load currents or any of the individual load voltages deviate significantly from the output current or output voltage, respectively, a fault condition is detected/identified.
Instrumentation block 113 performs all current and voltage measurements at the respective power terminal. The accuracy and resolution of instrumentation block 113 can be enhanced if needed by using various calibration and compensation techniques. The resolution enhancement features could all be controlled by central diagnostic unit 100.
During voltage measurements, there are two main sources for measurement uncertainty, instrumentation errors, and resolution limitation. Instrumentation errors are due to circuits and circuit components like resistor dividers, amplifiers, A/D converter and others that are used to perform the measurements. The errors in these circuits can be calibrated by providing a voltage reference at each node.
During a series arc event, the input current, in addition to the DC input voltage will drop significantly, this current drop changes the IR drop on the power cables 104. The detection capability is improved by accounting for the IR drop. A measured input current can be used to compute the IR as shown in Equation (1):
V
source
=V
load
+IR Equation (1)
where I is the input current at the load and R is the resistance of the power cables 104.
Fault detection precision is also limited by methodical measurement error. This is cumulative measurement error at N different locations (source plus N−1 loads). Since arcing could cause relatively small amounts of current that may not be distinguishable from large changes in a dominant load, it is important to minimize the accumulated error. In one aspect of the present invention, processor 103 provides compensation to balance source output and load inputs under normal (no fault) operating conditions and by doing so enhances the resolution of the detection system.
The current measurements have an additional source of error originating from the current sensor. Typically, industry grade DC current sensors are capable of 0.5% accuracy over −40° C. to 85° C. temperature range and are hence adequate.
Synchronization block 116 can be implemented using a phase lock loop (PLL) or other synchronous circuits to establish precise sampling times. In the present invention, the phase lock loop with 50 Hz bandwidth has reasonable acquisition times and it is impervious to large spikes and other noise phenomena existing on power cables 104.
Codec block 115 performs data translation between instrumentation block 113 and transceiver block 117. It encodes measurement and status data transmitted by transceiver 117 to processor 103 and decodes commands/instructions received by transceiver 117 from processor 103.
Transceiver block 117 provides a communication means between central diagnostic unit 100 and the plurality of FRU's 120, 130 and 140, using the power cables 104 as communication medium. Orthogonal Frequency-Division Multiplexing (OFDM), Direct-Sequence Spread Spectrum (DSSS) or other modulation techniques can be used to send information from sampling blocks 105, 125, 135, and 145 back to the processor 103 directly on the power cables 104. Such communication would likely incorporate a Forward Error Correction (FEC) scheme in order to avoid “fades” that occurs due to large amplitude spikes on the media. Alternatively, fiber optic cable can be used as the transmission medium. Instead of using power cables 104, sampling blocks can transmit data via connection 104B. Similarly, clock generator 102 can transmit reference signal via connection 104A.
In step 153, the sampled currents and voltages are encoded. In step 154, the encoded data is transmitted to central diagnostic unit 100. The data is received in step 154, and in step 155, the encoded data is decoded.
In step 156, load currents are summed by processor 103, if needed, compensation can be applied, and then currents are compared. In one aspect, Iload is sum of all the measured currents and it is compared to the current that was supplied by power supply 101 (Isupply).
If the sum of the measured currents deviates from the source current beyond a threshold limit, then in step 157, ground/parallel arcing is detected. For example, if the difference between the measured current and supplied current is IΔ and it exceeds a predetermined value, then it denotes that ground/parallel fault condition exists. IΔ is computed by using Equation (2):
I
Δ
=I
supply
−I
load Equation (2)
As stated above, Isupply is the current provided by the power supply 101 and Iload is the sum of all of all the load currents.
After the current compare, the voltage samples are compared in step 158. Comparison results are the basis serial arcing detection and identification.
When the voltage difference of any consecutive sample exceeds a predetermined value, serial arcing is detected, as shown in step 159. This voltage difference is expressed by Equation (3):
V
Δ
=V
n-1
−V
n Equation (3)
where Vn-1 and Vn are any two consecutively taken voltage readings
The present invention provides numerous advantages over previous approaches to power diagnosis. Measurements are performed at loads and at power supply, providing better accuracy enhancing the fault detection capability. Data collection method is tolerant of noise on the transmission medium. Having a central processor unit makes the system more flexible and more economical to implement. Furthermore, additional cables are not needed and hence is very useful in weight sensitive operations (for example, aircrafts, space shuttle and others).
Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.
