Claims
- 1. A Power-Down-Miller-Killer circuit for guarding an output pulldown transistor of an output buffer capable of current-sourcing and current-sinking at a signal output V.sub.OUT, said Power-Down-Miller-Killer circuit comprising,
- (a) a Power-Down-Miller-Killer-driver-transistor having a control gate coupled to a high potential power rail V.sub.CC and with primary current path between said output V.sub.OUT and a control node of
- (b) a Power-Down-Miller-Killer-transistor with primary current path between a control node of said output pulldown transistor and a low potential power rail GND,
- (c) a Power-Down-Miller-Killer-disabler means for ensuring that when said buffer is in an active current-sinking state, said Power-Down-Miller-Killer-transistor is not conducting.
- 2. A Power-Down-Miller-Killer circuit as described in claim 1 wherein
- (a) said output pulldown transistor is a bipolar transistor,
- (b) said Power-Down-Miller-Killer-driver-transistor is a MOS transistor with a control gate coupled to said high potential power rail V.sub.CC and a primary current path between said output V.sub.OUT and a control gate of said Power-Down-Miller-Killer-transistor, and
- (c) said Power-Down-Miller-Killer-transistor is a MOS transistor coupled between a base node of said output pulldown transistor and said low potential power rail GND.
- 3. A Power-Down-Miller-Killer circuit as described in claim 2 wherein said output buffer also comprises an input V.sub.IN coupled to a CMOS pulldown-driver-input-inverter-stage, and wherein said Power-Down-Miller-Killer-disabler means comprises a MOS transistor having primary current path between said control gate of said Power-Down-Miller-Killer-transistor and said low potential power rail GND and having a control gate node coupled to an output of said pulldown-driver-input-inverter-stage.
- 4. A Power-Down-Miller-Killer circuit as described in claim 1 wherein
- (a) said output pulldown transistor is a MOS transistor,
- (b) said Power-Down-Miller-Killer-driver transistor is a MOS transistor coupled between said high potential power rail V.sub.cc and a control gate of said Power-Down-Miller-Killer transistor, and
- (c) said Power-Down-Miller-Killer transistor is a MOS transistor coupled between a control gate node of said output pulldown transistor and said low potential power rail GND.
- 5. A Power-Down-Miller-Killer circuit as described in claim 4 wherein said output buffer also comprises an input V.sub.in coupled to MOS pulldown-driver-input-inverter stage, and wherein said Power-Down-Miller-disabler means comprises a MOS transistor having primary current path between said control gate of said Power-Down-Miller-Killer transistor and said low potential power rail GND and having a control gate node coupled to an output of said pulldown-driver-input-inverter stage.
- 6. A Power-Down-Miller-Killer circuit as described in claim 1 wherein
- (a) said output pulldown transistor is a bipolar transistor Q44,
- (b) said Power-Down-Miller-Killer-driver-transistor is a PMOS transistor Q99A with a control gate coupled to said high potential power rail V.sub.CC and primary current path between said output V.sub.out and a control gate of said Power-Down-Miller-Killer-transistor, and
- (c) said Power-Down-Miller-Killer-transistor is an NMOS transistor Q99 coupled between a base node of said bipolar transistor Q44 and said low potential power rail GND.
- 7. A Power-Down-Miller-Killer circuit as described in claim 6 wherein said output buffer also comprises an input V.sub.IN coupled to a CMOS pulldown-driver-input-inverter-stage, and wherein said Power-Down-Miller-Killer-disabler means comprise an NMOS transistor Q98 having primary current path between said control gate of said Power-Down-Miller-Killer transistor and said low potential power rail GND and having a control gate node coupled to an output of said pulldown-driver-input-inverter-stage.
- 8. A Power-Down-Miller-Killer circuit as described in claim 1 wherein
- (a) said output pulldown transistor is an NMOS transistor Q100,
- (b) said Power-Down-Miller-Killer-driver transistor is a PMOS transistor Q99A coupled between said high potential power rail V.sub.CC and a control gate of said Power-Down-Miller-Killer transistor, and
- (c) said Power-Down-Miller-Killer transistor is a PMOS transistor coupled between a control gate node of said output pulldown transistor and said low potential power rail GND.
- 9. A Miller Killer improvement for a BiCMOS tristate output buffer circuit for delivering output signals of high and low potential levels at an output V.sub.out in response to data signals at an input V.sub.in, comprising
- (a) a relatively high-current-capacity bipolar primary-output-pulldown-transistor Q44 having a primary current path through collector and emitter nodes coupled for sinking current from said output V.sub.out to a low potential power rail GND, a MOS output-pulldown-driver-transistor Q60 coupled between a high potential power rail V.sub.cc and a base node of said bipolar primary-output-pulldown-transistor Q44, and having a control gate node coupled to said input V.sub.in through an input circuit, and
- (b) a CMOS pulldown-predriver-input-stage incorporating an NMOS transistor Q10 and a PMOS transistor Q11 with common control gate nodes coupled to said input V.sub.in,
- said Miller Killer improvement being a circuit for diverting and discharging base/collector-capacitive-feedback-Miller-Current from said base node of said bipolar primary-output-pulldown-transistor Q44 and comprising:
- (a) a Power-Down-Miller-Killer-driver-transistor Q99A having a control gate coupled to said high potential rail V.sub.cc and having a primary current path through drain and source nodes coupled between said output V.sub.out and a control gate of a Power-Down-Miller-Killer-transistor Q99, wherein said Power-Down-Miller-Killer-transistor Q99 has a primary current path through drain and source nodes coupled between a base node of said bipolar primary-output-pulldown-transistor Q44 and said low potential power rail GND, and
- (b) a Power-Down-Miller-Killer-disabler means for ensuring that when said tristate output buffer is active and in the logic low output state said Power-Down-Miller-Killer-transistor Q99 is not conducting.
- 10. The Miller Killer improvement as set out in claim 9 wherein said disabler means comprises a disabler transistor Q98 having primary current path through drain and source nodes coupled between said control gate of said Power-Down-Miller-Killer-transistor Q99 and said low potential power rail GND and having a control gate node coupled to said output of said pulldown-predriver-input-stage Q11,Q10.
- 11. A Power-Down-Miller-Killer circuit, used in combination with a pulldown output transistor of a tristate output buffer coupled between a high potential power rail V.sub.CC and a low potential power rail GND and with a buffer output V.sub.OUT coupled to a common bus, for discharging from a base node of said pulldown output transistor a capacitive feedback Miller current generated by an L.fwdarw.H transition at said common bus when said tristate output buffer is powered down, comprising
- a) a MOS Miller Killer transistor having a primary current path through drain and source nodes coupled between said base node of said pulldown output transistor and said low potential power rail GND, and having a control gate coupling means, connected to a drain node of a Power-Down-Miller-Killer-driver, which permits said Miller Killer transistor to conduct only when said high potential power rail V.sub.CC has been reduced significantly below its normal operating potential, and
- (b) a disabler transistor having primary current path between said control gate of said Power-Down-Miller-Killer-transistor and said low potential power rail GND and having a control gate node coupled to an output of a pulldown-predriver-input-stage, for ensuring that said Miller Killer transistor is non-conducting when said tristate output buffer is in its active low state, regardless of the potential of said high potential power rail V.sub.CC.
- 12. A BiCMOS output buffer circuit for delivering output signals of high and low potential levels at an output V.sub.OUT in response to data signals at an input V.sub.IN, a relatively large-current-capacity bipolar primary-output-pulldown-transistor Q44 having a primary current path through collector and emitter nodes coupled for sinking current from said output V.sub.OUT to a low potential power rail GND, a MOS output pulldown driver transistor Q60 having a primary current path through drain and source nodes coupled to a base node of said bipolar primary-output-pulldown-transistor Q44 and a control gate node coupled to said input V.sub.IN and having a CMOS Power-Down-Miller-Killer circuit comprising
- (a) a Power-Down-Miller-Killer-driver-transistor Q99A having a control gate coupled to said high potential rail V.sub.CC and a primary current path coupled between said output V.sub.OUT and a control gate of
- (b) a Power-Down-Miller-Killer-transistor Q99 with a primary current path coupled between a base node of said primary-output-pulldown-transistor Q44 and said low potential power rail GND, and
- (c) a Power-Down-Miller-Killer-disabler means for ensuring that when said BiCMOS tristate output buffer is current sinking, said Power-Down-Miller-Killer-transistor Q99 is non-conducting.
- 13. A BiCMOS tristate output buffer as set out in claim 12, wherein said output buffer also comprises a CMOS pulldown-driver-input-inverter-stage, an input to which is coupled to said input V.sub.IN and wherein said Power-Down-Miller-Killer-disabler means comprises a disabler-transistor having primary current path coupled between said control gate of said Power-Down-Miller-Killer-transistor and said low, potential power rail GND, wherein a control gate node of said disabler-transistor is coupled to an output of said pulldown-driver-input-inverterstage.
- 14. A BiCMOS tristate output buffer as set out in claim 13, wherein said high potential power rail V.sub.CC is divided into (a) a quiet high potential power rail V.sub.CCQ for powering input stages of said tristate output buffer, said input stages comprising a pullup-predriver-input-stage, Q14, Q15 and an input-inverterstage Q11, Q12, and (b) a "noisy" high potential power rail V.sub.CCN for supplying current for current-sourcing circuitry and wherein said low potential power rail GND is divided into (a) a quiet low potential power rail GNDQ forming a low potential power rail for said input stages of said tristate output buffer and (b) a noisy low potential power rail GNDN for sinking current from said primary-output-pulldown-transistor Q44, and wherein said Power-Down-Miller-Killer-transistor Q99 and said Power-Down-Miller-Killer-disabler-transistor Q98 both sink current to said noisy low potential power rail GNDN while having bulks coupled to said quiet low potential power rail GNDQ, and wherein said control gate of said Power-Down-Miller-Killer-driver-transistor Q99A is coupled to said quiet high potential power rail V.sub.CCQ.
- 15. A Miller Killer improvement for a BiCMOS tristate output buffer circuit for delivering output signals of high and low potential levels at an output V.sub.out in response to data signals at an input V.sub.in, comprising
- (a) a MOS output-pulldown-transistor Q100 having a primary current path through source and drain nodes coupled for sinking current from said output V.sub.out to a low potential power rail GND, a MOS output-pulldown-driver-transistor Q60 coupled between a high potential power rail V.sub.CC and a control gate node of said MOS output-pulldown-transistor Q100, and having a control gate node coupled to said input V.sub.in through an input circuit, and
- (b) a CMOS pulldown-predriver-input-stage incorporating NMOS transistor Q10 and a PMOS transistor Q11 with common control gate nodes coupled to said input V.sub.in,
- said Miller Killer improvement being a circuit for diverting and discharging parasitic feedback current from said MOS output-pulldown-transistor Q100 and comprising:
- (a) a Power-Down-Miller-Killer-driver-transistor Q99A having a control gate coupled to said high potential rail V.sub.cc and having a primary current path through drain and source nodes coupled between said output V.sub.out and a control gate of a Power-Down-Miller-Killer-transistor Q99, wherein said Power-Down-Miller-Killer-transistor Q99 has a primary current path through drain and source nodes coupled between said control gate node of said CMOS output-pulldown-transistor Q100 and said low potential power rail GND, and
- b) Power-Down-Miller-Killer-disabler means for ensuring that when said tristate output buffer is active and in the logic low output state said Power-Down-Miller-Killer-transistor Q99 is not conducting.
- 16. The Miller Killer improvement as set out in claim 15 wherein said Power-Down-Miller-Killer-disabler comprises a disabler transistor Q98 having primary current path through drain and source nodes coupled between said control gate of said Power-Down-Miller-Killer-transistor Q99 and said low potential power rail GND and having a control gate node coupled to said output of said pulldown-predriver-input-stage Q11, Q10.
- 17. A Power-Down-Miller-Killer circuit for discharging from said pulldown output transistor a capacitive feedback Miller current generated by a L.fwdarw.H transition at said common bus when said tristate output buffer is powered down, used in combination with a pulldown output transistor of a tristate output buffer coupled between a high potential power rail V.sub.CC and a low potential power rail GND and with a buffer output V.sub.OUT coupled to a common bus, said Power-Down-Miller-Killer circuit comprising
- (a) a MOS Miller Killer transistor having a primary current path through drain and source nodes coupled between a control gate node of said pulldown output transistor and said low potential power rail GND, and having a control gate coupling means which permits said Miller Killer transistor to conduct only when said high potential power rail V.sub.CC has been reduced significantly below its normal operating potential, and
- (b) a disabler transistor Q98 having primary current path coupled between said control gate of said Power-Down-Miller-Killer-transistor Q99 and said low potential power rail GND and having a control gate node coupled to an output of said pulldown-predriver-input-stage Q11, Q10, for ensuring that said Miller Killer transistor is non-conducting when said tristate output buffer is in its active low state, regardless of the potential of said high potential power rail V.sub.CC.
- 18. A BiCMOS output buffer circuit for delivering output signals of high and low potential levels at an output V.sub.OUT in response to data signals at an input V.sub.IN, a MOS output-pulldown-transistor Q100 having a primary current path through source and drain nodes coupled for sinking current from said output V.sub.OUT to a low potential power rail GND, a MOS output pulldown driver transistor Q60 having a primary current path through drain and source nodes coupled to a control gate node of said MOS output-pulldown-transistor Q100 and a control gate node of said MOS output pulldown driver transistor Q60 coupled to said input V.sub.IN, and having a MOS Power-Down-Miller-Killer circuit comprising
- (a) a Power-Down-Miller-Killer-driver-transistor Q99A having a control gate coupled to said high potential rail V.sub.CC and a primary current path coupled between said output V.sub.OUT and a control gate of
- (b) a Power-Down-Miller-Killer-transistor Q99 with a primary current path coupled between a control gate node of said MOS output-pulldown-transistor Q100 and said low potential power rail GND, and
- (c) a Power-Down-Miller-Killer-disabler means for ensuring that when said BiCMOS tristate output buffer is current sinking, said Power-Down-Miller-Killer-transistor Q99 is non-conducting.
- 19. A BiCMOS tristate output buffer as set out in claim 18, wherein said output buffer also comprises a CMOS pulldown-driver-input-invertor-stage, an input to which is coupled to said input V.sub.IN and wherein said Power-Down-Miller-Killer-disabler means comprises a disabler-transistor having primary current path coupled between said control gate of said Power-Down-Miller-Killer-transistor and said low potential power rail GND, wherein a control gate node of said disabler-transistor is coupled to an output of said pulldown-driver-input-invertor-stage.
- 20. A BiCMOS tristate output buffer as set out in claim 19, wherein said high potential power rail V.sub.CC is divided into (a) a quiet potential power rail V.sub.CCQ for powering input stages of said tristate output buffer, said input stages comprising a pullup-predriver-input stage, Q14, Q15 and an input-inverter-stage Q11, Q12, and (b) a "noisy" high potential power rail V.sub.CCN for supplying current for current sourcing circuitry and wherein said low potential power rail GNDQ forming a low potential power rail for said input stages said tristate output buffer and (b) a noisy low potential power rail GNDN for sinking current from said output-pulldown-transistor Q100, and wherein said Power-Down-Miller-Killer-transistor Q99 and said disabler-transistor Q98 both sink current to said noisy low potential GNDN while having bulks coupled to said quiet low potential power rail GNDQ, and wherein said control gate of said Power-Down-Miller-Killer-driver-transistor Q99 is coupled to said quiet high potential power rail V.sub.CCQ.
Parent Case Info
This is a continuation-in-part of application Ser. No. 803,201, filed Dec. 6, 1991, now abandoned.
US Referenced Citations (9)
Continuation in Parts (1)
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Number |
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803201 |
Dec 1991 |
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