Patent Application
20130249504
(1) Field of the Invention
This invention relates to a power factor correction (PFC) controller and application circuits with the same, and particularly relates to a PFC controller for a bridgeless PFC circuit.
(2) Description of the Prior Art
Environmental protection and power conservation has become an important issue nowadays. The trend of improving power efficiency of isolated ac power suppliers is directed to the development of topologies of secondary side synchronous rectifier control and primary side power factor correction (PFC) control.
As shown, during the positive half cycles of the ac voltage input from the ac power source, the current flows from the ac power source, through the diode d1, the inductor Li, the turned-on switching unit sw0, the diode d4, and back to the ac power source. As the switching unit sw0 is turned off, the inductor Li releases energy to establish an energy-releasing current flowing from the inductor Li, through the diode do, load Ro, diode d4, ac power source, diode d1, and back to the inductor Li. During the negative half cycles of the ac voltage input from the ac power source, the current flows from the ac power source, through the diode d2, the inductor Li, the turned-on switching unit sw0, and the diode d3, and back to the ac power source. As the switching unit sw0 is turned off, the inductor Li releases energy to establish an energy-releasing current flowing from the inductor Li, through the diode do, load Ro, diode d3, ac power source, diode d2, and back to the inductor Li.
The application of power factor correction topology nowadays is deviated to bridgeless designs. Bridgeless PFC topology combined the separated bridge rectifier control and PFC control in the traditional topology into a common circuit such that rectifying voltage drop in the bridge rectifier can be reduce to enhance overall power efficiency.
During the negative half cycles of the ac voltage input from the ac power source, the current flows from the ac power source, through the conducted switching units sw2 and sw1, the inductor Li, and back to the ac power source for charging the inductor Li. As the switching units sw1 and sw2 are turned off, the inductor Li releases energy to establish an energy-releasing current flowing from the inductor Li, through the ac power source, the diode d6, the load Ro, the body diode ds1 of the switching unit sw1, and back to the inductor Li.
For a bridge PFC application circuit, there needs two diodes on the current path for bridge rectifying. Conduction loss from the diodes may affect overall conversion efficiency. In contrast, bridgeless PFC application circuits have the advantage of fewer rectifying diodes on the current path and thus voltage drop and energy loss from the diode can be effectively reduced.
As shown, during the positive half cycles of the ac voltage input from the ac power source, the current flows from the ac power source, through the inductor Li, the conducted switching unit sw4 and the diode d8, and back to the ac power source for charging the inductor Li as the switching unit sw3 is turned off. On the other hand, as the switching unit sw4 is turned off and the switching unit sw3 is turned on, the energy-releasing current generated by the inductor Li flows from the inductor Li, through the conducted switching unit sw3, the load Ro, the diode d8, and back to the inductor Li.
During the negative half cycles of the ac voltage input provided by the ac power source, the current flows from the ac power source, through the diode d7, the conducted switching unit sw3, the inductor Li, and back to the ac power source for charging the inductor Li as the switching unit sw4 is turned off. On the other hand, as the switching unit sw3 is turned off and the switching unit sw4 is turned on, the energy-releasing current generated by the inductor Li flows from the inductor Li, through the ac power source, the diode d7, the load Ro, the conducted switching sw4, and back to the inductor Li.
The inductor Li in the aforementioned two bridgeless PFC application circuits needs to be charged and discharged no matter during the positive half cycles output or the negative half cycles output from the ac power source. That is, the switching units sw1, sw2, sw3, sw4 should be adequately controlled during both half cycles. Thus, the difficulty for detecting inductor current and current state of the switching unit to properly control the switching units sw1, sw2, sw3, and sw4 is unpreventable.
It is a main object of the present invention to provide a PFC control circuit, which is capable to detect inductor current of both directions attended with the positive and negative half cycles of the output from the ac power source.
It is another object of the present invention to provide a PFC controller, which is able to detect conductive current of the switching unit on matter during the positive half cycles or the negative half cycles of the output from the ac power source.
According to an embodiment of the present invention, a power factor correction (PFC) controller for controlling at least a switching unit is provided. The PFC controller includes a feedback control circuit, a conductive current detecting circuit, and a switching control circuit. The feedback control circuit generates a feedback control signal for controlling the switching unit according to a feedback voltage signal. The conductive current detecting circuit includes a second clamp circuit, which generates a second clamped signal restricted in a positive potential varying range at least according to a negative potential portion of a conductive-current detecting signal, and generates a cutoff signal to turn off the switching unit at least according to the second clamped signal. The switching control circuit is utilized for turning off the switching unit according to the feedback control signal and the cutoff signal.
According to another embodiment of the present invention, a bridgeless PFC circuit is provided. The bridgeless PFC circuit includes a converting circuit, a switching unit current detector, and a PFC controller. The converting circuit has a high-side line and a low-side line and also includes a first high-side rectifier unit, a first low-side rectifier unit, a second high-side rectifier unit, a second low-side rectifier unit, at least an inductor, and an output capacitor. The first high-side rectifier unit and the first low-side rectifier unit are serially connected between the high-side line and the low-side line and a first node is defined on a circuit between the first high-side rectifier unit and the first low-side rectifier unit. The second high-side rectifier unit and the second low-side rectifier unit are serially connected between the high-side line and the low-side line and a second node is defined on a circuit between the second high-side rectifier unit and the second low-side rectifier unit. The inductor is connected between a power source and the first node. The inductor and the power source are serially connected between the first node and the second node. The output capacitor is connected between the high-side line and the low-side line. At least one of the first high-side rectifier unit, the first low-side rectifier unit, the second high-side rectifier unit, and the second low-side rectifier unit is a switching unit.
The switching unit current detector is connected to the switching unit for detecting a conductive current flowing through the switching unit to generate a conductive-current detecting signal. The PFC controller includes a feedback control circuit, a conductive current detecting circuit, and a switching control circuit. The feedback control circuit generates a feedback control signal for controlling the switching unit according to a feedback voltage signal with respect to an output voltage of the converting circuit. The conductive current detecting circuit includes a second clamp circuit, which generates a second clamped signal restricted in a positive potential varying range at least according to a negative potential portion of the conductive-current detecting signal, and generates a cutoff signal for turning off the switching unit at least according to the second clamped signal. The switching control circuit is utilized for turning off the switching unit according to the feedback control signal and the cutoff signal.
The present invention will now be specified with reference to its preferred embodiment illustrated in the drawings, in which:
The DC-to-DC converter circuit includes an inductor L1, a switching unit Q1, a diode D1, a capacitor C1, a switching unit current detector 170, an auxiliary inductor L2, a voltage divider composed of resistors R2 and R3, and a PFC controller 160. The switching unit current detector 170 includes a resistor serially connected to the switching unit Q1 for detecting the conductive current flowing through the switching unit Q1 so as to generate a conductive-current detecting signal VCS. The auxiliary inductor L2 is utilized for detecting the inductor current on the inductor L1 so as to generate an inductor current detecting signal VZCD. To prevent the inductor current detecting signal VZCD from being directly fed into the PFC controller 160 to damage or error, a resistor Rb is connected between the auxiliary inductor L2 and the PFC controller 160. The voltage divider converts the output voltage Vo of the DC-to-DC converter circuit into a feedback voltage signal VFB and has the feedback voltage signal VFB fed to the PFC controller 160 for feedback control. In conclusion, the PFC controller 160 in the present embodiment controls the switching unit Q1 based on three detecting signals, the conductive current of the switching unit Q1 detected by using the switching unit current detector 170, the output voltage Vo detected by using the voltage divider, and the inductor current on the inductor L1 detected by using the auxiliary inductor L2.
The converting circuit has a high-side line HL and a low-side line LL. In the present embodiment, the low-side line LL is grounded. The converting circuit also has a first high-side rectifier unit DH1, a first low-side rectifier unit QL1, a second high-side rectifier unit DH2, a second low-side rectifier unit QL2, an inductor L1, and an output capacitor C1. The first high-side rectifier unit DH1 and the first low-side rectifier unit QL1 are serially connected between the high-side line HL and the low-side line LL. A first node N1 is defined on the circuit between the first high-side rectifier unit DH1 and the first low-side rectifier unit QL1. The second high-side rectifier unit DH2 and the second low-side rectifier unit QL2 are serially connected between the high-side line HL and the low-side line LL also and a second node N2 is defined on the circuit between the second high-side rectifier unit DH2 and the second low-side rectifier unit QL2. The inductor L1 is connected between the ac power source and the first node N1. In addition, the ac power source and the inductor L1 are serially connected between the first node N1 and the second node N2. The output capacitor C1 is connected between the high-side line HL and the low-side line LL.
In the present embodiment, the first high-side rectifier unit DH1 and the second high-side rectifier unit DH2 are two diodes forwardly biased between the first node N1 and the high-side line HL as well as the second node N2 and the high-side line HL. The first low-side rectifier unit QL1 and the second low-side rectifier unit QL2 are two switching units. Thus, the topology of the converting circuit in the present embodiment is similar to that shown in
As shown in
In the present embodiment, the first comparator COM1 receives the first clamped signal VZCD′ at a positive input thereof and a first reference level Vr1 at a negative input thereof for generating a first comparing signal VCOM1. The second comparator COM2 receives the first clamped signal VZCD′ at a negative input thereof and a second reference level Vr2 at a positive input thereof for generating a second comparing signal VCOM2. The first logic circuit 424 receives the first comparing signal VCOM1 and the second comparing signal VCOM2 so as to generate the zero-current signal SZC.
In the present embodiment, the first logic circuit 424 has a first one-shot circuit OS1, a second one-shot circuit 0S2, and an OR gate OR1. The first one-shot circuit OS1 receives the first comparing signal VCOM1 and generates a first pulse signal PUL1 according to a level switching time of the first comparing signal VCOM1. The second one-shot circuit OS2 receives the second comparing signal VCOM2 and generates a second pulse signal PUL2 according to a level switching time of the second comparing signal VCOM2. The OR gate OR1 receives the first pulse signal PUL1 and the second pulse signal PUL2 so as to generate the zero-current signal SZC.
Referring to
The level of the inductor current detecting signal VZCD is dependent to the level of the AC voltage input. The usage of the first clamp circuit 422 for converting the inductor current detecting signal VZCD into the first clamped signal VZCD′ is also to shrink the potential varying range of the inductor current detecting signal VZCD to facilitate flowing operations in the PFC controller 400.
As the level of the first clamped signal VZCD′ rises over the first reference level Vr1, the first comparing signal VCOM1 outputted by the first comparator COM1 would be switched from low to high. The first one-shot circuit OS1 senses level switching of the first comparing signal VCOM1 and generates the first pulse signal PUL1 immediately to raise gate voltage VG of the switching units QL1 and QL2 from low to high to turn on the switching units QL1 and QL2. Then, the ac power source begins charging the inductor L1.
The above mentioned embodiment turns on the switching units QL1 and QL2 according to the comparing result of the first comparator COM1 based on the first clamped signal VZCD′ and the first reference level Vr1. However, the present invention is not so restricted. As shown in
Referring to
When the first clamped signal VZCD′ drops below the second reference level Vr2, the second comparing signal VCOM2 outputted by the second comparator COM2 is switched from low to high. The second one-shot circuit OS2 senses the switching of the second comparing signal VCOM2 and generates the second pulse signal PUL2 to turn on the switching units QL1 and QL2 immediately. Then, the ac power source AC begins charging the inductor L1.
The above mentioned embodiment achieves the object of controlling the timing to turn on the switching units QL1 and QL2 by using the second comparator COM2 to compare the first clamped signal VZCD′ and the second reference level Vr2. However, the present invention is not so restricted. As shown in
The zero-current detecting circuit 420 detects a first portion of the inductor current detecting signal VZCD with respect to the negative half cycle of the ac voltage input and a second portion thereof with respect to the positive half cycle of the ac voltage input by using the first comparator COM1 and the second comparator COM2 respectively. Thus, the difficulty of detecting inductor current with both directions can be resolved.
The conductive current detecting circuit 440 includes a second clamp circuit 442, a third comparator COM3, a fourth comparator COM4, and a second logic circuit 444. The second clamp circuit 442 generates a second clamped signal VCS′ restricted in a positive potential range at least according to a negative potential portion of a conductive-current detecting signal VCS. The conductive current detecting circuit 440 generates a cutoff signal SCS to turn off the switching units QL1 and QL2 according to the second clamped signal VCS′. The third comparator COM3 receives the second clamped signal VCS′ and a third reference level Vr3 for generating a third comparing signal VCOM3. The fourth comparator COM4 receives the conductive-current detecting signal VCS and a fourth reference level Vr4 for generating a fourth comparing signal VCOM4. The above mentioned third reference level Vr3 and the fourth reference level Vr4 may be identical or not. In the present embodiment, the third reference level Vr3 and the fourth reference level Vr4 are designated with an identical level for simplifying circuit design. The second logic circuit 444 receives the third comparing signal VCOM3 and the fourth comparing signal VCOM4 so as to generate the cutoff signal SCS to turn off the switching units QL1 and QL2.
In the present embodiment, the second clamp circuit 442 is a level shifter for raising the whole negative potential portion of the conductive-current detecting signal VCS with a predetermined level Va so as to generate a second clamped signal VCS′, which is varying within the potential range above zero, and the resulted level equals to the sum of VCS and Va.
Referring to
After the switching units QL1 and QL2 are turned on (the gate voltage VG is high), the power source AC begins charging the inductor L1 through the switching units QL1 and QL2. At this time, the level of the conductive-current detecting signal VCS would be gradually declined attending with increasing of the absolute value of the input current lin. As the second clamped signal VCS′ drops to a level lower than the third reference level Vr3, the third comparator COM3 outputs the high level third comparing signal VCOM3 to cut off the switching units QL1 and QL2.
Also referring to
On the other hand, as shown in
Back to
The switching control circuit 460 of the PFC controller 400 has a flip-flop. The set and reset inputs of the flip flop receives the zero-current signal SZC and the cutoff signal SCS respectively, and the inverted output QB of the flip-flop outputs a driving signal DRV to control on/off state of the switching units QL1 and QL2. In the present embodiment, the level of the driving signal DRV is reversely related to the gate voltage of the switching units QL1 and QL2. However, the present invention is not so restricted. The non-inverted output of the flip-flop or both the inverted and non-inverted outputs of the flip-flop may be used for providing the driving signal DRV if the driving circuit connected to the switching control circuit 460, the switching unit, or the converting circuit topology are changed.
The condition the PFC controller of
During the positive half cycle of the ac voltage input VAC, the level of the conductive-current detecting signal VCS would be gradually increased attending with the increasing of conductive current flowing through the switching units QL1 and QL2. At this time, the second clamped signal VCS′ generated by the second clamp circuit 442 would be maintained above the third reference level Vr3, and the third comparator COM3 may consistently output the low level third comparing signal VCOM3. However, the level of the fourth reference level Vr4 is designated as located in the potential varying range of the conductive-current detecting signal VCS. As the conductive-current detecting signal VCS is raised above the fourth reference level Vr4, the fourth comparator COM4 may output the fourth comparing signal VCOM4 to turn off the switching units QL1 and QL2.
During the negative half cycle of the ac voltage input VAC, the conductive-current detecting signal VCS is negative and would be more negative attending with the increasing of conductive current flowing through the switching units QL1 and QL2. Meanwhile, the level of the conductive-current detecting signal VCS would be kept below the fourth reference level Vr4 and the fourth comparator COM4 may consistently output the low level fourth comparing signal VCOM4. On the other hand, for the third comparator COM3, the level of the conductive-current detecting signal VCS would be raised by the second clamp circuit 442 so as to generate the second clamped signal VCS′, and the third reference level Vr3 should be designate as located in the potential varying range of the second clamped signal VCS′. As the level of the second clamped signal VCS′ is declined below the third reference level Vr3, the third comparator COM3 would output the high level third comparing signal VCOM3 to turn off the switching units QL1 and QL2.
As mentioned above, the conductive current detecting circuit 440 of the present embodiment detects conductive current flowing through the switching units QL1 and QL2 with respective to positive half cycle and negative half cycle of the ac voltage input VAC by using the third comparator COM3 and the fourth comparator COM4 respectively such that the difficulty for traditional PFC control to detect conductive current flowing through the switching units QL1 and QL2 with both directions can be resolved.
In the embodiment shown in
The clamp circuits applied in the zero-current detecting circuit 420 and the conductive current detecting circuit 440 may be chosen according to the level of the signals to be detected, the potential varying range, the reference level, and etc., and should not be so restricted. In addition, since the waveform of the conductive-current detecting signal generated by the switching unit current detector 370 in the embodiment of
The PFC controller described in the present invention can be applied to not only the bridgeless PFC application circuit as shown in
No matter during the positive half cycle or the negative half cycle of the ac voltage input, the PFC controller is able to detect the inductor current and the conductive current flowing through the switching unit effectively. Thus, the controlling issues for bridgeless PFC applications can be solved. In addition, the PFC controller provided in the present invention can be also used to control the traditional full-bridge PFC converter in addition to the PFC bridgeless converter.
While the preferred embodiments of the present invention have been set forth for the purpose of disclosure, modifications of the disclosed embodiments of the present invention as well as other embodiments thereof may occur to those skilled in the art. Accordingly, the appended claims are intended to cover all embodiments which do not depart from the spirit and scope of the present invention.
