Power-gating instruction scheduling for power leakage reduction

Abstract

A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method of reducing power leakage in processors or ICs, and in particular to a method of power-gating instruction scheduling for power leakage reduction.

2. Description of the Related Art

Overall power dissipation in semiconductor application comprises static power dissipation and dynamic power dissipation, generated by current leakage and switching transient current in complementary metal oxides semiconductor (CMOS) circuits, respectively. As semiconductor technology continues to scale down to deep-submicron levels, power leakage gains more significance in the total power dissipation.

In recent years, many power-gating mechanisms have been developed and employed to reduce the static power loss generated by the current leakage in CMOS circuits. The power-gating mechanisms insert power-gating instructions into a program to reduce power leakage of power-gated components in the processor. The power-gating instructions comprise power-off and power-on instructions to shut down inactive power-gated components.

ROC. Pat. Pub. No. 00519599 discloses architecture and complier solutions to employ a power-gating mechanism to reduce the current leakage in power-gated components of a processor executing a program. The power-gating mechanism analyzes utilization of the power-gated components by data-flow analysis on the basis of the program and then inserts power-off and power-on instructions into the program to shut down the inactive power-gated components.

However, the power-off and power-on instructions increase execution time of the program and increase code size. With the development of semiconductor manufacturing technologies, the increasing number of power-gated components in a processor aggravates the above drawbacks. Moreover, fetching and decoding of power-gating instructions, and shut-down and wake-up procedures all results in power loss. Power loss from wake-up is derived from peak-voltage requirements. Therefore, it is advantageous necessary to reduce power-gating instructions.

BRIEF SUMMARY OF THE INVENTION

The invention provides a method of reducing power-gating instructions without increasing power loss. By postponing the power-off instruction to other blocks and advancing the power-on instructions to other blocks, the combined power-gating instructions are merged as one compound power-gating instruction, enabling power reduction and reducing code size. The invention provides a method of power-gating instruction scheduling for power leakage reduction comprising receiving a program, generating a control-flow graph which divides the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions into one compound power-off instruction and merging the power-on instructions into one compound power-on instruction and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

The invention also provides a system of power-gating instruction scheduling for reducing power leakage, receiving a program, generating a power-gated program comprising power-gating instructions, and comprising a control-flow graph construction module, generating a control-flow graph by dividing the program into a plurality of blocks and linking the blocks according to the program, wherein the control-flow graph contains control commands, a utilization analysis module, analyzing utilization of power-gated components of a processor executing the program, a first power-gating instruction placement generator, generating first power-gating instruction placement based on the control-flow graph and the utilization of the power-gated components, the first power-gating instruction placement comprising a plurality of power-off instructions and a plurality of power-on instructions to shut down inactive power-gated components, a second power-gating instruction placement generator, generating second power-gating instruction placement by modifying the first power-gating instruction placement, wherein the second power-gating instruction placement comprises compound power-off instructions and compound power-on instructions generated by combining the power-off instructions and the power-on instructions respectively, and a power-gating instruction insertion module, inserting the power-gating instructions into the program according to the second power-gating instruction placement to generate the power-gated program.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows architecture of a processor;

FIG. 2 shows a method of generating assembly code for power leakage reduction;

FIG. 3 shows step 204 in detail;

FIG. 4 shows step 305 in detail;

FIG. 5 is a flowchart of a sinkable analysis module;

FIG. 6 is a flowchart of a hoistable analysis module;

FIG. 7 is a flowchart of a power-off instruction classification module;

FIG. 8 is a flowchart of a power-on instruction classification module;

FIG. 9A is a control-flow graph of a program, utilization of power-gated components, and a first power-gating instruction placement; and

FIG. 9B shows a second power-gating instruction placement generated from FIG.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 shows architecture of a processor comprising a program counter 101, a instruction decoder 102, integer registers 103, floating point registers 104, power-gating control registers 105, an integer ALU 106, an integer multiplier 107, a floating point adder 108, a floating point multiplier 109, and a floating point divider 110. The power-gated components of the processor, comprising the integer multiplier 107, the floating point adder 108, the floating point multiplier 109, and the floating point divider 110, are equipped individually with a power-gating control unit 111 controlled by the value stored in the power-gating control registers 105. According to power-off and power-on instructions in a power-gated program, the processor generates the value stored in the power-gating control registers 105.

FIG. 2 shows a method of generating assembly code for power leakage reduction, based on a compiler solution and comprising receiving high-level language, and converting the high-level language to high-level intermediate language (step 201), converting the high-level intermediate language to low-level intermediate language for a processor (step 202), generating a program by performing instruction scheduling and register allocation on the low-level intermediate language (step 203); converting the program to a power-gated program by analyzing utilization of the power-gated components in the processor in accordance with the program and inserting power-gating instructions into the appropriate position of the program to reduce power-gating instructions (step 204); converting the power-gated program to assembly code for the processor (step 205).

FIG. 3 shows step 204 in detail, comprising receiving the program from step 203 (step 301), generating a control-flow graph by dividing the program into blocks and linking the blocks, the control-flow graph comprising control commands (step 302), analyzing utilization of the power-gated components in the processor (step 303), generating the first power-gating instruction placement for leakage power reduction according to the utilization of the power-gated components, the first power-gating instruction comprising power-off and power-on instructions to shut down the inactive power-gated components (step 304), generating the second power-gating instruction placement by merging the power-off instructions and the power-on instructions of the first power-gating instruction placement into one compound power-off instruction and one compound power-on instruction, respectively (step 305), and inserting the power-gating instructions, including the power-off, power-on, compound power-off, and compound power-on instructions, into the program according to the second power-gating instruction placement (step 306).

Step 302 to 304 can be implemented by the processes disclosed in ROC. Pat. Pub. No. 00519599 or other technologies such as profiling mechanisms which can also be applied to generate the first power-gating instruction placement. Other suitable technologies generating the first power-gating instruction placement by software or hardware solution are also applicable.

FIG. 4 shows step 305 in detail comprising receiving the control-flow graph of the program, the utilization of the power-gated components in each block of the control-flow graph, and the first power-gating instruction placement generated by step 304 (step 401), determining whether the power-off instructions of the first power-gating instruction placement can be postponed to other blocks to determine executable blocks for each power-off instruction, and determining whether the power-on instructions of the first power-gating instruction placement can be advanced to other blocks to determine executable blocks for each power-on instruction: (step 402), dividing the blocks of the control-flow graph into groups to class the executable blocks of the combinable power-off instructions into one group, and to class the executable blocks of the combinable power-on instructions into one group (step 403), generating all combinations of the power-gating instructions in each group in accordance to the executable blocks of the power-off or power-on instructions occurring in each group and determining the best combination for power reduction to generate the second power-gating instruction placement.

In an exemplary embodiment of the invention, MAX-SINK-SLK_C represents the maximum number of blocks to which the power-off instruction of component C can be postponed. SINK-SLK_C represents the number of blocks to which the power-off instruction of component C can be postponed from the present block. SINK-SLK_C is calculated by the formulaE_off(C)+P_rleak(C)·SINK_—SLK_C>E_fet-dec-off(C)/N+E_exe-off(C)+P_leak(C)·SINK_—SLK_C,  (1).where E_fet-dec-off(C) represents energy consumption of fetching and decoding the power-off instruction of component C, E_exe-off(C) represents energy consumption of executing the power-off instruction of component C, N represents the amount of power-gated components in the processor, P_leak(C) represents leakage energy consumption of component C during a block cycle, P_rleak(C) represents reduced leakage energy consumption of component C during a block cycle when the component C is shut down, E_off(C) represents energy consumption of issuing the power-off instruction of component C, and the value of E_off(C) equals the sum of E_exe-off(C) and E_fet-dec-off(C). MAX-SINK-SLK_C is calculated according to formula (1), wherein

$\begin{array}{cc}\mathrm{MAX}-\mathrm{SINK}-{\mathrm{SLK}}_C=\frac{\left(N-1\right)·E_{\mathrm{fet}-\mathrm{dec}-\mathrm{off}}\left(C\right)}{N·\left(P_{\mathrm{leak}}\left(C\right)-P_{\mathrm{rleak}}\left(C\right)\right)}.& \left(2\right)\end{array}$

Similarly, MAX-HOIST-SLK_C represents the maximum number of blocks to which the power-on instruction of component C can be advanced. HOIST-SLK_C represents the number of blocks to which the power-on instruction of component C can be advanced from the present block. HOIST-SLK_C is calculated by the formulaE_on(C)+P_rleak(C)·HOIST_—SLK_C>E_fet-dec-on(C)/N+E_exe-on(C)+P_leak(C)·HOIST_—SLK_C,  (3)where E_fet-dec-on(C) represents energy consumption of fetching and decoding a power-on instruction of component C, E_exe-on(C) represents energy consumption of executing the power-off instruction of component C, N represents the number of power-gated components in the processor, E_on(C) represents energy consumption of issuing the power-on instruction of component C, and the value of E_on(C) equals the sum of E_exe-on(C) and E_fet-dec-on(C). MAX-HOIST-SLK_C is calculated according to formula (3), wherein

$\begin{array}{cc}\mathrm{MAX}-\mathrm{Hoist}-{\mathrm{SLK}}_C=\frac{\left(N-1\right)·E_{\mathrm{fet}-\mathrm{dec}-\mathrm{on}}\left(C\right)}{N·\left(P_{\mathrm{leak}}\left(C\right)-P_{\mathrm{rleak}}\left(C\right)\right)}.& \left(4\right)\end{array}$

SINKABLE_loc(b), SINKABLE_blk(b), SINKABLE_in(b), and SINKABLE_out(b) of each block b are determined to perform a data-flow analysis to determine the executable power-off instructions in each block. SINK-SLK_C^b represents the number of blocks to which the power-off instruction of component C can be postponed from block b. FIG. 5 is a flowchart of the sinkable analysis module. Based on the first power-gating instruction placement, SINKABLE_loc(b) represents a set of power-off instructions occurring in block b. In step 501, SINKABLE_loc(b) of each block b is determined and SINK-SLK_C^b of the power-off instructions occurring in each block b are initialized as the corresponding MAX-SINK-SLK_C.

In step 502 and step 503, SINKABLE_blk(b), SINKABLE_in(b), and SINKABLE_out(b) of each block b are determined from the beginning block to the end and repeatedly until SINKABLE_out(b) of each block b is stabilized. The method of determining SINKABLE_blk(b), SINKABLE_in(b), and SINKABLE_out(b) in one block b comprises determining SINKABLE_in(b) by the formula

${\mathrm{SINKABLE}}_{\mathrm{in}}\left(b\right)=\bigcap _{p\in \mathrm{Pred}\left(b\right)}{\mathrm{SINKABLE}}_{\mathrm{out}}\left(p\right),$ where Pred(b) represents the former blocks of the block b. SINK-SLK_C^b of component C, the power-off instruction of which exists in SINKABLE_in(b) and not in SINKABLE_loc(b), is determined by the formula SINK-SLK_C^b=MIN_{p∈Pr ed}(b)(SINK-SLK_C^p)−1. The components in SINKABLE_blk(b) are power-off instructions having zero SINK-SLK_C^b. Finally, SINKABLE_out(b) is determined by the formulaSINKABLE_out(b)=SINKABLE_loc(b)∪(SINKABLE_in(b)−SINKABLE_blk(b)).

If the components in SINKABLE_out(b) of each block b are invariable (step 503), SINKABLE_out(b) of every block b is regarded as stable and the power-off instructions in SINKABLE_out(b) are the executable power-off instructions of each block b.

Similarly, HOISTABLE_loc(b), HOISTABLE_in(b), HOISTABLE_blk(b), and HOISTABLE_out(b) of each block b are determined to perform a data-flow analysis to determine the executable power-on instructions in each block. HOIST-SLK_C^b represents the number of blocks to which the power-on instruction of component C can be advanced from block b. FIG. 6 is a flowchart of the hoistable analysis module. Based on the first power-gating instruction placement, HOISTABLE_loc(b) represents a set of power-on instructions occurring in block b. In step 601, HOISTABLE_loc(b) of each block b is determined and HOIST-SLK_C^b of the power-on instructions occurring in each block b are initialized as the corresponding MAX-HOIST-SLK_C.

In step 602 and step 603, HOISTABLE_in(b), HOISTABLE_blk(b), and HOISTABLE_out(b) of each block b are determined from the beginning block to the end and repeatedly until HOISTABLE_in(b) of each block b is stable. Determining HOISTABLE_in(b), HOISTABLE_blk(b), and HOISTABLE_out(b) in one block b comprising determining HOISTABLE_out(b) by the formula

${\mathrm{HOISTABLE}}_{\mathrm{out}}\left(b\right)=\bigcap _{s\in \mathrm{Succ}\left(b\right)}{\mathrm{HOISTABLE}}_{\mathrm{in}}\left(s\right),$ where Succ(b) represents the subsequent blocks of the block b. HOIST-SLK_C^b of component C, the power-on instruction of which exists in HOISTABLE_out(b) and not in HOISTABLE_loc(b), is determined by the formula HOIST-SLK_C^b=MIN_s∈Succ(b)(HOIST-SLK_C^s)−1. The components in HOISTABLE_blk(b) are the power-on instructions having zero HOIST-SLK_C^b. HOISTABLE_in(b) is determined by the formulaHOISTABLE_in(b)=HOISTABLE_loc(b)∪(HOISTABLE_out(b)−HOISTABLE_blk(b)).

If the components in HOISTABLE_in(b) of each block b are invariable (step 603), HOISTABLE_in(b) of every block b is regarded as stable and the power-on instructions in HOISTABLE_in(b) are the executable power-on instructions of each block b.

GROUP-OFF_loc(b), GROUP-OFF_in(b), GROUP-OFF_blk(b), and GROUP-OFF_out(b) of each block b are determined to perform a data-flow analysis to class the executable blocks of the combinable power-off instructions into one group. FIG. 7 is a flowchart of the power-off instruction classification module.

In step 701, if

${\mathrm{SINKABLE}}_{\mathrm{out}}\left(b\right)\ne \varphi \mathrm{and}\bigcup _{p\in \mathrm{Pred}\left(b\right)}{\mathrm{SINKABLE}}_{\mathrm{out}}\left(p\right)=\varphi ,$ GROUP-OFF_loc(b) of block b is assigned an integer number not occurring before to generate a new group. The integer number is generated by a counter. Once a new group is determined, the output of the counter is increased by one.

In step 702 and step 703, GROUP-OFF_in(b), GROUP-OFF_blk(b), and GROUP-OFF_out(b) of each block b are determined from the beginning block to the end and repeatedly until GROUP-OFF_out(b) of every block b is stable. Determining GROUP-OFF_in(b), GROUP-OFF_blk(b), and GROUP-OFF_out(b) in one block b comprising determining GROUP-OFF_in(b) by the formula

$\mathrm{GROUP}\text{-}{\mathrm{OFF}}_{\mathrm{in}}\left(b\right)=\{\begin{array}{cc}\varphi ,& \begin{array}{c}\mathrm{if}{\mathrm{MIN}}_{p\in \mathrm{Pred}\left(b\right)}\\ \left(\Phi \left(\mathrm{GROUP}\text{-}{\mathrm{OFF}}_{\mathrm{out}}\left(p\right)\right)\right)=\infty \end{array}\\ \begin{array}{c}{\mathrm{MIN}}_{p\in \mathrm{Pred}\left(b\right)}\\ \left(\Phi \left(\mathrm{GROUP}\text{-}{\mathrm{OFF}}_{\mathrm{out}}\left(p\right)\right)\right),\end{array}& \mathrm{otherwise}\end{array},$ where Φ returns infinity if its parameter, GROUP-OFF_out(p), is an empty set, otherwise, Φ returns the value of GROUP-OFF_out(p). GROUP-OFF_blk(b), either a universal set named Ω or an empty set, is determined, wherein GROUP-OFF_blk(b) is a universal set Ω only when

${\mathrm{SINKABLE}}_{\mathrm{out}}\left(b\right)=Ø\mathrm{and}\bigcup _{p\in \mathrm{Pred}\left(b\right)}{\mathrm{SINKABLE}}_{\mathrm{out}}\left(p\right)\ne \varphi .$ GROUP-OFF_out(b) is determined by the formulaGROUP-OFF_out(b)=GROUP-OFF_loc(b)∪(GROUP-OFF_in(b)−GROUP-OFF_blk(b)).

If the components in GROUP-OFF_out(b) of each block b are invariable (step 703), GROUP-OFF_out(b) of every block b is regarded as stable, with the component in GROUP-OFF_out(b) representing the group number to which block b belongs.

GROUP-ON_loc(b), GROUP-ON_in(b), GROUP-ON_blk(b), and GROUP-ON_out(b) of each block b are determined to perform a data-flow analysis to class the executable blocks of the combinable power-on instructions into one group. FIG. 8 is a flowchart of the power-on instruction classification module.

In step 801, if

${\mathrm{HOISTABLE}}_{\mathrm{in}}\left(b\right)\ne Ø\mathrm{and}\bigcup _{p\in \mathrm{Pred}\left(b\right)}{\mathrm{HOISTABLE}}_{\mathrm{in}}\left(p\right)=Ø,$ GROUP-ON_loc(b) of block b is assigned an integer number not occurring before to generate a new group. The integer number is generated by a counter. Once a new group is determined, the output of the counter is increased by one.

In step 802 and step 803, GROUP-ON_in(b), GROUP-ON_blk(b), and GROUP-ON_out(b) of each block b are determined from the beginning block to the end and repeatedly until GROUP-ON_out(b) of every block b is stable. Determining GROUP-ON_in(b), GROUP-ON_blk(b), and GROUP-ON_out(b) in one block b comprising determining GROUP-ON_in(b) by the formula

$\mathrm{GROUP}\text{-}{\mathrm{ON}}_{\mathrm{in}}\left(b\right)\{\begin{array}{cc}\varphi ,& \begin{array}{c}\mathrm{if}{\mathrm{MIN}}_{p\in \mathrm{Pred}\left(b\right)}\\ \left(\Phi \left(\mathrm{GROUP}\text{-}{\mathrm{ON}}_{\mathrm{out}}\left(p\right)\right)\right)=\infty \end{array}\\ \begin{array}{c}{\mathrm{MIN}}_{p\in \mathrm{Pred}\left(b\right)}\\ \left(\Phi \left(\mathrm{GROUP}\text{-}{\mathrm{ON}}_{\mathrm{out}}\left(p\right)\right)\right),\end{array}& \mathrm{otherwise}\end{array}.$ GROUP-ON_blk(b), either a universal set named Ω or an empty set, is determined. GROUP-ON_blk(b) is a universal set, Ω only when

${\mathrm{HOISTABLE}}_{\mathrm{in}}\left(B\right)=Ø\mathrm{and}\bigcup _{p\in \mathrm{Pred}\left(b\right)}{\mathrm{HOISTABLE}}_{\mathrm{in}}\left(p\right)\ne \varphi .$ GROUP-ON_out(b) is determined by the formulaGROUP-ON_out(b)=GROUP-ON_loc(b)∪(GROUP-ON_in(b)−GROUP-ON_blk(b)).

If the components in GROUP-ON_out(b) of each block b are invariable (step 803), GROUP-ON_out(b) of every ‘block b is ’ regarded as stable, with the component in GROUP-ON_out(b) representing the group number to which block b belongs.

In an exemplary embodiment of the invention, there are two power-gated components in a processor. FIG. 9A shows a control-flow graph of a program, utilization of the power-gated components, and a first power-gating instruction placement. The left side of each block represents utilization of component A, and the right side of each component represents utilization of component B. The dotted region indicates that the component is active in the block. As shown in FIG. 9A, the power-off instruction of component A is arranged in blocks B_m+2 and B_n+2 and the power-off instruction of component B is arranged in blocks B_m+5 and B_n+5 according to the first power-gating instruction placement. Based on the invention, MAX-SINK-SLK_A is 4 and MAX-SINK-SLK_B is 2. The component in SINKABLE_loc(B_m+2) is A⁴, which indicates that there is a power-off instruction of component A occurs in block B_m+2 according to the first power-gating instruction placement. The superscript of A⁴ indicates SINK-SLK_A^Bm+5 which is initialized as MAX-SINK-SLK_A. After carrying out the steps of sinkable analysis module described in FIG. 5, SINKABLE_loc(b), SINKABLE_blk(b), SINKABLE_in(b), and SINKABLE_out(b) of each block b are shown in Table 1. An empty set is indicated as a blank. And the components of SINKABLE_out(b) represents the executable power-off instructions in block b.

TABLE 1
block		SINK-		SINK-
b	SINKABLEloc(b)	ABLEblk(b)	SINKABLEin(b)	ABLEout(b)
Bm+1
Bm+2	{A4}			{A4}
Bm+3			{A3}	{A3}
Bm+4			{A2}	{A2}
Bm+5	{B2}		{A1}	{A1, B2}
Bm+6		{A}	{A0, B1}	{B1}
Bm+7		{B}	{B0}
. . .
Bn+1
Bn+2	{A4}			{A4}
Bn+3			{A3}	{A3}
Bn+4			{A3}	{A3}
Bn+5	{B2}		{A2}	{A2, B2}
Bn+6			{A1, B1}	{A1, B1}
Bn+7		{A, B}	{A0, B0}

Power-off instruction classification module described in FIG. 7 is carried out. The resultant GROUP-ON_loc(b), GROUP-ON_in(b), GROUP-ON_blk(b), and GROUP-ON_out(b) of each block b are shown in Table 2. The components in GROUP-ON_out(b) is the group number of block b.

TABLE 2
	GROUP -	GROUP -	GROUP -	GROUP -
block b	OFFloc(b)	OFFblk(b)	OFFin(b)	OFFout(b)
Bm+1
Bm+2	{1}			{1}
Bm+3			{1}	{1}
Bm+4			{1}	{1}
Bm+5			{1}	{1}
Bm+6			{1}	{1}
Bm+7		Ω	{1}
. . .
Bn+1
Bn+2	{2}			{2}
Bn+3			{2}	{2}
Bn+4			{2}	{2}
Bn+5			{2}	{2}
Bn+6			{2}	{2}
Bn+7		Ω	{2}

The blocks are divided into two groups (group 1 and group 2). On the basis of the executable power-off instructions of each block, all combinations of power-off instructions in each group are generated. To determine the best combination of each groups for power reduction, the second power-gating instruction placement is generated, shown in FIG. 9B. In group 1, the best combination of power-off instructions is a compound power-off instruction of components A and B, which is placed in block B_m+5. In group 2, the best combination of power-off instructions is a compound power-off instruction of components A and B, which is placed in block B_n+6.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A method of power-gating instruction scheduling for power leakage reduction, comprising: receiving a program;generating a control-flow graph by dividing the program into a plurality of blocks and linking the blocks according to the program, wherein the control-flow graph contains control commands;analyzing utilization of power-gated components of a processor executing the program;generating first power-gating instruction placement based on the control-flow graph and the utilization of the power-gated components, the first power-gating instruction placement comprising a plurality of power-off instructions and a plurality of power-on instructions to shut down inactive components;generating second power-gating instruction placement by modifying the first power-gating instruction placement, wherein the second power-gating instruction placement comprises compound power-off instructions and compound power-on instructions generated by combining the combinable power-off instructions and combining the combinable power-on instructions respectively;inserting power-gating instructions into the program according to the second power-gating instruction placement; andexecuting the program by the processor.

2. The method as claimed in claim 1, generation of the second power-gating instruction placement further comprising: determining whether the power-off instructions of the first power-gating instruction placement can be postponed to other blocks, and determining executable blocks of each power-off instruction;determining whether the power-on instructions of the first power-gating instruction placement can be advanced to other blocks, and determining executable blocks of each power-on instruction;dividing the executable blocks of the combinable power-off instructions as one group and the executable blocks of the combinable power-on instructions as one group;evaluating all combinations of the power-off instructions in each group according to the executable blocks of the power-off instructions in each group;evaluating all combinations of the power-on instructions in each group according the executable blocks of the power-on instructions in each group; anddetermining the best combination in each group for power reduction, wherein the second power-gating instruction placement is generated based on the best combination in each group.

3. The method as claimed in claim 2, determination of executable blocks of each power-off instruction in the first power-gating instruction placement further comprising determining executable power-off instructions for each block by data-flow analysis; and determination of executable blocks of each power-on instruction in the first power-gating instruction placement further comprising determining executable power-on instructions for each block by data-flow analysis.

4. The method as claimed in claim 3, division of the blocks in the control-flow graph into groups further comprising: classing the executable blocks of the combinable power-off instructions of the first power-gating instruction placement as one group by data-flow analysis based on the executable power-off instructions of every block; andclassing the executable blocks of the combinable power-on instructions of the first power-gating instruction placement as one group by data-flow analysis based on the executable power-on instructions of every block.

5. The method as claimed in claim 3, determination of the executable power-off instructions of each block further comprising: evaluating MAX_SINK_SLKC for each component C to represent the maximum amount of blocks to which the power-off instruction of component C can be postponed;determining SINKABLEloc(b) for each block b according to the first power-gating instruction placement, wherein SINKABLEloc(b) is a set of power-off instructions occurring within block b, and each power-off instruction in SINKABLEloc(b) is associated with an integer number SINK_SLKCb which indicates how many blocks to which the power-off instruction of component C can be postponed, wherein SINK_SLKCb is initialized as MAX_SINK_SLKC;determining SINKABLEin(b), SINKABLEblk(b), and SINKABLEout(b) of every block b from the beginning block to the end and repeatedly until SINKABLEout(b) of every block b is stable, wherein the power-off instructions in the stable SINKABLEout(b) represent the executable power-off instructions in block b,wherein SINKABLEin(b), SINKABLEblk(b), and SINKABLEout(b) of one block b are calculated by: determining SINKABLEin(b) by the formula

6. The method as claimed in claim 3, determination of the executable power-on instructions of each block further comprising: evaluating MAX_HOIST_SLKC for each component C to represent the maximum amount of blocks to which the power-on instruction of component C can be advanced;determining HOISTABLEloc(b) for each block b according to the first power-gating instruction placement, wherein HOISTABLEloc(b) is a set of power-on instructions occurring within block b, with each power-on instruction in HOISTABLEloc(b) associated with an integer number HOIST_SLKCb which indicates how many blocks to which the power-on instruction of component C can be advanced, wherein HOIST_SLKCb is initialized as MAX_HOIST_SLKC;determining HOISTABLEout(b); HOISTABLEblk(b), and HOISTABLEin(b) of every block b from the beginning block to the end and repeatedly until HOISTABLEin(b) of every block b is stable, wherein the power-on instructions in the stable HOISTABLEin(b) represent the executable power-on instructions in block b,wherein HOISTABLEout(b), HOISTABLEblk(b), and HOISTABLEin(b) of one block b are calculated by: determining HOISTABLEout(b) by the formula

7. The method as claimed in claim 4, classification of the executable blocks of the combinable power-off instructions of the first power-gating instruction placement as one group further comprising: determining GROUP-OFFloc(b) for each block b, wherein, if

8. The method as claimed in claim 4, classification of the executable blocks of the combinable power-on instructions of the first power-gating instruction placement as one group further comprising: determining GROUP-ONloc(b) for each block b, wherein, if

9. A system of power-gating instruction scheduling for power leakage reduction, receiving a program, generating a power-gated program comprising power-gating instructions, and executing the power-gated program by a processor, the system comprising: a control-flow graph construction module, generating a control-flow graph by dividing the program into a plurality of blocks and linking the blocks according to the program, wherein the control-flow graph contains control commands;a utilization analysis module, analyzing utilization of power-gated components of the processor executing the program;a first power-gating instruction placement generator, generating first power-gating instruction placement based on the control-flow graph and the utilization of the power-gated components, the first power-gating instruction placement comprising a plurality of power-off instructions and a plurality of power-on instructions to shut down inactive power-gated components;a second power-gating instruction placement generator, generating second power-gating instruction placement by modifying the first power-gating instruction placement, wherein the second power-gating instruction placement comprises compound power-off instructions and compound power-on instructions generated by combining the combinable power-off instructions and combining the combinable power-on instructions respectively; anda power-gating instruction insertion module, inserting the power-gating instructions into the program according to the second power-gating instruction placement to generate the power-gated program.

10. The system as claimed in claim 9, wherein the second power-gating instruction placement further comprises: a power-gating instruction analysis module, determining whether the power-off instructions of the first power-gating instruction placement can be postponed to other blocks to determine executable blocks of each power-off instruction; and determining whether the power-on instructions of the first power-gating instruction placement can be advanced to other blocks to determine executable blocks of each power-on instruction;a classification module, dividing the blocks in the control-flow graph into groups to class the executable blocks of the combinable power-off instructions as one group and to class the executable blocks of the combinable power-on instructions as one group; anda power evaluation module, evaluating all combinations of the power-off instructions in each group according to the executable blocks of the power-off instructions in each group; and evaluating all combinations of the power-on instructions in each group according to the executable blocks of the power-on instructions in each group, the power evaluation module further determining the best combination in each group for power reduction, wherein the second power-gating instruction placement is generated based on the best combination in each group.

11. The system as claimed in claim 10, the power-gating instruction analysis module further comprising a sinkable analysis module and a hoistable analysis module, the sinkable analysis module determining a set of executable power-off instructions for each block by data-flow analysis, the hoistable analysis module determining a set of executable power-on instructions for each block by data-flow analysis.

12. The system as claimed in claim 11, wherein the classification module further comprises: a power-off instruction classification module, classing the executable blocks of the combinable power-off instructions of the first power-gating instruction placement into one group by data-flow analysis based on the executable power-off instructions of every block; anda power-on instruction classification module, classing the executable blocks of the combinable power-on instructions of the first power-gating instruction placement into one group by data-flow analysis based on the executable power-on instructions of every block.