Patent Application
20080195986
1. Field of the Invention
The present invention relates to integrated circuits (ICs). More particularly, the inventions disclosed and claimed herein relate to ICs and methods for tuning ICs to realize more uniform voltages across the IC.
2. Description of the Related Art
Power supply voltages are typically supplied to an integrated circuit (IC) from an external power supply source through interconnect or bond pads on the IC. The power supply voltages are routed from these pads to the transistors comprising the IC through metal conductors, referred to herein as “power distribution wiring,” that are formed on one or more layers for both horizontal and vertical power distribution. On the IC, the power distribution wiring is of varying lengths and widths, traversing the IC in a variety of patterns, including regular grids, irregular grids, serpentines and perforated wires. Power distribution wiring in the first level IC package consists of wires of a variety of widths, wires with a variety of diameters, and conductors patterned in plane shapes. As such, the path through the power distribution wiring supplying voltages and currents to any portion of the IC (e.g., transistors and functional circuit blocks) may differ physically in aggregate length, cross-sectional area and material composition from the power distribution wiring supplying voltages and currents to transistors and functional circuit blocks (e.g., macros) within other portions of the IC. Because power distribution wiring path resistances are determined by their respective lengths, cross-sectional areas, and material composition, the power distribution wiring paths to different portions of the IC have different resistance. Further, each section of the IC will require an amount of current that differs from the current requirements of other section. Thus the IR drop (Vdd-Vss) at the various positions of the IC may be decidedly non-uniform. That is, the magnitude of the voltage drop depends on the current demand, the lengths, cross-sections and the resistances of the conductive power distribution wiring.
For that matter, the speed of transistors and functional circuit block operation is partly dependent upon the magnitude of the power supply voltages they receive, whereby devices in locations of the IC that suffer large IR drops in their power distribution wiring maybe forced to operate at reduced speeds because of the reduced power supply voltage levels available to them. Other IC devices in locations that suffer less IR drop within their power distribution wiring will operate at relatively higher speeds. Of course this may result in timing problems such as increased clock skew or increased uncertainty propagation delay times through gates and flip-flops. In large ICs (e.g., VLSI), the non-uniformity in supply voltage is even more pronounced.
It would be welcomed in the art of IC chip design and IC chip package design to have available a technique or method for routing power supply voltages throughout an IC chip and IC package to reduce variations in power supply voltages received or provided to different voltage supply regions within the IC chip.
To that end, the inventions described and set forth herein implement a method for tuning a grid of supply voltages provided to the semiconductor chip itself, and through the chip package in order to create uniform voltage levels across each voltage supply level within the IC chip. The inventive methods include identifying localized circuit current draws, and modifying the electrical/mechanical parameters of the IC package power supply conductors, the IC chip power supply conductors, or both. When implemented as set forth in detail herein, the inventive methods result in providing more spatially uniform voltage levels throughout the various voltage supply regions, e.g., within the IC chip, within and between localized functional blocks. Because the methods are preferably implemented in computer software, the invention includes a computer readable medium that includes a set of computer instructions which may be downloaded and executed by a general purpose computer in order to support IC chip and IC package design and fabrication.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of embodiments of the inventions, with reference to the drawings, in which:
The inventive methods, software and apparatus set forth herein are disclosed and described in order to convey the broad inventive concepts. The drawings and descriptions are not meant to in any way limit the scope and spirit of the inventions, as claimed.
IC chips may have varied voltage needs, which may be supplied to various places within the chip's design through the IC package, as discussed above. For example, there may be a need for numerous voltage supplies required for IC chip operation such as 5 V, 0 V, −5V, 3.3 V, −3.3V, 2.0 V, −2.0 V, 2.5 V, −2.5 V, 1.2 V, −1.2 V, etc. Referring first to the logical block diagram of
The chip current map may be used in the presently described process for the IC package depicted in
Block 150 represents a step where the IC package design layout is analyzed using a package IR or voltage drop tool (i.e., I×R=V, or voltage drop). An example of a tool or application, which will analyze a package layout and design for IR drops, is HAL™, known to the skilled artisan. Block 160 represents a step in which an internal plane voltage map and plane current map are generated for each plane of the IC package. Known IC package designs may have multiple planes, for example, 10. Block 170 represents a step within which required vias, and various IC package plane current changes are generated in accordance with the voltage and current maps. That is, the resistances of the metal power distribution wiring are modified by varying their widths or lengths, adding extra power distribution wiring, removing or re-routing power distribution wiring, etc., to modify the IR drops to a voltage region. More, block 170 may include utilizing an IC chip voltage map. The IC chip voltage map may be generated in the IC chip IR balancing method, described in detail below with reference to
Decision step 180 represents where the method determines whether the various “R drops are equalized (balanced) across the package, and making any modifications to the conductive power distribution wiring in order to improve the balancing of the various 1R drops, where necessary. The modifications are implemented by changing conductive trace lengths, widths and routing, where necessary. The balancing is an iterative process, which if the IR drops throughout the IC package are not yet effectively balanced, to balance the voltages conveyed thereby (i.e., NO), the process winds back to the step represented by block 140 of the figure and repeats. When the most efficient tuning or balancing is realized, or determined, the IC package IR balancing is complete and the method is stopped (END).
Block 240 represents a step in which a metal power distribution wiring or conductive interconnect analysis is performed to identify voltages or IR drops within any of the supply voltage supply paths that need to be modified, or equalized, including shapes representative of supplied functional circuit blocks. The designation “A” represents that the IC chip current map generated in the
Block 325 represents as step where the positions and voltage rails of each chip-package interconnect site is assigned, as determined by the requirements of the IC chip current map. This includes assigning interconnect bumps and/or assigning peripheral array of conductive bond pads. The assigning should correlate to the IC chip voltage map requirements, which is particularly important when the IC module pin layout is a legacy footprint. Block 330 represents a step wherein an IC chip power grid is defined. This includes determining a set of power distribution wiring requirements for each of the supply voltages, and each of the functional blocks that each supply voltage supports in the IC chip, in accordance with the model.
Block 340 represents a step of analyzing the IC chip's metal power distribution wiring layout and functional derived shapes layout in order to incorporate their electrical resistances into a model and, with the chip current models, generating a map of IC chip voltages and IC chip-package interconnect voltages and currents.
Block 350 represents a step wherein the IC package layout is defined, including using the IC chip and interconnect voltage maps. The step includes assigning module pins and defining and the metal routing through the IC package. Block 360 represents a step of extracting and modeling the entire IC package design and IC chip design using an IR analysis tool (any known analysis TR tool). Included in this step, an internal plane voltage map and an internal plane current map are generated for each IC package supply plane, as well as a voltage map or the IC chip.
A decision step is performed, represented by diamond 370, to determine whether various IC chip voltages have been equalized or tuned. If not, the method proceeds to block 380, and the method continues iteratively until the IC chip voltages are effectively balanced (END).
Block 380 represents an analysis of the IC chip voltage map and the IC package plane voltage maps whereby the voltages to be equalized are identified. Further, package and IC chip power distribution wires that must be modified are identified to the end of balancing the voltages at the IC chip.
Block 390 represents a step wherein required via changes, and required plane current or voltage changes are implemented by modifying the IC chip and IC package conductive power distribution wiring lengths and/or thicknesses, and/or trace paths, in each supply plane based on the IC package plane voltage and plane current maps, as well as the IC chip voltage map. Following block 390, the method returns to block 360, and the method continues iteratively until the IR drops throughout the IC package are effectively balanced
Although a few examples of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes might be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
