Patent Application
20170222659
1. Field of the Invention
This invention relates to low-density parity check decoding, and more particularly, to a low-density parity check decoder and decoding method which can save power.
2. Description of the Prior Art
Low-density parity check (LDPC) decoders use a linear error correcting code with parity bits. Parity bits provide a decoder with parity equations which can validate a received codeword. For example, a low-density parity check is a fixed length binary code wherein all the symbols added together will equal zero.
During encoding, all data bits are repeated and transmitted to encoders, wherein each encoder generates a parity symbol. Codewords are formed of k information digits and r check digits. If the length of the codeword is n then the information digits, k, will equal n−r. The codewords can be represented by a parity check matrix, which consists of r rows (representing equations) and n columns (representing digits), and is represented in
LDPC engines support three modes: hard decision hard decoding, soft decision hard decoding, and soft decision soft decoding.
The check nodes, which are represented by the square boxes, are the number of parity bits; and the variable nodes, which are represented by the circular boxes, are the number of bits in a codeword. If a code symbol is involved in a particular equation, a line is drawn between the corresponding check node and variable node. ‘Messages’, which are estimates, are passed along the connecting lines, and combined in different ways at the nodes. Initially, the variable nodes will send an estimate to the check nodes on all connecting lines containing a bit believed to be correct. Each check node then takes all the other connected estimates, makes new estimates for each variable node based on this information, and passes the new estimate back to the variable nodes. The new estimate is based on the fact that the parity check equations force all variable nodes connected to a particular check node to sum to zero.
The variable nodes receive the new information and use a majority rule (a hard decision) to determine if the value of the original bit they sent was correct. If not, the original bit will be ‘flipped’. The bit is then sent back to the check nodes, and these steps are repeated for a predetermined number of iterations or until the parity check equations at the check nodes are satisfied. If these equations are satisfied (i.e. the value calculated by the check nodes matches the value received from the variable nodes) then Early Termination can be activated, which allows the system to exit the decoding process before the maximum number of iterations is reached.
The parity check constraints are performed by doing a syndrome check. A valid codeword will satisfy the equation H. CT=S=0, wherein H is the parity matrix, C is the hard decision codeword and S is the syndrome. When the syndrome equals zero, this means that no further information is required and the decoding process is complete.
Typically, a hard decision and a syndrome check are performed during each iteration, wherein a non-zero syndrome means there is odd parity and a new decoding iteration is required.
As detailed above, syndrome check is usually performed for each iteration in order to activate Early Termination. As it is unlikely that a codeword will pass parity check in the initial iterations, however, performing the syndrome check for each iteration wastes power. If the frequency of the syndrome checks can be reduced, power can be saved.
It is therefore an objective of the present invention to provide a system and method for estimating a best time to perform syndrome check, and utilizing this system and method to reduce the frequency of syndrome check operations in an LDPC engine.
A method for decoding low-density parity check data to decode a codeword is disclosed. The method comprises: receiving initial estimates representing a codeword from variable nodes; sending the initial estimates to corresponding check nodes; using all initial estimates to calculate a posteriori probability (APP) values and extrinsic information and sending the APP values and the extrinsic information to the variable nodes; monitoring the extrinsic information (branch information?) received at the check nodes; when the extrinsic information begins to converge, activating a syndrome check for the values at the variable nodes; and when the syndrome check equals zero, activating early termination for the decoding process.
A related low-density parity check (LDPC) decoder for decoding a codeword comprises: a channel memory, for storing channel values; a subtractor, coupled to the channel memory, for subtracting metrics information from the channel values to generate a resultant value for updating the channel values and the metrics information; a processor, coupled to the subtractor, for generating modified metrics information; an adder, coupled to the processor and the channel memory, for combining the modified metrics information and the channel values to generate modified channel values; a low parity detection circuit, coupled to the adder, for detecting the modified channel values; an Early Termination (ET) circuit, coupled to the low parity detection circuit, for performing a syndrome check on the modified channel values and ending the decoding process when the modified channel values pass the syndrome check; and a permutator, coupled between the low parity detection circuit and the ET circuit, wherein when the low parity detection circuit determines that the modified channel values converge to a same sign, the permutator will send the modified channel values to the ET circuit, and when the LP detection circuit determines that the modified channel values do not converge to a same sign, the permutator will begin another iteration of the LDPC decoder without sending the modified channel values to the ET circuit.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
An objective of the present invention is to determine a best time for activating the syndrome check in order to save power. The aim is to only perform the syndrome check at a time when the result is likely to equal zero, rather than performing the syndrome check each iteration as in the prior art.
Two equations are used to illustrate the method of the present invention. As detailed in the ‘Background’ section, when the syndrome is equal to zero, this means the parity check is satisfied and the decoding can be exited. The syndrome is determined by multiplying the variable node values with the parity check matrix, as detailed in equation 1.
H.CT=S (1)
When S=zero, this indicates that the decoder can be terminated and the hard decision output. Otherwise, the decoding will continue for a next iteration.
The present invention also uses a sum-product decoding algorithm, rather than the bit flipping algorithm, as a means to determine when syndrome check can be activated. In the sum-product algorithm, the messages representing each decision are probabilistic values. In the bit flipping algorithm, although hard decisions are made, what is actually received is real values wherein the sign (0 or 1) represents a positive or negative decision, respectively, and the magnitude of the value represents a level of confidence in the decision. This is known as soft information. Sum-product algorithms can use this soft information by computing an a posteriori probability value APPj for each bit, which is the probability that a certain bit will equal 1 if all the parity checks are met. An approximation of the APPj is computed over a series of iterations.
The iterations follows those of the bit flipping algorithm, except that each time what is calculated is the probability that a parity check equation will be satisfied if the bit is a particular value. Each time the check node returns a probability value, it will also return extrinsic information which is independent of the probability value for that bit which is then used by the variable node as a priori information for the next iteration.
The relation between the variable node values, the check node values, and the a posteriori probability values for sum-product decoding are represented by equation 2.
APPj−Rij=Qij (2)
where APPj is the a posteriori probability sent by the check node, Qij is the response from the variable node and Rij is the extrinsic information from the check node. Subscript j represents a parity check equation and subscript i represents a bit of the code.
In the sum-product algorithm, when a codeword is found, APPj will gradually converge. From equation (2), it can be seen that as APPj gradually converges into a codeword, Rij will also converge but will be smaller than APPj. Further, the sign of Qij will be approximately equal to the sign of APPj as it converges. Therefore, by implementing a detection circuit which determines when the check node values converge to a same sign, the LDPC system can determine at what time the syndrome check should be activated.
When the syndrome check is then activated, the Qij value is put into equation (1) to determine if the parity check constraints are satisfied. Once the codeword meets the parity check, Early Termination can be activated and the decoding process can end without having to go through a maximum number of iterations.
By turning off the syndrome check until it is determined that extrinsic (soft) information sent from the check node converges to a same sign, power wasted on performing syndrome check for each iteration, even when the codeword is unlikely to meet parity constraints, can be saved. A simple detection circuit can detect the sign of the extrinsic information, which does not require complicated circuitry to be added to the LDPC engine.
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The present invention therefore can save power when using a sum-product algorithm for hard decision soft decoding of low-density parity check codes.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
