Power loss memory back-up

Abstract

A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Description

TECHNICAL FIELD

[0001] This invention relates to memory management, and more particularly to enhancing data retention of a memory controller during a system reset.

BACKGROUND

[0002] Many computing systems include a power-fail system for detecting a power failure and transitioning the computing system from system power to battery power. Typically, the power-fail system places the memory system in an auto refresh mode to retain stored data.

[0003] Two factors that effect effective data retention is the speed at which the system enters the retention state and the ability to remain in that state. Most events that place the memory into the self-refresh state are asynchronous and unpredictable. Examples of these events include depressing the reset button the failure of a power supply. Neither of these situations has a predictable duration, and therefore the memory sub-system must be placed in the self-refresh state.

DESCRIPTION OF DRAWINGS

[0004] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.

[0005] FIG. 1 is a block diagram illustrating an example of a memory system configured according to the invention.

[0006] FIG. 2 is a circuit diagram illustrating an example of the power delay circuit of the memory system of FIG. 1.

[0007] FIG. 3 is a circuit diagram illustrating an example of the power fail controller of the memory system of FIG. 1.

DETAILED DESCRIPTION

[0008] FIG. 1 is a block diagram illustrating an example memory system 2 arranged according to the invention. A memory controller 4 provides one or more control signals for configuring and controlling a memory sub-system 6. The memory sub-system 6 stores digital data and may be any random access memory device such as dynamic random access memory (DRAM), static random access memory (SRAM) or the like.

[0009] As described in detail below, a power delay circuit 26 and a power fail controller 10 cooperate to quickly place the memory system 2 in a retention state in the event a power failure event is detected. The memory controller 4 typically includes an internal state machine 16 for controlling the operations of the memory controller 4 and the communication between the memory controller 4 and the memory sub-system 6. For example, in response to a power fail signal, the state machine 16 may direct the memory controller 4 through a sequence to place the memory sub-system 6 in a self-refresh state.

[0010] In operation, a voltage monitor 20 monitors the voltage of the system to detect if a power failure has occurred by determining if the voltage falls below a predetermined threshold. If the voltage does fall below the predetermined threshold, the voltage monitor 20 transmits a signal 22 (PWRFAIL) to the power delay circuit 26. A second signal 24 (RESETIN) received by the power delay circuit 26 detects if a reset of the system is requested.

[0011] The power delay circuit 26 receives the signals 22, 24 and determines if the system is in a reset condition. The reset condition may be caused by a power failure (assertion of the PWRFAIL signal 22) or a reset request (assertion of the RESETIN signal 24). If either signal 22, 24 indicates a reset condition, the power delay circuit 26 transmits a reset signal 12 (RESET) to the power fail controller 10. The power delay circuit also transmits a power delay signal 14 (PWR_DELAYED) to the power fail controller 10.

[0012] The power fail controller 10 receives the reset signal 12 and the power delay signal 14 from the power delay circuit 26. The power fail controller 10 asserts the reset signal 26 to the entire chip. However, the power fail controller 10 also sends two signals 16, 18 to the state machine 16 to ensure the self-refresh routine is not issued when the chip is not configured. If the power delay circuit 26 did not detect the reset signal for a finite period of time, the self-refresh circuit will be held in reset to prevent invalid transitioning through the self-refresh sequence. However, if the reset signal is detected long enough and either a power failure or an external reset event is detected, the memory controller 4 self-refresh state machine 16 will execute. Once the self-refresh sequence has been performed, the memory controller would enter the reset state.

[0013] FIG. 2 is a circuit diagram illustrating an example of the power delay circuit 26 of the memory system 2 of FIG. 1. The power delay circuit 26 includes an AND gate 30, an inverter 32, resistors 38, 34, 36, a transistor 40, a diode 42, and a capacitor 44. The power delay circuit 26 receives the signals 22, 24 and determines if the system is in a reset condition. Each of the signals 22, 24 is provided as an input to the AND gate 30. In this embodiment, each of the signals 22, 24 are active low, and thus if either of the signals are active, the output of the AND gate 30 is driven low, thus activating the active low reset signal 12. Additionally, the reset signal 24 is provided as an input to the inverter 32. The inverter 32 is used to clean up the reset signal 32. The transistor 40, the resistors 34, 36, 38, and the diode 42 comprise a bleed off circuit. The bleed off circuit may act as an RC constant that ensures the power fail signal 22 and the reset signal 24 do not conflict. When the reset signal is high, indicating no reset condition is requested, the signal at the gate of the transistor 40 is low, turning on the active low transistor 40. This provides voltage to the bleed of circuit, and the power delay signal 14 is high. The capacitor 44 provides a stable signal at the power delay signal 14. When the reset signal 24 is active low, the input to the gate of the transistor 40 is high, turning the transistor 40 off. This causes the power delay signal to go low.

[0014] FIG. 3 is a circuit diagram illustrating an example of the power fail controller 10 of the memory system 2 of FIG. 1. The power delay signal 14 is input into a Schmidt trigger 50 to ensure the signal has a clean edge. The output of the Schmidt trigger 50 if provided as an input to a first OR gate 54 and to an inverter 52. The output of the inverter 52 is provided as an input to a second OR gate 56. The reset signal 12 is provided as the second input to the OR gates 54, 56. Therefore, if either the reset signal 12 or the power delay signal 14 is high, the output of the first OR gate 54 is high. This output 16 is a signal (RST_PF_FSM, reset power fail state machine) instructing the state machine 16 to remain in the idle state. If the reset signal 12 is high, or the power delay signal 14 is low, the output of the second OR gate 56 is high. This output 18 is a signal (START_PF, start power fail) instructing the state machine to begin the power fail routine.

[0015] Various embodiments of the invention have been described. For example, a single machine instruction has been described that conditionally moves data between a pointer register and a data register. The processor can be implemented in a variety of systems including general purpose computing systems, digital processing systems, laptop computers, personal digital assistants (PDA's) and cellular phones. These and other embodiments are within the scope of the following claims.

Claims

1. A method comprising: detecting a reset condition; verifying a memory controller is initialized; and placing a memory system into a retention state.

2. The method of claim 1, further comprising verifying the memory controller is initialized by delaying a reset signal.

3. The method of claim 1, further comprising monitoring the voltage level of a system to determine a power failure.

4. The method of claim 3, further comprising generating a reset condition when either a power failure or a reset request occurs.

5. The method of claim 4, further comprising verifying the reset request does not occur prior to initialization.

6. The method of claim 1, further comprising detecting the reset condition and verifying the memory controller is initialized external to the memory controller.

7. A memory system comprising: a power delay circuit external to a memory controller, wherein the power delay circuit instructs the memory system to run a retention routine during a power failure or reset condition.

8. The memory system of claim 7, further comprising a power fail controller which prevents the retention routine from executing when the memory system is not configured.

9. The memory system of claim 7, wherein the power delay circuit outputs a reset signal is either a power failure or a system reset signal is detected.

10. The memory system of claim 9, wherein the power delay circuit outputs a delay signal when the output reset signal is caused by a system reset signal.

11. The memory system of claim 7, wherein the power delay circuit monitors a voltage detector to detect a power failure.

12. The memory system of claim 8, wherein the power fail controller may be internal to the memory controller.

13. A method placing a memory system in a data retention mode comprising: detecting either a power failure or reset signal; generating a delay signal based on the reset signal; and initiating a data retention routine if the delay signal indicates the memory system is initialized.

14. The method of claim 13 further comprising monitoring the voltage level of a system to determine a power failure.

15. The method of claim 13, further comprising generating two output signals to the memory controller based on the delay signal.

16. The method of claim 13, further comprising preventing initiating the data retention routine if the reset signal is not de-asserted for a predetermined period of time.