Patent Application
20190227618
The present invention relates to power management for a data storage device and, more particularly, to power management that reaches good balance between low power consumption and high performance.
Referring to
SSD 12 receives data from host 10 and stores the data. Yet, SSD 12 is not always in need. There are idle situations in which communication of data of host 10 with SSD 12 is not needed. A typical power management method includes a hibernation routine and a wake-up routine. The hibernation routine is executed to put SSD 12 into hibernation to reduce power consumption in such idle situations. The wake-up routine is executed to wake up SSD 12 from the hibernation when host 10 has to communicate with SSD 12.
Referring to
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The present invention is therefore intended to obviate or at least alleviate the problems encountered in prior art.
It is the primary objective of the present invention to provide a data storage apparatus with a power management method that reaches balance between low power consumption and high performance.
To achieve the foregoing objective, the data storage apparatus includes a NAND flash memory, an external memory and two cores. The external memory is divided into a first portion and a second portion smaller than the first portion. Each of the cores includes a CPU, an ITCM and a DTCM. The data storage apparatus is switchable between an operative state and hibernation. In the hibernation, the NAND flash memory, the first portion of the external memory, the CPU of the first core, and the CPU, ITCM and DTCM of the second core are shut down while the second portion of the external memory and the ITCM and DTCM of the first core are kept awake.
Other objectives, advantages and features of the present invention will be apparent from the following description referring to the attached drawings.
The present invention will be described via detailed illustration of the preferred embodiment versus the prior art referring to the drawings wherein:
Host 10 and SSD 12 have been described above in RELATED PRIOR ART referring to
NAND flash memory 14 includes a hibernation physical block 22 that is in fact a plurality of physical blocks of NAND flash memory 14 for storing data about the hibernation of SSD 12. Each of cores 18 and 20 includes an F/W code that is stored in hibernation physical block 22. The term, “external memory 16”, is used because it represents a memory that is located out of NAND flash memory 14 and cores 18 and 20.
In the power management method according to the present invention, external memory 16 is divided into a first portion and a second portion. The first portion is larger than the second portion. Reasons for dividing external memory 16 into the first and second portions will be given later. External memory 16 is connected to NAND memory 14.
As described above, core 18 includes CPU 24, ITCM 26 and DTCM 28. CPU 24 runs a software program to execute the power management method according to the present invention. ITCM 26 stores software programs to be run in CPU 24. DTCM 28 stores data needed in the operation of core 18 and, more particularly, CPU 24. For example, ITCM 26 receives a flash translation layer (“FTL”) and a back end (“BE”) from NAND flash memory 14 and stores the FTL and the BE. Then, CPU 24 receives the FTL and the BE from ITCM 26 and executes the FTL and the BE. The data stored in DTCM 28 include data required for or produced by CPU 24 in operation and the context of CPU 24. Core 18 is connected to NAND flash memory 14.
As described above, core 20 includes CPU 30, ITCM 32 and DTCM 34. CPU 30 runs a software program to execute the power management method according to the present invention. ITCM 32 stores software programs to be run in CPU 30. DTCM 34 stores data needed in the operation of core 20 and, more particularly, CPU 30. For example, ITCM 32 receives a front end (“FE”) and a data cache (“DC”) from NAND flash memory 14 and stores the FE and the DC. Then, CPU 30 receives the FE and the DC from ITCM 32 and executes the FE and the DC. The data stored in DTCM 34 include data required for or produced by CPU 30 in operation and the context of CPU 30.
Core 20 is connected to host 10. Cores 18 and 20 are connected to each other via a remote procedural call (“RPC”). Thus, CPU 24 is allowed to require CPU 30 to access to ITCM 32 and DTCM 34. In addition, CPU 30 is allowed to access to require CPU 24 to access to ITCM 26 and DTCM 28.
When an idle situation occurs, host 10 instructs core 20 to kick off the hibernation routine. Hence, core 20 starts the hibernation routine, and sends a notification to core 18. On receiving the notification, core 18 starts the hibernation routine, and tells core 20 that core 18 is ready for the hibernation. Referring to
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At S10, host 10 provides a hibernation request.
At S12, the FE run in CPU 30 receives the hibernation request from host 10, and provides a DC write request.
At S14, according to the DC request, CPU 30 receives the DC from ITCM 32 and executes the DC to flush a DC buffer into NAND flash memory 14. Moreover, CPU 30 provides an FTL write request. The DC buffer is a block of external memory 16 (hardware) that is allocated to the DC (software).
At S16, according the FTL write request, CPU 24 receives the FTL from ITCM 26 and executes the FTL to write user data into NAND flash memory 14 from an FTL buffer. Furthermore, CPU 24 executes a callback function for the DC request. The FTL buffer is a block of external memory 16 (hardware) that is allocated to the FTL (software).
At S18, CPU 24 runs the DC to invalidate the DC buffer and provides the hibernation request for the FTL. As mentioned above, data have been written into NAND flash memory 14 from the DC buffer. That is, there are no data in the DC buffer, and there is no need to restore any data from the DC buffer. Hence, the DC buffer is invalidated.
At S20, CPU 24 runs the FTL to write User/System/SysMeta data into NAND flash memory 14, invalidates a related cache and executes a callback function for the DC request.
Briefly speaking, tasks are done at S14, S16 and S20 to write data into NAND flash memory 14 from external memory 16. At S14, a portion of the data stored in external memory 16 is written into NAND flash memory 14. At S16, another portion of the data stored in external memory 16 is written into NAND flash memory 14. At S20, the remaining data stored in external memory 16 are written into NAND flash memory 14.
At S22, the FTL records a hibernation state, a resume entry and the context of CPU 24 are written the second portion of external memory 16. Then, the FTL continues to monitor the power state to determine to enter or leave the hibernation.
At S24, the DC-callback function executes the FE callback function.
At S26, the FE callback function monitors the system state and kicks off the hibernation.
Referring to
At S32, the system recognizes hibernation and jumps to the resume entry.
At S34, the context of CPU 30 is restored, and core 20 is initialized.
At S36, the SysRoot/SysMeta/external memory 16 is restored, a heap/reap allocator is initialized, data are transferred back into ITCM 32 and DTCM from hibernation physical block 22, and core 20 is released.
Advantageously, the power management method according to the present invention shuts down the first portion of external memory 16, CPU 24 of core 18 and entire core 20 while keeping ITCM 26 and DTCM 28 of core 18 awake in the hibernation. The first portion of external memory 16, CPU 24 of core 18 and entire core 20 are shut down to reduce the power consumption in the hibernation. ITCM 26 and DTCM 28 of core 18 and the second portion of external memory 16 are kept awake in the hibernation, thereby allowing the wake-up subroutine to begin with the firmware of core 18, bypassing the boot-rom code, the boot loader code and the initializing code for core 18 to expedite the wake-up process, i.e., to reduce overall latency of SSD 12. Hence, the power management method according to the present invention reaches good balance between low power consumption and high performance.
The present invention has been described via the illustration of the preferred embodiment. Those skilled in the art can derive variations from the preferred embodiment without departing from the scope of the present invention. Therefore, the preferred embodiment shall not limit the scope of the present invention defined in the claims.
