Patent Application
20060145974
The invention relates to display systems and more particularly to display devices and methods of operating display devices.
A spatial light modulator (SLM) is a device which imparts information onto a light beam. For example, SLMs include liquid crystal devices (LCD—reflective and transmissive) and micro-electronic mirror systems (MEMS). SLMs are useful as part of display devices. One known type of display device utilizing an SLM is an LCD having a liquid crystal (LC) material which is driven by electronics located under each pixel. There are many known pixel architectures for these devices, each of which utilizes different structures and techniques to drive the pixel elements.
Various features of the invention will be apparent from the following description of preferred embodiments as illustrated in the accompanying drawings, in which like reference numerals generally refer to the same parts throughout the drawings. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the invention.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of the invention. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the invention may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
With reference to
For example, the display device 10 may include an array of pixel cells arranged in lines and one or more buffer circuits 14 may be configured to divide each line into two or more line segments. In some embodiments, the pixel segments and the buffer circuit(s) may be provided on the same integrated circuit. Alternatively, some or all of the buffer circuit(s) may be provided on one or more circuits not integrated on the same die with the pixel segments, but electrically coupled thereto.
The array of pixel cells may be addressed in a similar fashion to a memory device. Namely, a word line may select a row of the pixel array for update, and a per-column set of bit lines may provide control information to update the pixels in the selected row. However, in contrast to a memory device, the vertical height of the pixel array may be constrained by the desired physical geometry of the pixel array, as opposed to the less constraining electronic circuits of the memory device (which have no requirement for particular physical arrangement of memory cells). In conventional display devices, very long bit lines and word lines may require relatively high power for drive signals on those lines. Advantageously, some embodiments of the invention may reduce the loading on the bit lines and/or word lines and thus reduce the average power required to drive bit lines and/or word lines in a pixel array (e.g. of a spatial light modulator).
With reference to
With reference to
With reference to
The pixel elements A, B, C, and D may each be represented by a capacitor having a per-pixel capacitive load of CP. In general terms, the power utilized to drive a signal line may be written as:
P=CV2f
where C is the capacitance of the signal line, V is the rail voltage, and f is the frequency at which the line toggles. Advantageously, some embodiments of the invention may reduce C in the average case.
For example, a display device may sequentially update the rows of the pixel array. The update may start from row 0 and work toward row n−1. In a conventional display device, the bit line signal may be loaded by all of the pixel elements along a line (e.g. the column), together with some lumped line capacitance (CL). According to some embodiments, the line of pixel elements may be divided into two or more isolated segments which can be selectively enabled.
Likewise, the drive signal may be broken into multiple segments of adjacent rows. For example, each segment may be isolated from the others by a tri-state buffer.
For example, the buffer circuit 44 may include a logic gate such as an AND gate 41. The bit line drive signal BL may be provided to a drive circuit 45 which provides the drive signal to one input of the AND gate 41. The control signal 43 may be considered a segment enable signal 43 for the isolated segment 46. The first segment 42 with pixel elements A and B may correspond to ROW-0 and ROW-1 of the display device 40. The second segment 46 with pixel elements C and D may correspond to ROW-2 and ROW-3 of the display device 60. The line capacitance (CL) may be divided into two per-segment line capacitances, CL1 and CL2, which are both less than the original line capacitance.
When the first two rows (ROW-0 and ROW-1) are being updated, the segment enable signal 43 may be OFF, such that the signal BL is not passed through the AND gate 41 to the isolated segment 46. Advantageously, when the control signal 43 is OFF the signal BL is not loaded by the pixel elements C and D. In other words, the AND gate 41 is disabled and the bit line drive signal BL does not pass through to ROW-2 and ROW-3, and the pixel elements C and D do not draw significant power.
Accordingly, some embodiments of the invention may reduce the power by reducing the amount of line capacitance that must be driven for rows that are closer to the source of the bit line signal (this approach may reduce the average line capacitance). For example, the segment enable signal 43 may toggle at a much lower frequency than the bit line signal(s) BL. Also, any extra line capacitance on the segment enable signal 43 may be relatively small.
With reference to
The display device 50 includes a line of pixel elements (A, B, C, and D) divided into two or more segments 52 and 56, and two or more corresponding buffer circuits 54 (e.g. AND gate 51) and 58 (e.g. drive circuit 55) configured to isolate each of the segments (e.g. segment 56 including pixel elements C and D) from each of the other segments (e.g. segment 52 including pixel elements A and B). The buffer circuit 54 is configured to selectively provide a drive signal BL to the isolated segment 56. The buffer circuit 58 is configured to provide the drive signal BL to the pixel segment 52. In some embodiments, the buffer circuit 54 may receive a control signal 53 and may be configured to selectively provide the drive signal BL to the isolated segment 56 in accordance with the control signal 53.
In this case, the additional loading seen for ROW-2 and ROW-3 includes only the line capacitance up to the buffer circuit 58, but not the pixel load for pixel elements A and B or the line capacitance CL1. Depending on the number of rows and number of isolated segments, power consumption of the display device 50 may be reduced. Depending on the physical geometry and fabrication process, the number of separately driven pixel segments may be limited by the number of wires which may be effectively routed in the bit line direction.
In some embodiments, some power savings may be achieved even if all pixel elements in a line of pixels are not necessarily included in a pixel segment. It may not be necessary that all pixel segments have an identical number of pixel elements. Also, for some embodiments the circuits and techniques described above may be mixed such that some drive signals get passed through various pixel segments and some drive signals are directly applied to other completely isolated segments, with appropriate control signals (which may have more than one bit).
With reference to
The drive circuit 62 may include a digital ramp circuit 65 and a digital to analog converter (DAC) circuit 66 (which may be linear or non-linear). For example, the digital ramp circuit 65 may provide an N bit wide output digital ramp signal which increments from zero (0) to 2N−1 over a refresh cycle. In the illustrated embodiment, the DAC circuit 66 is connected to the output of the digital ramp circuit 65. The DAC circuit 66 may receive the digital ramp signal and output a corresponding non-linear analog ramp signal. For example, the analog ramp signal from the DAC circuit 66 is configured to refresh the array of pixel cells 1,1 through X,Y.
The SLM 61 may include a set of comparators CMP-1 through CMP-X which each receive a respective input from the pixel input buffer 64 and also the digital ramp signal. The analog ramp signal may be provided from the DAC 66 to each column's pixel cells through respective gating transistors 67 connected to respective bit lines BL-1 through BL-X. The output of the comparators are respectively provided to the gate of the gating transistors 67, such that when a pixel data value from the pixel input buffer 64 is less than the digital ramp value, the gating transistor is turned ON and the corresponding pixel cell receives the analog ramp signal. When the digital ramp value is equal to or greater than the pixel value, the gating transistor is turned OFF and the corresponding pixel cell no longer receives the analog ramp signal.
When a write line is active, the analog ramp signal is applied to the pixel cell over the bit line, for as long as the gating transistor 67 is turned ON. For example, the gating transistor 67 may be turned ON at the beginning of the refresh cycle and may stay on until the digital ramp value equals the pixel data value for the corresponding pixel cell, thus transferring an appropriate amount of charge to the pixel element in accordance with the analog ramp signal. Those skilled in the art will appreciate that the pixel cell may take various forms depending on the particular display technology of the SLM 61.
In accordance with some embodiments of the invention, the line of pixel cells arranged along a bit line signal are divided into two or more pixel line segments by a buffer circuit including a logic gate such as an AND gate 68. The bit line drive signal (e.g. BL-1) is provided to one input of the AND gate 68 and a segment enable signal EN is provided to the other input of the AND gate 68. When the EN signal is OFF, the pixel segment(s) on the output side of the AND gate 68 are isolated from the pixel segment(s) on the input side of the AND gate 68. When the EN signal is ON, the AND gate 68 selectively provides the bit line drive signal BL-1 to the pixel segment(s) on the output side of the AND gate 68. In some embodiments, three or more pixel segments may be provided together with respective corresponding buffer circuits.
Advantageously, when the rows on the input side of the AND gate 68 are being updated, the bit line drive signal is not loaded by the pixel cells on the output side of the AND gate 68, and the average line capacitance and power consumption may be reduced.
With reference to
For example, some embodiments may further include receiving a control signal (e.g. at block 73), and selectively providing the drive signal to the isolated segment in accordance with the control signal (e.g. at block 74).
For example, some embodiments may further include isolating each of the two or more segments from each of the other segments (e.g. at block 75), and selectively providing the drive signal to each isolated segment (e.g. at block 76).
For example, some embodiments may further include receiving the drive signal at one input of a logic gate (e.g. at block 77), receiving a control signal at another input of the logic gate (e.g. at block 78), and selectively outputting the drive signal from the logic gate to the isolated segment in accordance with the control signal (e.g. at block 79). For example, the drive signal may correspond to a bit line signal and the control signal may correspond to a segment enable signal.
With reference to
With reference to
In some embodiments, the system 90 further includes a first buffer circuit 105 coupled to or integrated with the first LCOS panel 95, and a second buffer circuit 106 coupled to or integrated with the second LCOS panel 96, wherein the drive circuits are respectively configured to divide respective lines of pixels on the respective LCOS panels 95 and 96 into two or more segments and selectively isolate one or more of the segments. For example, the buffer circuits 105 and 106 may be configured to selectively provide bit line drive signals to the pixel segments to reduce power consumption of the LCOS panels 95 and 96.
Substantially polarized, modulated light from the first and second LCOS panels 95 and 96 is reflected by the opposite side of the WGP 93 onto respective faces of a combining prism 98. In accordance with some embodiments of the invention, and as illustrated in
Even though single or two-panel (or two PBS) display systems have been described above, according to some embodiments, more or less panels may be utilized in various embodiments of the invention. In many embodiments, single or multi-panel-based color imaging systems may be devised without departing away from the spirit of the present invention. An example of a panel is a liquid crystal on silicon (LCOS) panel, forming screen projection displays in projection display systems. Consistent with numerous embodiments of the present invention, color schemes other than a red-green-blue (RGB) format may be employed since the RGB format is simply used here for illustration purposes only.
The foregoing and other aspects of the invention are achieved individually and in combination. The invention should not be construed as requiring two or more of such aspects unless expressly required by a particular claim. Moreover, while the invention has been described in connection with what is presently considered to be the preferred examples, it is to be understood that the invention is not limited to the disclosed examples, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and the scope of the invention.
