Power management integrated circuit

Abstract

A power management integrated circuit (PMIC) is disclosed. The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of the voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.

Description

FIELD OF THE DISCLOSURE

The present disclosure is related to a power management integrated circuit (PMIC).

BACKGROUND

Mobile communication devices have become increasingly common in current society for providing wireless communication services. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

The redefined user experience requires higher data rates offered by such advanced wireless communication technologies as fifth-generation new-radio (5G-NR). To achieve higher data rates, a mobile communication device may employ a power amplifier(s) to amplify a radio frequency (RF) signal(s) (e.g., maintaining sufficient energy per bit) before transmission. Given that the power amplifier(s) requires a supply voltage(s) for operation, a power management integrated circuit (PMIC) is thus required to generate and provide the supply voltage(s) to the power amplifier(s).

Given that the PMIC often needs to concurrently generate multiple supply voltages for multiple power amplifiers, the PMIC typically includes multiple direct-current to direct-current (DC-DC) power inductors. As a result, the PMIC can claim a larger portion of precious real estate in the mobile communication device. Hence, it is desirable to reduce the number of DC-DC power inductors in the PMIC to help reduce footprint of the PMIC.

SUMMARY

Embodiments of the disclosure relate to a power management integrated circuit (PMIC). The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.

In one aspect, a PMIC is provided. The PMIC includes a voltage generation circuit configured to generate and maintain a number of voltages during at least one voltage generation period based on a reference voltage. The PMIC also includes a voltage modulation circuit configured to modulate the reference voltage during the at least one voltage generation period. The PMIC also includes a control circuit. The control circuit is configured to divide the at least one voltage generation period into a number of voltage generation intervals for generating the number of voltages, respectively. The control circuit is also configured to cause the voltage modulation circuit to modulate the reference voltage to a respective level during each of the number of voltage generation intervals. The control circuit is also configured to cause the voltage generation circuit to generate and maintain each of the number of voltages in a respective one of the number of voltage generation intervals based on the respective level of the reference voltage modulated during the respective one of the number of voltage generation intervals.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of an exemplary power management integrated circuit (PMIC) configured according to embodiments of the present disclosure to concurrently generate multiple voltages without requiring multiple direct-current to direct-current (DC-DC) power inductors;

FIG. 2 is a schematic diagram providing an exemplary illustration of a voltage generation period during which the PMIC of FIG. 1 can be configured to concurrently generate the voltages;

FIG. 3 is a schematic diagram providing an exemplary illustration of a voltage modulation circuit provided in the PMIC of FIG. 1 and configured according to an embodiment of the present disclosure to include a single DC-DC power inductor;

FIG. 4 is a schematic diagram providing exemplary illustration of a voltage generation circuit provided in the PMIC of FIG. 1 and configured according to an embodiment of the present disclosure to generate and maintain the voltages;

FIGS. 5A and 5B are signal diagrams illustrating exemplary operations of the PMIC of FIG. 1 in accordance with embodiments of the present disclosure; and

FIG. 6 is a schematic diagram providing an exemplary illustration of a voltage generation circuit provided in the PMIC of FIG. 1 and configured according to an alternative embodiment of the present disclosure.

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to a power management integrated circuit (PMIC). The PMIC is configured to generate multiple voltages during a voltage generation period(s). In embodiments disclosed herein, the voltage generation period(s) is divided into multiple voltage generation intervals. A voltage generation circuit is configured to generate and maintain a respective one of the voltages during a respective one of voltage generation intervals based on a reference voltage modulated for the respective one of the voltage generation intervals to thereby make the voltages concurrently available during the voltage generation period(s). Moreover, a voltage modulation circuit is configured to modulate the reference voltage in each of the voltage generation intervals based on a single direct-current to direct-current (DC-DC) power inductor. As a result, the PMIC can concurrently support multiple load circuits (e.g., power amplifiers) with significantly reduced footprint.

In this regard, FIG. 1 is a schematic diagram of an exemplary PMIC configured according to embodiments of the present disclosure to generate multiple voltages V_CC1-V_CCN without requiring multiple DC-DC power inductors. In an embodiment, the PMIC 10 is configured to generate and maintain the voltages V_CC1-V_CCN during at least one voltage generation period (T) as illustrated in FIG. 2. FIG. 2 is a schematic diagram providing an exemplary illustration of the voltage generation period (T) during which the PMIC 10 of FIG. 1 can be configured to concurrently generate the voltages V_CC1-V_CCN.

In a non-limiting example, the voltage generation period (T) can be equally divided into multiple time slots (Δt). Accordingly, multiple voltage generation intervals dT₁-dT_N can be further defined to each include a respective one or more of the time slots (Δt). Each of the voltage generation intervals dT₁-dT_N can be longer if a respective one of the voltages V_CC1-V_CCN is higher or be shorter if a respective one of the voltages V_CC1-V_CCN is lower. For example, the voltage generation interval dT₁ can be configured to include two time slots (2Δt) for generating a higher voltage V_CC1. In contrast, the voltage generation intervals dT₂ and dT_N are configured to each include one time slot (Δt) for generating lower voltages V_CC2 and V_CCN. Accordingly, the PMIC 10 can be configured to generate and maintain each of the voltages V_CC1-V_CCN during a respective one of the voltage generation intervals dT₁-dT_N.

In this regard, the voltage generation intervals dT₁-dT_N appear to be analogous to a time-division schedule for generating the voltages V_CC1-V_CCN. However, as discussed in detail below, the PMIC 10 can be further configured to maintain each of the voltages V_CC1-V_CCN at a respective constant level during each of the voltage generation intervals dT₁-dT_N. As such, despite that the voltages V_CC1-V_CCN are each generated in a time-division fashion, the PMIC 10 can nevertheless make the voltages V_CC1-V_CCN concurrently available during the voltage generation period (T). Accordingly, the voltage generation period (T) should be determined by taking into consideration as to how long the PMIC 10 can maintain the voltages V_CC1-V_CCN and to what degree a ripple can be tolerated in each of the voltages V_CC1-V_CC.

With reference back to FIG. 1, the PMIC 10 includes a voltage generation circuit 12 and a voltage modulation circuit 14. The voltage generation circuit 12 is configured to generate and maintain a respective one of the voltages V_CC1-V_CCN during a respective one of voltage generation intervals dT₁-dT_N based on a reference voltage V_REF modulated for the respective one of the voltage generation intervals dT_n-dT_N. The voltage modulation circuit 14 is configured to modulate the reference voltage V_REF in each of the voltage generation intervals dT₁-dT_N.

The PMIC 10 further includes a control circuit 16, which can be a field programmable gate array (FPGA), as an example. The control circuit 16 is configured to divide the voltage generation period (T) into the voltage generation intervals dT₁-dT_N. Accordingly, the control circuit 16 can provide a target signal 18 to cause the voltage modulation circuit 14 to modulate the reference voltage V_REF to a respective level during each of the voltage generation intervals dT₁-dT_N. In addition, the control circuit 16 can assert multiple control voltages CTRL₁-CTR_N to thereby cause the voltage generation circuit 12 to generate and maintain each of the voltages V_CC1-V_CCN in a respective one of the voltage generation intervals dT₁-dT_N based on the respective level of the reference voltage V_REF modulated during the respective one of the voltage generation intervals dT₁-dT_N. Herein, asserting the control voltages CTRL₁-CTR_N means increasing the control voltages CTRL₁-CTR_N above respective threshold voltages. In contrast, de-asserting the control voltages CTRL₁-CTR_N means decreasing the control voltages CTRL₁-CTR_N below the respective threshold voltages.

Given that the voltages V_CC1-V_CCN are each generated in a time-division fashion, the voltage modulation circuit 14 can also modulate the reference voltage V_REF in the time-division fashion. As such, it is not necessary for the voltage modulation circuit 14 to concurrently modulate the reference voltage V_REF in the voltage generation intervals dT₁-dT_N, thus making it possible for the voltage modulation circuit 14 to operate based on a single DC-DC power inductor to help reduce footprint of the PMIC 10.

In this regard, FIG. 3 is a schematic diagram providing an exemplary illustration of the voltage modulation circuit 14 in the PMIC 10 of FIG. 1 configured according to an embodiment of the present disclosure to modulate the reference voltage V_REF based on a single DC-DC power inductor L_DC-DC. Common elements between FIGS. 1 and 3 are shown therein with common element numbers and will not be re-described herein.

In a non-limiting example, the voltage modulation circuit 14 includes a voltage amplifier 20 (denoted as “VA”), an offset capacitor C_OFF, a multi-level charge pump (MCP) 22, the DC-DC power inductor L_DC-DC, and a switch S_OFF. The voltage amplifier 20 is configured to generate an initial reference voltage VAMP based on a target voltage V_TGT, which is received as part of the target signal 18. The offset capacitor C_OFF is configured to raise the initial reference voltage V_AMP by an offset voltage V_OFF to thereby generate the reference voltage V_REF (V_REF=V_AMP+V_OFF) at a reference node 24. In this regard, the voltage amplifier and the offset capacitor C_OFF are collectively responsible for modulating the reference voltage V_REF in each of the voltage generation intervals dT₁-dT_N. Notably, by using the offset capacitor C_OFF to raise the initial reference voltage V_AMP, the initial reference voltage V_AMP will be lower than the reference voltage V_REF, thus helping to improve efficiency of the voltage amplifier 20.

The MCP 22 is configured to generate a DC voltage V_DC as a function of a battery voltage V_BAT and in accordance with a defined duty cycle. In a non-limiting example, the defined duty cycle can also be configured via the target signal 18. The DC-DC power inductor L_DC-DC-DC is configured to induce a reference current I_REF based on the DC voltage V_DC to thereby charge the offset capacitor C_OFF to the offset voltage V_OFF. The switch S_OFF may be closed when the offset capacitor C_OFF is charged towards the offset voltage V_OFF and opened when the offset capacitor C_OFF is charged to the offset voltage V_OFF. In this regard, the offset voltage V_OFF is said to be modulated by the reference current I_REF.

By modulating the reference voltage V_REF and/or the reference current I_REF, the voltage modulation circuit 14 further modulates a reference power P_REF (P_REF=V_REF*I_REF) at the reference node 24. In this regard, the voltage modulation circuit 14 may also be referred to as a power modulation circuit. In one embodiment, the reference current I_REF can be so generated as a constant current during the voltage generation period (T). As such, the voltage modulation circuit 14 can modulate the reference power P_REF by modulating the reference voltage V_REF.

With reference back to FIG. 1, the PMIC 10 can include multiple voltage outputs 26(1)-26(N), each coupled to a respective one of multiple load circuits LOAD₁-LOAD_N (e.g., power amplifier circuits). The voltage generation circuit 12 is coupled to the voltage outputs 26(1)-26(N) and configured to concurrently provide the voltages V_CC1-V_CCN to the voltage outputs 26(1)-26(N), respectively, during the voltage generation period (T). Notably, the load circuits LOAD₁-LOAD_N can each act as a current source. As such, the load circuits LOAD₁-LOAD_N can each induce a respective one of multiple load currents I_LOAD-1-I_LOADN in response to receiving a respective one of the voltages V_CC1-V_CCN. Accordingly, the load circuits LOAD₁-LOAD_N will each consume a respective one of multiple load powers P_LOAD-1-P_LOAD-N (P_LOAD-i=V_CCi*I_LOAD-i, 1≤i≤N).

The voltage generation circuit 12 may be configured according to an embodiment illustrated in FIG. 4. FIG. 4 is a schematic diagram providing an exemplary illustration of the voltage generation circuit 12 in the PMIC 10 of FIG. 1 configured according to an embodiment of the present disclosure. Common elements between FIGS. 1 and 4 are shown therein with common element numbers and will not be re-described herein.

In a non-limiting example, the voltage generation circuit 12 includes multiple holding capacitors C_HOLD-1-C_HOLD-N each coupled between a respective one of the voltage outputs 26(1)-26(N) and a ground (GND). The voltage generation circuit 12 also includes multiple switched capacitor-based voltage converters 28(1)-28(N) each configured to generate a respective one of multiple charging voltages V_CHARGE-1-V_CHARGE-N in a respective one of the voltage generation intervals dT₁-dT_N based on the reference voltage V_REF modulated during the respective one of the voltage generation intervals dT₁-dT_N. Each of the charging voltages V_CHARGE-1-V_CHARGE-N can cause a respective one of multiple charge currents I_CHARGE-1-I_CHARGE-N to thereby charge a respective one of the holding capacitors C_HOLD-1-C_HOLD-N to a respective one of the voltages V_CC1-V_CCN during a respective one of the voltage generation intervals dT₁-dT_N.

In this regard, the holding capacitors C_HOLD-1-C_HOLD-N are still being charged sequentially to the voltages V_CC1-V_CCN during the voltage generation intervals dT₁-dT_N. However, each of the holding capacitors C_HOLD-1-C_HOLD-N is so chosen to have a respective capacitance that can maintain a respective one of the voltages V_CC1-V_CCN for up to the voltage generation period (T). As a result, the voltages V_CC1-V_CCN can be simultaneously available at the voltage outputs 26(1)-26(N) during the voltage generation period (T). Hence, each of the voltage generation intervals dT₁-dT_N must be long enough and each of the charge currents I_CHARGE-1-I_CHARGE-N must be large enough to ensure that a respective one of the holding capacitors C_HOLD-1-C_HOLD-N can be charged to a respective one of the voltages V_CC1-V_CCN during a respective one of the voltage generation intervals dT₁-dT_N.

The switched capacitor-based voltage converters 28(1)-28(N) can be implemented based on any known switched capacitor-based voltage converter that does not include a DC-DC power inductor. In one embodiment, each of the switched capacitor-based voltage converters 28(1)-28(N) can be a switched capacitor-based buck voltage converter. In this regard, each of the switched capacitor-based voltage converters 28(1)-28(N) can operate based on a respective one of multiple conversion ratios x₁-x_N that is less than or equal to 1 (x₁-x_N≤1). Accordingly, each of the switched capacitor-based voltage converters 28(1)-28(N) is configured to reduce or pass the reference voltage V_REF modulated in a respective one of the voltage generation intervals dT₁-dT_N to thereby generate a respective one of the charge voltages V_CHARGE-1-V_CHARGE-N that is lower than or equal to the reference voltage V_REF.

In another embodiment, each of the switched capacitor-based voltage converters 28(1)-28(N) can be a switched capacitor-based boost voltage converter. In this regard, each of the switched capacitor-based voltage converters 28(1)-28(N) can operate based on a respective one of the conversion ratios x₁-x_N that is greater than 1 (x₁-x_N>1). Accordingly, each of the switched capacitor-based voltage converters 28(1)-28(N) is configured to boost the reference voltage V_REF modulated in a respective one of the voltage generation intervals dT₁-dT_N to thereby generate a respective one of the charge voltages V_CHARGE-1-V_CHARGE-N that is higher than the reference voltage V_REF. Notably, by boosting the reference V_REF to generate the charge voltages V_CHARGE-1-V_CHARGE-N, the voltage modulation circuit 14 can be configured to reduce the reference voltage V_REF during each of the voltage generation intervals dT₁-dT_N, thus helping to improve efficiency of the voltage modulation circuit 14. In addition, the voltage modulation circuit 14 may also reduce the reference current I_REF during each of the voltage generation intervals dT₁-dT_N, thus making it possible to reduce the size of the DC-DC power inductor L_DC-DC.

In one embodiment, the conversion ratios x₁-x_N can be so determined to be different from one another. Accordingly, the switched capacitor-based voltage converters 28(1)-28(N) will each operate based on a different one of the conversion ratios x₁-x_N. In another embodiment, the conversion ratios x₁-x_N can be so determined to be identical. Accordingly, the switched capacitor-based voltage converters 28(1)-28(N) will each operate based on a common conversion ratio. The conversion ratios x₁-x_N can be determined by the control circuit 16 or preconfigured in the switched capacitor-based voltage converters 28(1)-28(N).

FIGS. 5A and 5B are signal diagrams illustrating exemplary operations of the PMIC of FIG. 1 in accordance with embodiments of the present disclosure. The illustrations discussed in FIGS. 5A and 5B are based on a set of assumptions. It should be appreciated that the assumptions are merely made for the convenience of illustration and shall not be considered as limiting by any means. Elements in FIGS. 1 and 4 are referenced in FIGS. 5A and 5B by respective element numbers and will not be re-described herein.

Herein, the voltage generation circuit 12 is assumed to generate the three voltages V_CC1, V_CC2, and V_CC3 for the three load circuits LOAD₁, LOAD₂, and LOAD₃, respectively. In this regard, it is assumed that there will be three load currents I_LOAD-1, I_LOAD-2, and I_LOAD-3 flowing through the load circuits LOAD₁, LOAD₂, and LOAD₃, respectively.

The voltage generation circuit 12 is also assumed to include the three switched capacitor-based voltage converters 28(1), 28(2), and 28(3) (represented by 28(N)) and the three holding capacitors C_HOLD-1, C_HOLD-2, and C_HOLD-3. The holding capacitors C_HOLD-1, C_HOLD-2, and C_HOLD-3 are assumed to be coupled to the three voltage outputs 26(1), 26(2), and 26(3), respectively. The voltage outputs 26(1), 26(2), and 26(3) are assumed to be coupled to three load circuits LOAD₁, LOAD₂, and LOAD₃, respectively.

Accordingly, the voltage generation period (T) is assumed to be divided into three voltage generation intervals dT₁, dT₂, and dT₃ (T=dT₁+dT₂+dT₃) for generating the voltages V_CC1, V_CC2, and V_CC3, respectively. In this example, the voltage generation period (T) is assumed to include four time slots (T=4Δt), which are divided unevenly among the voltage generation intervals dT₁, dT₂, and dT₃. The voltage generation interval dT₁ is assumed to include 2 time slots (dT₁=2Δt=½T), while the voltage generation intervals dT₂ and dT₃ are assumed to each include 1 time slot (dT₂=dT₃=Δt=¼ T).

The switched capacitor-based voltage converters 28(1), 28(2), and 28(3) are assumed to operate based on three conversion ratios x₁, x₂, and x₃ to convert the reference voltage V_REF modulated during the voltage generation intervals dT₁, dT₂, and dT₃ into three charging voltages V_CHARGE-1, V_CHARGE-2, and V_CHARGE-3, respectively. The charging voltages V_CHARGE-1, V_CHARGE-2, and V_CHARGE-3, in turn, are assumed to cause three charging currents I_CHARGE-1, I_CHARGE-2, and I_CHARGE-3 for charging the holding capacitors C_HOLD-1, C_HOLD-2, and C_HOLD-3 during the voltage generation intervals dT₁, dT₂, and dT₃, respectively.

With reference to FIG. 5A, in a non-limiting example, the switched capacitor-based voltage converters 28(1), 28(2), and 28(3) are each configured to operate as a switched capacitor-based boost voltage converter based on a common conversion ratio x (x=x₁=x₂=x₃). The load currents I_LOAD-1, I_LOAD-2, and I_LOAD-3 as well as the voltages V_CC1, V_CC2, and V_CC3 are prestored in the PMIC 10 and thus considered known to the control circuit 16. In this example, it is further assumed that V_CC1=1 Volt (V), V_CC2=2 V, V_CC3=3 V, I_LOAD-1=2 Amp (A), I_LOAD-2=1 A, I_LOAD-3=1 A, and x=4.

The control circuit 16 may determine each of the charge currents I_CHARGE-1, I_CHARGE-2, and I_CHARGE-3 as a function of a respective one of the load currents I_LOAD-1, I_LOAD-2, and I_LOAD-3, as expressed in the equations below, for charging the holding capacitors C_HOLD-1, C_HOLD-2, and C_HOLD-3 during the voltage generation intervals dT₁, dT₂, and dT₃, respectively.I_CHARGE-1=I_LOAD-1*(T/dT₁)=4 A I_CHARGE-2=I_LOAD-2*(T/dT₂)=4 A I_CHARGE-3=I_LOAD-3*(T/dT₃)=4 A

The control circuit 16 can further determine the reference current I_REF during the voltage generation intervals dT₁, dT₂, and dT₃ in accordance with the equations below.I_REF during dT₁(I_REF1)=I_CHARGE-1/X=4 A/4=1 A I_REF during dT₂(I_REF2)=I_CHARGE-2/X=4 A/4=1 A I_REF during dT₃(I_REF3)=I_CHARGE-3/X=4 A/4=1 A

In this regard, the reference current I_REF is a constant current across the voltage generation intervals dT₁, dT₂, and dT₃. The control circuit 16 can further determine the reference voltage V_REF during the voltage generation intervals dT₁, dT₂, and dT₃ in accordance with the equations below.V_REF during dT₁(V_REF1)=x*V_CC1=4*1 V=4 V V_REF during dT₂(V_REF2)=x*V_CC2=4*2 V=8 V V_REF during dT₃(V_REF3)=x*V_CC3=4*4 V=12 V

Accordingly, an average of the reference power P_REF as modulated by the voltage modulation circuit 14 during the voltage generation period (T) can be expressed in the equation below.

$\begin{array}{c}\mathrm{AVG}\left(P_{\mathrm{REF}}\right)=\left({\mathrm{dT}}_1*V_{\mathrm{REF}1}*I_{\mathrm{REF}1}+{\mathrm{dT}}_2*V_{\mathrm{REF}2}*I_{\mathrm{REF}2}+{\mathrm{dT}}_3*V_{\mathrm{REF}3}*I_{\mathrm{REF}3}\right)/T\\ =\left(1/2T*4V*1A+1/4T*8V*1A+1/4T*12V*1A\right)/T=7\mathrm{Watt}\left(W\right)\end{array}$

Similarly, an average load power AVG(P_LOAD) consumed by the load circuits LOAD₁, LOAD₂, and LOAD₃ during the voltage generation period (T) can be expressed in the equation below.

$\begin{array}{c}\mathrm{AVG}\left(P_{\mathrm{LOAD}}\right)=\left(V_{\mathrm{CC}1}*I_{\mathrm{LOAD}-1}+V_{\mathrm{CC}2}*I_{\mathrm{LOAD}-2}+V_{\mathrm{CC}3}*I_{\mathrm{LOAD}3}\right)\\ =1V*2A+2V*1A+3V*1A=7W\end{array}$

With reference to FIG. 5B, the control circuit 16 may control each of the switched capacitor-based voltage converters 28(1), 28(2), and 28(3) via a respective one of three control voltages CTRL₁, CTRL₂, and CTR₃. The control circuit 16 may assert the control voltage CTRL₁ prior to or at time T₁ to cause the switched capacitor-based voltage converter 28(1) to charge the holding capacitor C_HOLD-1, assert the control voltage CTRL₂ prior to or at time T₂ to cause the switched capacitor-based voltage converter 28(2) to charge the holding capacitor C_HOLD-2, and assert the control voltage CTRL₃ prior to or at time T₃ to cause the switched capacitor-based voltage converter 28(3) to charge the holding capacitor C_HOLD-3. The control circuit 16 may be further configured to de-assert the control voltage CTRL₁ at or after time T₂, de-assert the control voltage CTRL₂ at or after time T₃, and de-assert the control voltage CTRL₃ at or after time T₄.

With reference back to FIG. 1, the PMIC 10 may be configured to include a memory circuit 30, which can be a random-access memory (RAM) circuit, a flash storage circuit, or a register bank, as an example. The memory circuit 30 may be programmed to store the voltages V_CC1-V_CCN and the load currents I_LOAD-1-I_LOADN. The memory circuit 30 may be further programmed to store the conversion ratios x₁-x_N of the switched capacitor-based voltage converters 28(1)-28(N), as shown in FIG. 4. In a non-limiting example, the memory circuit 30 can be programmed via a control bus 32, such as a radio frequency front-end (RFFE) bus or a single-wire serial bus, as an example. Accordingly, the control circuit 16 may retrieve the voltages V_CC1-V_CCN, the load currents I_LOAD-1-I_LOADN, and/or the conversion ratios x₁-x_N from the memory circuit 30.

The PMIC may also include multiple feedback circuits FB1-FB_N, each configured to provide a respective one of a plurality of voltage feedbacks V_CC1-FB-V_CCN-FB to the control circuit 16. Notably, each of the voltage feedbacks V_CC1-FB-V_CCN-FB can be proportionally related to a respective one of the voltages V_CC1-V_CCN. Accordingly, the control circuit 16 may control the voltage modulation circuit 14 to adjust the reference voltage V_REF during any of the voltage generation intervals dT₁-dT_N based on a respective one of the voltage feedbacks V_CC1-FB-V_CCN-FB.

Alternative to the voltage generation circuit 12 of FIG. 4, it is also possible to implement the voltage generation circuit 12 based on alternative configurations. In this regard, FIG. 6 is a schematic diagram of an exemplary voltage generation circuit 34 configured according to another embodiment of the present disclosure. Common elements between FIGS. 1, 4, and 6 are shown therein with common element numbers and will not be re-described herein.

The voltage generation circuit 34 includes multiple hybrid switch circuits 36(1)-36(N) (denoted as “SW/LDO”). Each of the hybrid switch circuits 36(1)-36(N) is coupled to a respective one of the holding capacitors C_HOLD-1-C_HOLD-N and can operate either as a switch or a low dropout (LDO) regulator. Specifically, each the hybrid switch circuits 36(1)-36(N) can provide the reference voltage V_REF as a respective one of the charging voltages V_CHARGE-1-V_CHARGE-N directly to a respective one of the holding capacitors C_HOLD-1-C_HOLD-N when operating as the switch. In contrast, when operating as the LDO regulator, each of the hybrid switch circuits 36(1)-36(N) regulates the reference voltage V_REF before providing to a respective one of the holding capacitors C_HOLD-1-C_HOLD-N as a respective one of the charging voltages V_CHARGE-1-V_CHARGE-N.

In one embodiment, the control circuit 16 may cause the voltage modulation circuit 14 to modulate the reference voltage V_REF in each of the voltage generation intervals dT₁-dT_N to be equal to a respective one of the voltages V_CC1-V_CCN. In this regard, the control circuit 16 may cause each of the hybrid switch circuits 36(1)-36(N) to operate as the switch.

In another embodiment, the control circuit 16 may cause the voltage modulation circuit to modulate the reference voltage in each of the voltage generation intervals dT₁-dT_N to be higher than a respective one of the voltages V_CC1-V_CCN. In this regard, the control circuit 16 may cause each of the hybrid switch circuits 36(1)-36(N) to operate as the LDO regulator.

The voltage generation circuit 34 may also include a maximum voltage control circuit 38. The maximum voltage control circuit 38 may be configured to ensure that the reference voltage V_REF is always greater than or equal to a respective one of the voltages V_CC1-V_CCN during a respective one of the voltage generation intervals dT₁-dT_N such that none of charging currents I_CHARGE-1-I_CHARGE-N can flow back toward the voltage modulation circuit 14.

With reference back to FIG. 1, the PMIC 10 may also include an auxiliary voltage generation circuit 40 coupled to the voltage generation circuit 12. The auxiliary voltage generation circuit 40 may be configured generate multiple auxiliary voltages V_ASS1-V_ASSN to assist in charging the holding capacitors C_HOLD-1-C_HOLD-N during the voltage generation intervals dT₁-dT_N, respectively. Notably, the auxiliary voltages V_ASS1-V_ASSN may each cause a respective one of the charging currents I_CHARGE-1-I_CHARGE-N to increase, thus helping to speed up charging of a respective one of the holding capacitors C_HOLD-1-C_HOLD-N during a respective one of the voltage generation intervals dT₁-dT_N. In a non-limiting example, the auxiliary voltage generation circuit 40 may generate each of the auxiliary voltages V_ASS1-V_ASSN during a respective one of the voltage generation intervals dT₁-dT_N as a function of the reference voltage V_REF modulated during the respective one of the voltage generation intervals dT₁-dT_N.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A power management integrated circuit (PMIC) comprising: a voltage generation circuit configured to generate and maintain a plurality of voltages during at least one voltage generation period based on a reference voltage;a voltage modulation circuit comprising: a voltage amplifier configured to generate an initial reference voltage based on a target voltage; andan offset capacitor configured to raise the initial reference voltage by an offset voltage to generate the reference voltage during the at least one voltage generation period; anda control circuit configured to: divide the at least one voltage generation period into a plurality of voltage generation intervals for generating the plurality of voltages, respectively;cause the voltage modulation circuit to modulate the reference voltage to a respective level during each of the plurality of voltage generation intervals; andcause the voltage generation circuit to generate and maintain each of the plurality of voltages in a respective one of the plurality of voltage generation intervals based on the respective level of the reference voltage modulated during the respective one of the plurality of voltage generation intervals and maintain each of the plurality of voltages till an end of the at least one voltage generation period.

2. The PMIC of claim 1, wherein the voltage generation circuit is further configured to concurrently provide the plurality of voltages to a plurality of voltage outputs, respectively, during the at least one voltage generation period.

3. The PMIC of claim 2, wherein the voltage generation circuit comprises a plurality of holding capacitors each coupled between a respective one of the plurality of voltage outputs and a ground, the voltage generation circuit is further configured to charge each of the plurality of holding capacitors to a respective one of the plurality of voltages during a respective one of the plurality of voltage generation intervals.

4. The PMIC of claim 3, wherein the control circuit is further configured to: divide the at least one voltage generation period into a plurality of time slots; anddetermine the plurality of voltage generation intervals to each include a respective one or more of the plurality of time slots whereby the voltage generation circuit can charge a respective one of the plurality of holding capacitors to a respective one of the plurality of voltages within a respective one of the plurality of voltage generation intervals.

5. The PMIC of claim 3, wherein each of the plurality of holding capacitors is configured to maintain the respective one of the plurality of voltages at the respective one of the plurality of voltage outputs during the at least one voltage generation period to thereby cause the plurality of voltage outputs to output the plurality of voltages concurrently during the at least one voltage generation period.

6. The PMIC of claim 3, wherein the control circuit is further configured to: determine a plurality of load currents;determine a plurality of charging currents each as a function of a respective one of the plurality of load currents, respectively; andcause the voltage generation circuit to generate the plurality of charging currents to charge the plurality of holding capacitors to the plurality of voltages during the plurality of voltage generation intervals, respectively.

7. The PMIC of claim 6, further comprising a memory circuit configured to: store a respective value of each of the plurality of voltages; andstore a respective value of each of the plurality of load currents.

8. The PMIC of claim 7, wherein the control circuit is further configured to retrieve the plurality of load currents and the plurality of voltages from the memory circuit.

9. The PMIC of claim 6, wherein the voltage generation circuit further comprises a plurality of switched capacitor-based voltage converters each coupled to a respective one of the plurality of holding capacitors, the plurality of switched capacitor-based voltage converters is configured to generate the plurality of charging currents to charge the plurality of holding capacitors, respectively.

10. The PMIC of claim 9, wherein each of the plurality of switched capacitor-based voltage converters is configured to operate based on a respective one of a plurality of conversion ratios to convert the reference voltage modulated in each of the plurality of voltage generation intervals into a respective one of a plurality of charging voltages to thereby cause a respective one of the plurality of charging currents to be generated.

11. The PMIC of claim 10, wherein the control circuit is further configured to cause the voltage modulation circuit to modulate the reference voltage in each of the plurality of voltage generation intervals as a function of a respective one of the plurality of conversion ratios and a respective one of the plurality of voltages.

12. The PMIC of claim 11, wherein the control circuit is further configured to: receive a plurality of voltage feedbacks each corresponding to a respective one of the plurality of voltages; andcontrol the voltage modulation circuit to adjust the reference voltage in any of the plurality of voltage generation intervals based on a respective one of the plurality of voltage feedbacks.

13. The PMIC of claim 6, wherein the voltage generation circuit further comprises a plurality of hybrid switch circuits each coupled to a respective one of the plurality of holding capacitors, each of the plurality of hybrid switch circuits is configured to: operate as a switch to provide the reference voltage directly to a respective one of the plurality of holding capacitors; andoperate as a low dropout (LDO) regulator to regulate the reference voltage before providing the reference voltage to the respective one of the plurality of holding capacitors.

14. The PMIC of claim 13, wherein the control circuit is further configured to: cause the voltage modulation circuit to modulate the reference voltage in each of the plurality of voltage generation intervals to be equal to a respective one of the plurality of voltages; andcause each of the plurality of hybrid switch circuits to operate as the switch.

15. The PMIC of claim 13, wherein the control circuit is further configured to: cause the voltage modulation circuit to modulate the reference voltage in each of the plurality of voltage generation intervals to be higher than a respective one of the plurality of voltages; andcause each of the plurality of hybrid switch circuits to operate as the LDO regulator.

16. The PMIC of claim 3, further comprising an auxiliary voltage generation circuit configured to generate a plurality of auxiliary voltages to assist in charging the plurality of holding capacitors in the plurality of voltage generation intervals, respectively.

17. The PMIC of claim 1, wherein the voltage modulation circuit further comprises: a multi-level charge pump (MCP) configured to generate a direct current (DC) voltage as a function of a battery voltage in accordance with a defined duty cycle; anda DC to DC (DC-DC) power inductor configured to induce a reference current based on the DC voltage to thereby charge the offset capacitor to the offset voltage.

18. The PMIC of claim 17, wherein the reference current is a constant current during the at least one voltage generation period.

19. The PMIC of claim 1, wherein each of the plurality of voltages is a constant voltage during the at least one voltage generation period.