Patent Application
20080292031
This invention relates to a power management method for radio frequency (RF) receivers and a corresponding receiver.
To maximize usage of the available bandwidth, a number of multiple access technologies have been implemented to allow more than one subscriber to communicate simultaneously in a communication system. These multiple access technologies include for example, time division multiple access (TDMA), frequency division multiple access (FDMA), code division multiple access (CDMA), and coded orthogonal frequency division multiplexing (COFDM). These technologies assign each system subscriber to a specific traffic channel that transmits and receives subscriber voice/data signals via a selected time slot, a selected frequency, a selected unique code, or a combination thereof. The data received during a time slot is called a burst of data.
Typically, radio frequency (RF) receivers comprise components to receive and process every kind of signal. All or some components of an RF receiver can operate in binary modes, i.e., some components such as the RF front-end or the entire base band demodulator, are either in idle or active mode.
Known power management methods take advantage of the receiver abilities to deactivate the receiver between reception periods, leaving only a monitoring component active in order to detect the reception of a new burst of data. It is also possible to use the energy of the received signal to trigger the powering up of the receiver without the use of a monitoring component.
In the case of digital video broadcasting handheld (DVB-H), the receiver is put in an idle mode between the receptions of two consecutive bursts of data dedicated to the service being selected. The RF receiver therefore activates entirely only upon receipt of the beginning of a burst of data.
It is an object of the invention to provide a device for receiving RF signal having low power consumption.
With the following and other objects in view, the invention features a device for receiving a radio frequency signal as recited in claim 1.
According to the device of the invention, all the processing elements are not activated together at the activation time: some processing elements are activated only at a later time. Until that time they do not consume power, which permits to obtain a low consumption device.
Other advantages of the receiver are recited in the dependant claims.
As recited in claim 7, the invention also features a power management method.
Other features of the method are recited in the dependent claims.
These and other aspects of the dynamic power management method and the corresponding device will be apparent from the following description, claims, and from the drawings in which:
Referring to
The RF receiver 10 further comprises a power management module 18 for activating/deactivating the processing elements 16.
Depending on the reception quality, the signal must be processed in by a certain number of processing elements 16. More precisely, the amount of processing needed to demodulate the signal increases as the reception quality decreases. When the reception quality is low, the signal must therefore be processed by many processing elements.
Several data paths are thus possible within the demodulating unit 12 between its input and output, depending on the processing elements through which data must be processed.
The processing elements 16 are grouped in functional modules 16A . . . 16G so that the processing elements 16 of a single functional module 16A . . . 16G are all managed at the same time.
In the example described, the processing elements 16 are grouped in seven consecutive functional modules, from input to output: a reception module 16A, a reception control module 168, a fast Fourier transform (FFT) module 16C, a frequency channel estimation module 16D, a first decoder module 16E, a second decoder module 16F and a demultiplexing module 16G.
In the example, only some processing elements are described, for clarity reason. It will become apparent for the ones skilled in the art that other processing elements may be used in the demodulating unit, without departing from the scope of the invention. Moreover, the functional modules may be defined in another way, i.e. the processing elements may be grouped in another way, still without departing from the scope of the invention.
Accordingly, the reception module 16A comprises a front-end 20 outputting a base band signal.
The reception control module 16B comprises an analog to digital converter 22 and an amplifier gain controller (AGC) 24 for generating a gain signal from the digitized signal in order to control the front end 20.
The FFT module 16C comprises a time and frequency offsets compensator 26 outputting a compensated signal to a FFT processing element 28. The FFT module 16C further comprises a symbol, time and frequency synchronization element 30 for controlling the time and frequency offsets compensator 26 and the FFT processing element 28.
The frequency channel estimation module 16D comprises a frequency channel estimation unit 32 with several processing elements 32j, among which a channel estimator 321 and a first order channel derivate estimator 322, both using the frequency signal outputted by the FFT processing element 20B.
The first decoder module 16E comprises an equalization unit 34 with several processing elements 34j. The equalization unit 34 is intended for equalizing the frequency signal outputted by the FFT processing element 28. The equalization unit 34 is controlled by the processing elements 32i of the channel estimation module 16D.
The first decoder module 24 further comprises a Viterbi decoder 36 for decoding the equalized signal and outputting a sequence of bits. The Viterbi decoder 36 comprises several processing elements 36k that must be used all or in part depending on the quality of the signal.
The second decoder module 16F comprises a Reed Solomon decoder 38 for generating a byte transport stream from the bit sequence outputted by the Viterbi decoder 36.
The demultiplexing module 16G comprises a demultiplexing element 40 and a decoder 42 for outputting IP data. The demultiplexing element 40 is able to extract information relative the reception instant of a next burst of data from a burst of data being demodulated. This point of the invention will be further explained later.
Before outputting any useful data, each functional module 16A . . . 16G needs to be synchronised with the signal it receives. Synchronization of a functional module 16A . . . 16b means synchronization of its processing elements. The synchronization duration thus depends on the number of processing elements needed to achieve the function of the functional module 16A . . . 16G, and therefore depends on the reception quality.
In order to determine the synchronization duration of the functional modules 16A . . . 16G, the power management module 18 comprises an analyzing module 44 and a synchronization duration determination element 46.
The synchronization duration element 46 is able to provide the synchronization duration of every functional module 16A . . . 16G. The synchronization durations are referenced as SD1, SD2, SD3, SD4, SD5, SD6 and SD7.
Some synchronization durations are predetermined and stored in a database 48. They correspond to the maximum synchronization duration, i.e. to the worse possible reception.
The predetermined synchronization durations are SD1, SD2, SD3 and SD6. They preferably correspond to functional modules whose synchronization duration does not vary a lot relative to reception condition.
The other synchronization durations, namely SD4 and SD5, are adapted to the actual reception conditions.
In order to adapt synchronization durations SD4 and SD5, the analysing module 44 comprises a Doppler effect calculation element 44A and a Viterbi pseudosyndrome calculation element 44B.
The Doppler effect estimation element 44A is based on deformation measurements measured in time and frequency interpolation filters of the frequency channel estimation unit 32.
The Viterbi pseudosyndrome calculation element gives information on the quality of the bit sequence outputted by the Viterbi decoder 36. It may be designed as explained in the article “Pseudo-synchrome method for supervising Viterbi decoders at any coding rate” by C. Berron and C. Douillard, published in Electronics letters, 23rd Jun. 1994, Vol. 30, No. 13.
The synchronization duration determination element 46 is connected to the analyzing module 44 and to the database 48. The determination is achieved by comparing the calculations provided by the analysing module 44 to predetermined thresholds memorised in the database 48.
The Doppler effect calculation gives the synchronization duration SD4, while the Viterbi syndrome calculation gives the synchronization duration SD5.
Moreover, the synchronization duration determination element 46 is configured to determine the total synchronization duration SD of the entire demodulating unit 12. The total synchronization duration SD is deduced from the time length between the activation of the first processing element along the data path and the outputting of demodulated data at the output of the demodulating unit 12. The total synchronization duration SD is deduced from at least one previously received burst of data B. Preferably, it corresponds to the average of the time lengths determined for a given number of previously received bursts of data.
Consequently, the synchronization duration determination element 46 delivers estimated synchronization durations at different locations along the data path.
The processing elements 16 are adapted to be activated and deactivated separately from one another. The power management module 18 comprises an activation/deactivation module 50 adapted to activate or deactivate each processing element 16 individually, according to the synchronization durations determined by the synchronization duration determination element 46.
The activation or deactivation of a processing element relies on the control of its power supply, the processing element being active when supplied with power and inactive when not. Alternatively, it may be based on the supply of a clock signal. In this last case, the processing element is active when supplied with a clock signal and inactive when the clock signal is not supplied or is constant.
Referring now to
The DVB-H signal part carries several services noted S1 . . . S3. For example, each service corresponds to a TV channel.
The transmission is “time-sliced”. This means that each service S1 . . . S3 uses a part of the available bandwidth during a predetermined time slot. When the receiver 10 is set to receive a particular service, for example the first service S1, useful data is received as consecutive bursts of data B, each corresponding to a time slot attributed to S1. The signal between two bursts of data is called off-time signal and carries the other services data.
The data of each burst B includes the off-time duration between two bursts of data.
Referring now to
The operation is based on the fact that when a burst of data B is received, all the processing elements forming the data path must be active and synchronized. It is also based on the fact that a given processing element is able to synchronize only when the previous processing element in the data path is itself synchronized.
Consequently, when the receiver 10 is first powered-up and set to receive the first service S1, the demodulating unit 12 is entirely, or most entirely, active in order to receive and demodulate a first burst of data B. Once the burst of data is received, the receiver 10 is switch to an idle state, i.e. the demodulating unit 12 is deactivated.
The following steps are then achieved for each subsequent burst of data B.
The method comprises a step 100 of determining a time T at which a next burst of data B corresponding to the first service S1 is expected to be received by the antenna 14. This determination is achieved by using the data of the previously received burst of data B.
During a step 110, the first functional module 16A along the data path is activated, i.e. its processing elements are activated, at a time T0 corresponding to the expected reception instant less the total synchronization duration SD.
The first functional module 16A then synchronizes with the off-time signal received from the antenna 14.
During a step 130, the second functional module 14B is activated at a time T1 corresponding to the time T0 of the activation of the first functional module 16A plus the predetermined synchronization duration SD1. It then synchronizes with off-time signal received from the first functional module 16A.
Similarly, the third functional module 16C is activated at time T plus SD and SD2 during a step 140 and synchronizes.
During a step 150, the processing elements of the frequency channel estimation module 16D that must be activated are deduced from the Doppler calculation realized by the analysing module 44 on at least one previously received burst of data. Also from the Doppler calculation, the synchronisation duration SD4 is determined.
The step 150 is followed by a step 160 during which the frequency channel estimation module 16B, is activated at a time T0 plus SD1, SD2 and SD3. During a step 170 it synchronizes with the off-time signal received from the previous module 16C.
The step 170 is followed by a step 180 during which the first decoder module 16E is activated at a time corresponding to the time T0 plus the synchronization durations SD1, SD2, SD3 and SD4.
The processing elements PE that must be activated in the first decoder module 16E are deduced from the Viterbi pseudo-syndrome calculation realized by the analysing module 44 on at least one previously received burst of data. Also from the Viterbi pseudo-syndrome calculation, the synchronization duration SD5 is determined.
The step 180 is followed by a step 190 during which the first decoder module 16E synchronizes with the off-time signals received from the previous module 16D and 16C.
During a step 200, the second decoder module 16F is activated at a time corresponding to the time T0 plus the synchronization durations SD1, SD2, SD3, SD4 and SD5 of the previous modules.
The step 200 is followed by a step 240 during which the second decoder module 16F synchronizes with the off-time signal received from the first decoder module 16E.
Similarly, during steps 220 and 240, the last functional module 16G is activated at time T0 plus the synchronization durations of the previous functional modules and synchronizes with the data it receives.
The method goes on with a step 250 during which the expected burst of data B is received at reception time T. At the time of reception T, all the functional modules 16A . . . 16G are expected to be activated and synchronised so as to correctly demodulate the burst of data B.
During a step 260, the output of each functional module 16A . . . 16G is scanned by the analysis module 44 in order to determine if some of the functional modules are finished with the processing of the burst of data B. If it is the case, they are deactivated by the activation/deactivation module 50, i.e. their processing elements are deactivated. This is referenced as 270 on
Once demodulation is done, the receiver is again in an idle state and the method goes back to step 100.
Many other additional embodiments are possible. For example, the method of the invention may be executed by a processor program having a sequence of instructions stored on a processor readable medium to cause the processor to activate processing elements modules of a demodulating unit separately and dynamically based on the received signal.
This processor program can be integrated in any kind of processing unit as for example, computers, laptops, mobile phones, television decoders, television sets and the like.
| Number | Date | Country | Kind |
|---|---|---|---|
| 07290661.3 | May 2007 | EP | regional |
