Patent Application
20080037306
The foregoing and other features and advantages of the present invention will become apparent to those skilled in the art to which the present invention relates upon reading the following description with reference to the accompanying drawings, in which:
Provided is a device and method for supplying a display, such as a liquid crystal display, for example a bistable ChLCD, with drive voltages for extremely low power operation. The method enables, for example, the use of small displays operating with coin (button) batteries, including devices such as watches, calculators, etc. with the desired longer battery lifetime. Implementation of the inventive method and circuit serves to counter the quiescent current draw of the voltage conversion circuitry.
Power savings can be obtained by the controller 14 controlling the converter 12 such that the converter 12 is only on for short periods of time sufficient to supply the storage device 16 with enough energy to maintain a proper output voltage to support updating (and/or maintaining) an image provided by the display 18, even when the converter 12 is powered down. This technique can be utilized by commercially available off-the-shelf (OTS) converters that were not designed for operating in this manner, but that can provide sufficient power during power-on to both supply the display 18, and charge the storage device 16 sufficient to drive the display 18 during at least a portion of a period of converter 12 power down.
Additional embodiments might control the converter 12 in a manner other than using a controller 14, such as by using an internal controller or other switching circuit, for example, or some other method or circuit for powering the converter 12 up and down, as desired.
Scheme 40 of
In scheme 40, note that the driving phase only partially overlaps both the active and the inactive phases. Of course, different amounts of overlap can be accommodated, as desired, until, as shown in scheme 50, the driving phase 56 overlaps both the entire active phase 52, and the entire inactive phase 54. Such a scheme could be utilized where power is required to maintain an image provided by the display, or where image updates are required often (such as in a video display, for example), and thus the display requires power nearly continuously.
Scheme 60 provides phase timings and durations that allow the converter to power the display at the same time as the converter charges the storage device. Hence, driving phase 66 overlaps all of the active phase 62, and at least a portion of the inactive phase 64.
Finally, scheme 70 provides phase timings and durations that are more consistent with the example embodiments for the commercial converters discussed below. Hence, active phase 72 is very short when compared to either the driving phase 76 or the inactive phase 74 to conserve power, and the driving phase 76 is also short when compared to the inactive phase 74. Furthermore, there is a substantial portion of the inactive phase where no driving takes place (i.e., where the driving phase 76 does not overlap the inactive phase 64).
Furthermore, the driving phase 76 is typically started either once the active phase 72 has ended, or thereabouts. This is so that the storage device (which is substantially discharged at the start of the active phase, both due to prior discharge into the display and due to leakage) does not keep down the voltage provided to the display while the converter is charging the storage device, especially in the situation where capacitors are utilized as part of the storage device. As the converter charges the storage device, the available voltage rises, until it can again be used to drive the display.
Scheme 70 can be repeated cyclically, as shown in scheme 70A of
Of course, non-uniform or non-regular updates could also be supported, such as by controlling the timings and durations of the phases on a more irregular but periodic basis, or even on an as-needed basis, possibly leading to more randomly spaced and/or positioned phases than those shown in
Accordingly, a myriad of various timings and durations for the various phases are possible, and thus can be chosen for the particular application that is being utilized. The example schemes shown in
For more practical examples, existing voltage conversion circuitry, such as used in OTS devices, can be used in the manner described above to maximize the number of updates achievable with the display, such as a liquid crystal display (e.g. a ChLCD or other display) utilizing a single battery. When using a ChLCD or some other types of bistable displays, there is the advantage that no power is required to maintain a static image, and thus stored energy is only necessary during a display update, which may be only a fraction of the time a relatively static image is displayed. Accordingly, the display might need power for only a small fraction of the time that an image is displayed, and then only when the image is changed or updated.
A specific example of an OTS converter that could be utilized is the Texas Instruments TPS61041, described as a “Low Power DC/DC Boost Converter in SOT-23 Package”. Many such similar devices exist from various manufacturers, as well as similar devices based on capacitive charge pumps or inductive switching circuitry. Additionally, charge pumps are often included directly in the LCD driver IC's (for example, see the Samsung S6B0724) and E-Paper driver IC's (for example, Solomon Systech SSD1622) used to drive the displays.
One example implementation using a discrete converter focuses on using the Texas Instruments TPS61041 converter chip; however, it is appreciated that one could implement such concepts using other similar commercially provided conversion circuitry. This includes dc-to-dc conversion circuitry integrated into a display driver/controller IC, as in an example discussed in more detail below.
One primary difficulty with achieving long battery lifetimes with small display devices, such as ChLCD devices, is that the quiescent current of the voltage conversion circuitry can be relatively large. For example, the device datasheet for the TPS61041 lists a typical no-load quiescent current as 28 μA, whereas the typical shutdown current is only 0.1 μA. In an electronic watch application, for example, even if the device leaves shutdown only during the time when the display update is occurring (i.e., the display is being driven), this no-load quiescent current is too large to typically provide the desired battery lifetime.
Fortunately, monochrome operation of ChLCDs, for example, does not require precise drive voltages. This is particularly true of the direct drive segmented type displays that may be used in small, low power devices. These small devices also typically have a very low current requirement on the drive voltages. Thus, it is feasible to provide a drive voltage to the display from a storage device including, for example, a charge stored in storage capacitors, with the conversion circuitry disabled when not charging the capacitors.
In a first example implementation for driving a ChLCD device for this example embodiment, the planar drive voltages are applied to the display for 30 ms, with the focal conic drive voltages subsequently applied for the following 30 ms. Thus, the display drives for 60 ms per update, which occurs once per second for a watch operating in a time-of-day mode (with the “seconds digits” updating once every second). In this example embodiment, the dc-to-dc conversion circuitry is enabled (active phase) for significantly less time than the drive voltages are applied to the display (driving phase). In this example implementation, the active phase duration can, for the example case of a watch device, be made around 1 ms or less for each update. This duration is typically sufficient to charge up the storage device (e.g. drive voltage storage capacitors), which is sufficiently sized such that the voltage levels do not drop beyond permissible levels over the course of the update (driving phase).
Thus, for a low-powered device, such as a watch, for example, the 28 uA quiescent current draw is typically applicable for less than 1 ms out of every second. In comparison, common bistable display applications typically enable the dc-to-dc conversion circuitry for much longer durations. For a bistable display, power may only be required during display updates. Thus, it is common for the dc-to-dc conversion circuitry to be enabled for an initialization period prior to a bistable display update, and then remain enabled during the display drive period (the driving phase). In this example implementation, this would lead to the dc-to-dc conversion circuitry being enabled (active phase) for at least 60 ms out of every second. Reducing the 28 uA quiescent current draw from greater than 60 ms per second down to less than 1ms per second can result in a significant increase in battery life, for example.
Note that the very low shutdown current of 0.1 μA is applicable during the remainder of the one second period in which the dc-to-dc converter is disabled (the inactive phase). If desired, even this current may be saved by gating off power to the external dc-to-dc converter IC rather than just disabling the IC, reducing the power draw to about zero. This is shown by example in
The example implementation shown in
The microcontroller 24 communicates update data to the driver 22 through the EIO1 and LP signals, while waveform timing is controlled by the FR and DSPOF signals. These signals, as well as the EN_HV and H/L signals used to control the dc-to-dc conversion circuitry 26, are logic signals that may be implemented as general purpose I/O on any common microcontroller. An example of an acceptable controller would be the MSP 430 series from Texas Instruments.
When high, the EN_HV signal enables the TPS61041 boost converter as well as turns on transistor Q1, which enables the feedback signal used by the TPS61041 to regulate voltage. When low, the EN_HV signal puts the TPS61041 into shutdown and turns off transistor Q1 such that the voltage feedback circuit does not unnecessarily drain charge from storage capacitor C4. When enabled, the converter circuit generates 17.5V (tunable using W1) on capacitor C4, and a voltage doubler generates twice this voltage, nominally 35V, on C5.
The H/L signal is set high to turn on transistors Q3 and Q2, which provides 35V from capacitor C5 to the driver chip 22. This is used during the first 30 ms of drive in which segments of the display 20 are written to the planar (bright) ChLCD state. The H/L signal is set low during the second 30 ms drive period in which segments are written to the focal conic (dark) ChLCD state. When H/L is low, transistors Q2 and Q3 are off, and 17.5 volts is supplied to the driver chip (LCD_PWR signal) from capacitor C4 through a diode.
An alternative implementation, shown in
The microcontroller 34 resets the driver 32 using the RES signal and configures the driver's internal operation using the CS, SCLK, and SDIN signals. Display data is communicated to the driver 32 using the D1, D0, DCLK, and LP signals. These signals may be generated using the general purpose I/O available on any common microcontroller. Alternatively, SCLK and SDIN may be generated by a microcontroller SPI port.
The SSD1622 implements a charge pump using capacitors C21 through C28. The charge pump generates 17.5V on V1 (tunable using W1) and twice this voltage (nominally 35V) on V0. Capacitors C27 and C28 effectively act as the storage device.
The SSD1622 is a 3-level driver, capable of driving ground, a high level voltage (V0), and a midlevel voltage (V1) simultaneously to different pins. It is thus possible to simultaneously drive some segments to the planar state and others to the focal conic state. Thus, rather than 60 ms of drive time (30 ms of planar plus 30 ms of focal conic) every second in a watch application, the SSD1622 uses a total of 30 ms of drive time (30 ms combined planar and focal conic) every second.
The dc-to-dc converter in the SSD1622 may be enabled or disabled at any time through the configuration interface. Typically, in a watch application, a total of 4 ms of enable time is used prior to each update in order to top off the charge storage capacitors.
Variations of the above described approach are readily apparent, with the dc-to-dc conversion circuitry (and/or other driver circuitry) selectively enabled and disabled at other portions of the waveform. In the above examples, the converter is enabled for a brief period before each update. However, it is similarly possible to enable the dc/dc converter for a brief period to charge up the capacitors prior to a select set of transitions or even every transition in the drive waveforms. Alternatively, the converter could be disabled only in between waveform transitions, when the drivers are outputting constant voltages, and enabled otherwise. The method is not limited to a specific driver IC or drive waveform. One key point is that during portions of the drive waveform, the drive voltages are being supplied by storage capacitors during which the voltage conversion circuitry can be disabled (thus greatly reducing any quiescent power loss).
Other driver circuitry may be selectively enabled and disabled as well. For example, the bandgap reference in the SSD1622 is only required when the dc-to-dc converter is enabled, but it has separate control. The configuration interface may be used to turn this reference off at the same times as the dc-to-dc converter. Additionally, the SSD1622 has an internal oscillator which typically runs whenever the display is not in its low power off mode. However, the oscillator is only required when the dc-to-dc converter is running or when transitions on the driver outputs are being generated. This internal oscillator may thus be disabled during constant periods in the drive waveforms, in addition to the longer periods between display updates. Because the oscillator must run during waveform transitions, another approach is to enable the dc/dc converter during this same time in order to minimize the time which the oscillator must run.
For a ChLCD, the storage capacitors should be of sufficient capacity such that the voltage on them drops by no more than a few hundred milivolts during an update. Factors affecting the amount of voltage drop include the capacitance of the LC, the number of transitions in the drive waveforms, and leakage currents. As an alternative strategy, enabling the dc-to-dc converter at multiple points during an update could allow the use of smaller capacitors than would be possible by only enabling the dc/dc converter once per update, as discussed above. Thus, a plurality of active phases could be provided during each driving phase, if a smaller energy storage capacity is desirable.
One advantage of the described methods is that it can extend battery lifetimes for extremely low powered displays, such as ChLCDs. The method is enabled by the imprecise voltage requirement and low drive currents typically utilized for certain low-power and/or bistable displays. Furthermore, the invention can be utilized in a device and method for driving a display as disclosed in application Ser. No. 60/822,128 and incorporated herein by reference.
The invention has been described hereinabove using specific examples and embodiments; however, it will be understood by those skilled in the art that various alternatives may be used and equivalents may be substituted for elements and/or steps described herein, without deviating from the scope of the invention. Modifications may be necessary to adapt the invention to a particular situation or to particular needs without departing from the scope of the invention. It is intended that the invention not be limited to the particular implementations and embodiments described herein, but that the claims be given their broadest interpretation to cover all embodiments, literal or equivalent, disclosed or not, covered thereby.
This application claims the benefit of co-pending provisional application No. 60/822,128, filed on Aug. 11, 2006 and incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60822128 | Aug 2006 | US |
