Patent Application
20130159734
Not applicable
1. Field of Invention
This invention relates to integrated circuits, specifically to power management methods for integrated circuits.
2. Description of Prior Art
Various embodiments described herein relate to power management of an integrated circuit. Power consumption in an integrated circuit is a function of the supply voltage provided to the integrated circuit. For example, many digital logic circuits represent a binary one and a binary zero as the supply voltage and ground voltage, respectively. As digital logic evaluates during operation, signals frequently transition fully from one voltage to the other. Therefore, the power consumed in an integrated circuit is dependent on magnitude of the supply voltage relative to the ground voltage. Reducing the supply voltage generally leads to reduced power consumption, but also impacts the speed at which digital circuits operate and thus may cause malfunction of the integrated circuit.
Additionally, as transistor geometries have continued to decrease in size, manufacturing process induced statistical variations in critical dimensions, such as, for example, a gate length of metal oxide semiconductor field effect transistor (MOSFET) is playing more critical rule in performances of the integrated circuit and therefore yield of a product. A designer has to take such variation into consideration when an integrated circuit is designed. Such an approach often leads to a conservative performance specification.
It is therefore an object of the present invention to provide power management methods that utilize powers more efficiently by operating subsystems of system on chip (SOC) under minimal supply voltages that still provides satisfactory functionalities and performances.
In one embodiment, a subsystem of a SOC comprises a first programmable voltage regulator coupled to one or more performance sensors, a second programmable voltage regulator coupled to system components of the subsystem and a controller coupled to the voltage regulators and to the performance sensors. When the subsystem starts to be operational, the controller sends a signal to the regulators to generate an initial output voltage as a bias voltage for the performance sensors and for the system components.
The controller starts immediately a power (bias voltage) optimization program. The output voltage of the first voltage regulator is reduced progressively to a minimal level at which the performance sensors deliver minimal acceptable performances. The performance sensors further include performance indicators that comprise limits. The limits of the performance indicators are correlated closely to performance limits of the subsystem. The minimal output voltage of the first voltage regulator is subsequently duplicated by the second voltage regulator by the controller as the bias voltage for the system components of the subsystem.
In another embodiment, SOC comprise a centralized controller. Each of the subsystems shares the controller to optimize its power consumption.
For a more complete understanding of the present invention and its various embodiments, and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings.
The present invention will now be described in detail with references to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order not to unnecessarily obscure the present invention.
Subsystem 102 further comprises a controller 108. Controller 108 may be the same controller as the SOC′. Controller 108 may also be an independent microcontroller. Controller 108 may even be a dedicated controller for power management only. Controller 108 may comprise a special purpose processor. Controller 108 may further comprise ASIC and FPGA types of circuits. Controller 108 may comprise hardware, software and firmware. Controller 108 further comprises a control unit 116, a file storage unit 118 and a power optimization program 120. File storage unit 118 may comprise a nonvolatile semiconductor memory, such as, for example, a flash memory or a MRAM. File storage unit may further comprise a cache including a SRAM or a DRAM. Power optimization program 120 may be stored in file storage unit 118. Program 120 may be read out by control unit 116 and be executed accordingly.
Subsystem 102 further comprises a first programmable voltage regulator 110 and a second programmable voltage regulator 111. Outputs of the voltage regulators may be controlled by controller 108. In one aspect, the output of the voltage regulator may take any value in a predetermined range controller by controller 108. In another aspect, the output of the regulators may comprise a number of selectable values by controller 108. Controller 108 sends a control signal and a reference signal to set the output of the regulator. In one implementation, voltage regulator 110 and voltage regulator 111 may be identically designed and are placed in close proximity limited only by design rules of layout. Such an implementation will enable the same reference signals from controller 108 for regulator 110 and regulator 111 to generate almost identical outputs. It should be noted the minimal output voltage of regulator is typically related to a reference signal (e.g., voltage or current). Controller 108 may measure the reference signal corresponded to the minimal output voltage and record the reference signal rather than the output voltage. Controller 108 may record the reference signal directly. Controller 108 may also record the reference signal after the signal is converted to a digital signal by an analog to digital converter (not shown in
However, the present inventive concept does not limit that regulator 110 and regulator 111 are identically designed and are placed closely. In another implementation, regulator 110 and regulator 111 may be one programmable voltage regulator with two or more outputs. Controller 108 may include a means of determining the output of the voltage regulator directly by measuring the output voltage and by employing a feedback loop to sustain it.
The first voltage regulator 110 is further coupled to a performance sensor 112. Performance sensor 112 may comprise one or multiple measurement circuits that generate one or more performance indicators. The performance indicators generated by performance sensor 112 shall closely represent performances of system components 114. Performance indicators may include limits that are closely correlated to performance limits of subsystem 102. For example, performance sensor 112 may include a ring oscillator. A frequency of the ring oscillator represents speed performance of system components 114. Performance sensor 112 may also include a current sensor for measuring saturation and leakage currents of a NMOSFET and a PMOSFET. Performance sensor 112 may include measurement circuit for measuring speed performance of a critical path of a digital integrated circuit. Performance sensor 112 may be designed to demonstrate certain “look-ahead” behaviors as a performance predictor. For example, the gate lengths of MOSFET's of a speed testing circuit may be intentionally sized up by a predetermined amount (e.g., 2% up). The gate lengths of a leakage testing circuit may be intentionally sized down by another predetermined amount (e.g., 2% down). Performance sensor 112 is not a portion of system components 114 and does not provide functionalities of subsystem 102 other than as a portion of a power management module.
The first voltage regulator 110 generates an output voltage as an initial bias voltage for performance sensor 112. Controller 108 then initiates the execution of power optimization program 120. The output of 110 will reduce progressively and performance indicators of performance sensor 112 are measured accordingly. The output voltage (or the related reference signal) that corresponds to limits of the performance indicators is recorded by controller 108. One or more performance indicators may be selected, depending on an operation mode of subsystem 102. The operation mode may depend on operation frequency of subsystem 102. The operation mode may depend on functionalities that subsystem 112 is delivering. In an exemplary case, the output voltage is recorded if anyone of the selected performance indicators is reaching its limit.
In one aspect, the output voltage (or the reference signal) and its current operation mode may be recorded in a data file. The data file may be stored in file storage unit 118. In another aspect, temperature of operation of the chip may also be recorded. Controller 108 may generate output voltages for the regulators according to the data file. Controller 108 may decide if power optimization program 120 will be executed. According to one embodiment, output voltages for different operation modes and at different temperatures are determined during a functional or final testing event. The output voltages and other operational parameters are stored in the data file in file storage unit 118. Controller 108 generates output voltage for the voltage regulators according to the data file for a selected operation mode at an operating temperature.
In another aspect, a temperature sensor 122 is included in controller 108. Temperature sensor 122 may also be external to controller 108 and is coupled to controller 108. Temperature sensor 122 may even be a portion of performance sensor 112. All such variations will fall into the scope of the present invention. It should be noted that inclusion of temperature sensor 122 is optional and is not essential for operations of various embodiments and should not limit the scope of the present invention. Operating temperature of subsystem 102 is measured by temperature sensor 122 in a predetermined frequency. Controller 108 may monitor the performance indicators of performance sensor 112, the operation mode of subsystem 102 and the operating temperature closely and adjust output voltages of the voltage regulators accordingly to ensure that subsystem 102 is operated with minimal power consumption.
While the invention has been disclosed with respect to a limited number of embodiments, numerous modifications and variations will be appreciated by those skilled in the art.
Additionally, although the invention has been described particularly with respect to system on a chip (SOC), it should be understood that the inventive concepts disclosed herein are also generally applicable to other electronic systems such as electronic systems in a printed circuit board or in multiple chip modules packaged by special technologies including but not limited to a through-silicon via (TSV) technology.
Although two voltage regulators are used, it should be understood that the inventive concepts disclosed herein are also generally applicable to more or less regulator, such as, for example, a single regulator with multiple outputs may be used.
Although a single power supply is illustrated in various embodiments, it should be understood that the inventive concepts disclosed herein are also generally applicable to a power supply with more than one bias voltage.
Although the embodiments are for power reduction in a SOC, it should be understood that the inventive concepts disclosed herein are also generally applicable to optimize other performances of the system, such as, for example, speed performances of the SOC.
It is intended that all such variations and modifications fall within the scope of the following claims:
