Claims
- 1. A voltage regulator comprising:
at least one voltage converter for providing at least one output voltage; and at least one integrated circuit including at least one voltage converter controller coupled to sense the at least one output voltage and to send at least one control signal to the at least one voltage converter to control the at least one output voltage.
- 2. The voltage regulator of claim 1 wherein the voltage converter controller comprises at least one register for selecting the at least one output voltage.
- 3. The voltage regulator of claim 2 wherein the integrated circuit writes at least one value into the at least one register for selecting the at least one output voltage.
- 4. The voltage regulator of claim 1 wherein the at least one voltage converter comprises at least one transistor.
- 5. The voltage regulator of claim 4 wherein the at least one control signal controls a voltage at the base of the at least one transistor.
- 6. The voltage regulator of claim 1 wherein the at least one voltage converter comprises at least one MOSFET transistor.
- 7. The voltage regulator of claim 6 wherein the at least one control signal controls a voltage at the base of the at least one MOSFET transistor.
- 8. A network interface card comprising:
at least one voltage converter for providing at least one output voltage; and at least one network controller integrated circuit including at least one voltage converter controller coupled to sense the at least one output voltage and to send at least one control signal to the at least one voltage converter to control the at least one output voltage.
- 9. The network interface card of claim 8 wherein the voltage converter controller comprises at least one register for selecting the at least one output voltage.
- 10. The network interface card of claim 9 wherein the network controller integrated circuit further comprises at least one CPU that writes at least one value into the at least one register for selecting the at least one output voltage.
- 11. The network interface card of claim 8 wherein the at least one voltage converter comprises at least one MOSFET transistor.
- 12. The network interface card of claim 11 wherein the at least one control signal controls a voltage at the base of the at least one MOSFET transistor.
- 13. The network interface card of claim 8 wherein the network controller integrated circuit is an Ethernet controller integrated circuit.
- 14. An alert standard format compliant PCI system including at least one primary power source and at least one auxiliary power source, the system comprising:
at least one switch for selectively providing power from the at least one primary power source or the at least one auxiliary power source; at least one voltage converter connected to receive power from the at least one switch; and at least one alert sending device including at least one voltage converter controller coupled to sense the at least one output voltage and to send at least one control signal to the at least one voltage converter to control the at least one output voltage.
- 15. The alert standard format compliant PCI system of claim 14 wherein the at least one alert sending device comprises at least one network interface card.
- 16. The alert standard format compliant PCI system of claim 14 wherein the alert sending device draws less than 375 mA of current when performing alert standard format functions.
- 17. The alert standard format compliant PCI system of claim 16 further comprising at least one clock controller for reducing a speed of at least one clock signal.
- 18. A method of providing power comprising the steps of:
generating, by a voltage converter, an output voltage; sensing, by an integrated circuit, the output voltage; generating, by the integrated circuit, a control signal in accordance with the sensed output voltage; sending the control signal to the voltage converter; and controlling, by the voltage converter, the output voltage in accordance with the control signal.
- 19. The method of claim 18 wherein the step of generating a control signal further includes the step of writing a value in a register in the integrated circuit to select a value for the output voltage.
- 20. The method of claim 18 wherein the voltage converter comprises a MOSFET transistor.
- 21. The method of claim 20 wherein the controlling step includes the step of applying a voltage at the base of the at least one MOSFET transistor.
- 22. An alert sending device, connected to be powered by at least one primary power source or an auxiliary power source, the alert sending device comprising:
at least one alert standard format controller for performing alert standard format functions; and at least one power controller for controlling power consumption of the alert sending device when the alert sending device is powered by the auxiliary power source.
- 23. The alert sending device of claim 22 wherein the alert sending device draws less than 375 mA of current when performing alert standard format functions.
- 24. The alert sending device of claim 22 further comprising at least one sensor for providing a signal to the at least one power controller, the signal indicative of whether the alert sensing device is powered by the auxiliary power source.
- 25. The alert sending device of claim 22 wherein the power controller comprises at least one clock controller for setting a frequency of at least one clock signal when the alert sending device is powered by the auxiliary power source.
- 26. The alert sending device of claim 22 wherein the at least one clock signal comprises a CPU clock.
- 27. The alert sending device of claim 22 further comprising at least one input-output pad for driving at least one clock signal to a steady state when the at least one primary power source is off.
- 28. The alert sending device of claim 22 wherein a first one of the at least one primary power source powers at least one input-output pad for a PCI bus and the auxiliary power source powers at least one input-output pad for another bus.
- 29. The alert sending device of claim 22 comprising at least one network controller integrated circuit.
- 30. The alert sending device of claim 22 comprising at least one network interface card.
- 31. The alert sending device of claim 22 wherein the at least one power controller disables at least one of a DMA engine and a PCI interface component.
- 32. The alert sending device of claim 22 wherein the at least one power controller provides auxiliary power to at least one of an internal CPU, a CPU memory, a packet buffer memory, a physical interface and media access controller.
- 33. An Ethernet network controller, connected to at least one PCI bus primary power source and a PCI bus auxiliary power source, for performing alert standard format functions when the Ethernet network controller is powered by the auxiliary power source, the Ethernet network controller comprising:
at least one interface for an Ethernet network; at least one interface for an SMBus; at least one interface for a PCI bus; at least one embedded processor for performing alert standard format functions via the at least one Ethernet interface and the at least one SMBbus interface; and at least one clock controller for setting a frequency of at least one clock signal when the Ethernet network controller is powered by the auxiliary power source.
- 34. The Ethernet network controller of claim 33 wherein the Ethernet network controller draws less than 375 mA of current when performing alert standard format functions.
- 35. The Ethernet network controller of claim 33 further comprising at least one sensor for providing a signal to the at least one processor, the signal indicative of whether the Ethernet network controller is powered by the auxiliary power source.
- 36. The Ethernet network controller of claim 33 wherein the at least one clock controller generates a signal to change a data rate supported by the at least one Ethernet interface.
- 37. The Ethernet network controller of claim 33 further comprising at least one input-output pad for driving at least one PCI bus clock signal to a steady state when the at least one PCI bus power source is off.
- 38. The Ethernet network controller of claim 33 wherein the at least one primary power source powers at least one input-output pad for a PCI bus and the auxiliary power source powers at least one input-output pad for at least one of the SMBus and the PCI bus.
- 39. The network controller of claim 33 comprising at least one Ethernet network interface card.
- 40. The network controller of claim 33 wherein the at least one clock signal comprises a CPU clock.
- 41. The network controller of claim 33 further comprising at least one power controller for disabling at least one of a DMA engine and a component of the PCI interface.
- 42. The network controller of claim 33 further comprising at least one power controller for providing auxiliary power to at least one of an internal CPU, a CPU memory, a packet buffer memory, a physical interface and a media access controller.
- 43. A method of providing alert standard format functions when powered by an auxiliary power source, comprising the steps of:
performing, by an alert sending device, alert standard format functions; and controlling power consumption of the alert sending device when the alert sending device is powered by the auxiliary power source.
- 44. The method of claim 43 wherein the controlling step includes the step of maintaining a current draw of less than 375 mA.
- 45. The method of claim 43 further comprising the step of sensing whether the alert sending device is powered by the auxiliary power source.
- 46. The method of claim 43 further comprising the step of setting a frequency of at least one clock signal when the alert sending device is powered by the auxiliary power source.
- 47. The method of claim 43 further comprising the step of reducing a frequency of at least one clock signal when the alert sending device is powered by the auxiliary power source.
- 48. The method of claim 47 wherein the at least one clock signal comprises a CPU clock.
- 49. The method of claim 43 further comprising the step of driving at least one clock signal to a steady state when a primary power source is off.
- 50. The method of claim 43 wherein the controlling step includes disabling at least one of a DMA engine and a PCI interface component.
- 51. The method of claim 43 wherein the controlling step includes enabling at least one of an internal CPU, a CPU memory, a packet buffer memory, a physical interface and a media access controller.
- 52. The method of claim 43 wherein the controlling step includes providing auxiliary power to at least one of an internal CPU, a CPU memory, a packet buffer memory, a physical interface and a media access controller.
- 53. An alert sending device, connected to at least one primary power source and an auxiliary power source, the alert sending device comprising:
at least one data memory powered by the auxiliary power source; and at least one processor for initiating alert standard format functions when powered by the auxiliary power source by accessing alert standard format code stored in the at least one data memory.
- 54. The alert sending device of claim 53 wherein the alert sending device draws less than 375 mA of current when performing alert standard format functions.
- 55. The alert sending device of claim 53 wherein the at least one data memory stores boot code for execution by the at least one processor to initiate the alert standard format functions.
- 56. The alert sending device of claim 53 wherein the at least one processor, upon execution of the boot code, transfers the alert standard format code to another one of the at least one data memory for execution by the at least one processor.
- 57. The alert sending device of claim 53 further comprising at least one sensor for providing a signal to the at least one processor, the signal indicative of whether the alert sending device is powered by the auxiliary power source.
- 58. The alert sending device of claim 53 comprising at least one network controller integrated circuit.
- 59. The alert sending device of claim 53 comprising at least one network interface card.
- 60. A network controller, connected to at least one PCI bus primary power source and a PCI bus auxiliary power source, for performing alert standard format functions when powered by the auxiliary power source, the network controller comprising:
at least one nonvolatile memory, powered by the auxiliary power source, for storing alert standard format code; and at least one network controller integrated circuit comprising:
at least one nonvolatile memory, powered by the auxiliary power source, for storing boot code; at least one data memory, powered by the auxiliary power source, for storing code for execution by at least one processor; and at least one processor, powered by the auxiliary power source, for performing alert standard format functions, wherein a boot operation for the at least one processor comprises:
executing the boot code; transferring the alert standard format code from the at least one nonvolatile memory to the at least one data memory; and executing the alert standard format code from the at least one data memory.
- 61. The network controller of claim 60 wherein the alert sending device draws less than 375 mA of current when performing alert standard format functions.
- 62. The network controller of claim 61 further comprising at least one sensor for providing a signal to the at least one processor, the signal indicative of whether the network controller is powered by the auxiliary power source.
- 63. The network controller of claim 60 wherein the at least one nonvolatile memory for storing alert standard format code comprises at least one SEEPROM.
- 64. The network controller of claim 60 comprising at least one network interface card.
- 65. A method for booting an alert sending device when powered by an auxiliary power source, comprising the steps of:
powering at least one data memory with an auxiliary power source; storing alert standard format code in the at least one data memory; retrieving the alert standard format code stored in the at least one data memory; and booting from the retrieved alert standard format code.
- 66. The method of claim 65 wherein the alert sending device draws a current of less than 375 mA.
- 67. The method of claim 65 further comprising the step of sensing whether the alert sending device is powered by the auxiliary power source.
- 68. The method of claim 65 further comprising the step of storing the retrieved alert standard format code in at least one scratch pad data memory powered by the auxiliary power source.
- 69. A method for booting a network controller powered by an auxiliary power source to perform alert standard format functions, comprising the steps of:
storing alert standard format code in at least one nonvolatile memory powered by the auxiliary power source; storing boot code in at least one nonvolatile memory powered by the auxiliary power source; executing the boot code; transferring the alert standard format code from the at least one nonvolatile memory to at least one data memory powered by the auxiliary power source; and executing the alert standard format code from the at least one data memory.
- 70. The method of claim 69 wherein the network controller draws a current of less than 375 mA.1.
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] The present application claims priority on the basis of the following United States Provisional Patent Application, the entire contents of which is herein incorporated by reference as though set forth in full: Serial No. 60/286,320, filed Apr. 24, 2001, and entitled “INTEGRATED GIGABIT ETHERNET PCI-X CONTROLLER.” The present application also is related to co-pending U.S. patent application Ser. No. 09/865,844, filed May 25, 2001, and entitled “MULTIPROTOCOL COMPUTER BUS INTERFACE ADAPTER AND METHOD,” the entire contents of which is incorporated herein by reference as though set forth in full. The present application also is related to co-pending United States Patent Application entitled “ALERTING SYSTEM, ARCHITECTURE AND CIRCUITRY,” with named inventors Steven B. Lindsay, Andrew SeungHo Hwang and Andrew M. Naylor filed on Apr. 24, 2002, the entire contents of which is incorporated herein by reference as though set forth in full. The present application also is related to co-pending United States Patent Application entitled “ASF MEMORY LOADING AND HANDLING SYSTEM,” with named inventors Steven B. Lindsay, Andrew SeungHo Hwang and Andrew M. Naylor filed on Apr. 24, 2002, the entire contents of which is incorporated herein by reference as though set forth in full. The present application also is related to co-pending United States Patent Application entitled “INTEGRATED GIGABIT ETHERNET PCI-X CONTROLLER,” with named inventors Steven B. Lindsay, Andrew SeungHo Hwang, Andrew M. Naylor, Michael Asker, Jennifer Chaio, Myles Wakayama and Gary Alvstad filed on Apr. 24, 2002, the entire contents of which is incorporated herein by reference as though set forth in full.
Provisional Applications (1)
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Number |
Date |
Country |
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60286320 |
Apr 2001 |
US |