Patent Application
20050138441
The inventions generally relate to power management without interrupt latency.
Serial ATA is a storage interface technology designed with power issues in mind. Serial ATA is often used as a mobile interface technology, but is not limited to mobile systems. A Serial ATA link can be placed in two low power modes, referred to as “partial” and “slumber”. These low power modes may be entered between commands or even while commands are outstanding in order to save power. The resume time from the partial power managed state is 10 microseconds and the resume time from the slumber power managed state is 10 milliseconds. This allows a system designer to choose a state that balances their power management versus performance needs for a system being designed. Serial ATA also defines registers by which software can explicitly request that the link enter the partial mode or the slumber mode.
The time between a ceasing of communication for a command on a communication link using serial ATA and when software services the corresponding interrupt can be long, and valuable power can be wasted during this interval.
Interrupt latencies on many operating systems (for example, Microsoft operating systems) are extremely variable depending on the load of the system, and can be milliseconds in length. Software cannot place the serial ATA link in a low power managed state until the interrupt service routine is entered. It would be advantageous to have a link (for example, a serial ATA link) be placed in a low power managed state in a faster manner (for example, without any interrupt latency).
The inventions will be understood more fully from the detailed description given below and from the accompanying drawings of some embodiments of the inventions which, however, should not be taken to limit the inventions to the specific embodiments described, but are for explanation and understanding only.
Some embodiments of the inventions relate to power management without interrupt latency.
In some embodiments, a register is used to store one or more bits indicating whether a low power mode is to be entered. A controller is to put at least one link in a low power state in response to the one or more bits indicating whether a low power mode is to be entered without waiting for a software interrupt routine when a particular condition is encountered. In some embodiments the condition could be that there are no commands outstanding and no commands to issue (or that the link is idle).
In some embodiments a system includes a host, a host bus adapter (HBA) coupled to the host, at least one device, each of the devices having a corresponding link to couple that device to the host bus adapter, a register to store one or more bits indicating whether a low power mode is to be entered, and a controller to put at least one of the links in a low power state in response to the one or more bits indicating whether a low power mode is to be entered without waiting for a software interrupt routine when a particular condition occurs.
In some embodiments it is determined (for example, by a host bus adapter) whether there are no commands outstanding and no commands to issue on at least one link (the link is idle), and at least one of the links is put in a low power mode without waiting for a software interrupt routine when there are no outstanding commands or commands to issue on link (or links).
In some embodiments the host bus adapter 104 is allowed to enter a power managed state automatically when there are no commands outstanding. A storage driver can specify via a host controller interface whether a power managed state should be entered automatically, and if so, it can specify which power managed state to enter. Additionally, in some embodiments, the storage driver can specify the power managed state on a per device basis (for example, in a system using point-to-point link technology such as Serial ATA and/or Serial Attached SCSI). In some embodiments a link (for example, a Serial ATA link) can be placed immediately into a low power state without waiting for any interrupt latency overhead.
In some embodiments the LPS bit or bits 202 identify two or more low power link states (for example, two states of “partial” and “slumber”, three states, or four states, etc.) In some embodiments the LPM bit or bits 204 identify an input as to whether or not a low power state should be entered by a link in certain circumstances. The LPM bit or bits may be input by a user through software, in response to a selection by software such as whether the system is being run on AC power or a battery, a hardware jumper, or some other means of inputting.
In some embodiments the low power link mode (LPM) bit or bits 204 is one bit. If the LPM bit is, for example, set to “1”, then the host bus adapter (for example, host bus adapter 104 of
In some embodiments the low power link state (LPS) bit or bits 202 is one bit. If the LPS bit is, for example, set to “1”, the host bus adapter will enter a slumber mode (for example, a low power slumber mode such as a Serial ATA slumber mode) when there are no commands outstanding and the LPM bit is set, for example, to “1”. If the LPS bit is, for example, cleared to “0”, then the host bus adapter will enter a partial mode (for example, a low power partial mode such as a Serial ATA partial mode) when there are no commands outstanding and the LPM bit is set, for example, to “1”.
In some embodiments the LPM bit 204 is set to “1” if the system is connected to battery power and is cleared to “0” if the system is connected to AC power such that the HBA enters a low power link state when there are no commands outstanding and no commands to issue, and the system is connected to battery power. In some embodiments operations performed on the LPS bit or bits 202 and on the LPM bit or bits 204 such as those described herein are implemented by a controller (for example, a hardware controller) that is coupled to the register 200. In some embodiments the controller is in a host bust adapter such as host bus adapter 104 of
In some embodiments the HBA will automatically enter the low power link states as described in some embodiments described above for all links to the HBA. In some embodiments the HBA will automatically enter the low power link states as described in some embodiments described above on a link-by-link basis. For example, in some embodiments the configuration can be managed on a per device basis automatically (for example, in a mobile system or any other type of system). If the system was set for higher performance, for example, a disk drive device could be set up in a “partial” mode while lower performing devices (for example, a CD device such as a CD-ROM or a DVD device such as a DVD-ROM) could be placed in “slumber” since the slower performance of the lower performing devices could not be discerned. In some embodiment each type of device that is in the system or could possibly be in the system could have a specially designed mode specially suited for that device (for example, a special mode for each of a tape device, a hard disk drive device, a CD device, etc.)
In some embodiments the flow 300 illustrated in and described in reference to
In some embodiments the amount of power saved by a link is not solely determined by having a good driver. Setting the bits (for example, the LPS and LPM bits) to control the HBA operation according to some embodiments is a trivial matter. Having software manage the low power states, on the other hand, adds software overhead, makes things more difficult to manage, and incurs latency penalties related to when the software can actually enter the low power modes and/or low power states. Many currently available drivers are poorly written and may not put the link in a low power mode (or to sleep) immediately. Alternatively, some drivers may choose not to put the link in a low power mode (or to sleep) at all (for example, because it is “extra code”). However, in some embodiments the driver only needs to set up the host bus adapter in the appropriate configuration by setting two bits (or two sets of bits LPM and LPS). After that point the HBA will automatically put the link in a low power mode (or to sleep) and automatically bring the link out of the low power state when there are no commands to issue.
Pseudo-code for a driver initialization according to some embodiments is as follows:
In some embodiments power savings may be implemented in any system. In some embodiments power savings may be implemented in any mobile system. In some embodiments battery life may be extended in a system using extra power savings (for example, in a mobile system).
In some embodiments an overhead incurred while waiting for software to initiate a lower power mode for a link may be eliminated. In some embodiments an overhead incurred while waiting for software to initiate a lower power mode for a link may be eliminated while still maintaining software control over what low power states may be entered in order to satisfy performance vs. power considerations.
Although most of the embodiments described above have been described in reference to particular implementations such as the invention being described in several places as having two low power link states (for example, “slumber” and “partial states), other implementations are possible according to some embodiments.
For example, the implementations described herein may be used to implement more than two low power link states or only one low power link state according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.
Although flow diagrams and/or state diagrams may have been used herein to describe embodiments, the inventions are not limited to those diagrams or to corresponding descriptions herein. For example, flow need not move through each illustrated box or state, or in exactly the same order as illustrated and described herein.
The inventions are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present inventions. Accordingly, it is the following claims including any amendments thereto that define the scope of the inventions.
