Power-on reset signal generation circuit and method

Abstract

A power-on reset (POR) circuit (200) can include a voltage divider section (202) having a first divider resistor (R21), a second divider resistor (R22), and a diode connected transistor (N22). Signal generator section (204) can include a transistor N21 that is activated according to a potential generated by voltage divider section (202). A trip point of a POR circuit (200) can be based on a difference between the threshold voltages of transistors N21 and N22, and thus less susceptible to variations in threshold voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block schematic diagram of a power-on reset (POR) circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a POR circuit according to a second embodiment of the present invention.

FIG. 3 is a schematic diagram of a conventional POR circuit.

Claims

1. A circuit, comprising: a first transistor with a first threshold voltage having a gate coupled to a trip node and a source-drain path coupled between a first power supply node and a reset node that provides a reset signal;a first trip impedance device coupled to the trip node; anda second transistor with a second threshold voltage less than the first threshold voltage having a source-drain path coupled between the first impedance device and the first power supply node.

2. The circuit of claim 1, wherein: the first transistor and second transistor are insulated gate field effect transistors of a first conductivity type.

3. The circuit of claim 2, wherein: the first conductivity type is n-channel.

4. The circuit of claim 1, wherein: the first trip impedance device comprises a resistor.

5. The circuit of claim 1, wherein: the second transistor has a gate coupled to its drain.

6. The circuit of claim 1, further including: a second trip impedance device coupled between the trip node and a second power supply node.

7. The circuit of claim 6, wherein: the second trip impedance device comprises a resistor.

8. The circuit of claim 6, wherein: the second trip impedance device has a resistance that matches the first trip impedance device.

9. The circuit of claim 1, further including: a bias impedance device coupled between the reset node and a second power supply node.

10. The circuit of claim 9, wherein: the bias impedance device comprises a resistor.

11. The circuit of claim 1, wherein: the second threshold voltage has an absolute value less than an absolute value of the first threshold voltage.

12. A method of generating a reset signal, comprising the steps of: providing a resistance voltage divider circuit coupled to a power supply node to generate a trip potential at a trip node;activating an insulated gate field effect transistor (IGFET) in response to the trip potential; andintroducing an IGFET threshold voltage drop into the voltage divider circuit.

13. The method of claim 12, wherein: providing the resistance voltage divider circuit includes connecting at least two resistances in series at the trip node.

14. The method of claim 13, wherein: the at least resistances having essentially the same resistance.

15. The method of claim 12, wherein: activating the insulated gate field effect transistor in response to the trip potential includes coupling a gate of a trip transistor to the trip node.

16. The method of claim 12, wherein: introducing the IGFET threshold voltage drop into the voltage divider circuit includes connecting a transistor in a diode configuration in series with resistors of the voltage divider circuit.

17. The method of claim 12, wherein: introducing an IGFET threshold voltage drop into the voltage divider circuit includes introducing a threshold voltage drop less than that of the activated IGFET.

18. A power-on reset signal generating circuit, comprising: a threshold adjusted voltage divider circuit coupled between a first power supply node and second power supply node that includes at least two resistors and at least one diode connected transistor arranged in series with one another; anda reset signal generator comprising at least one transistor having a gate coupled to the threshold adjusted voltage divider circuit that generates a reset signal at its drain.

19. The power-on reset signal generating circuit of claim 18, wherein: the threshold adjust voltage divider circuit includes a diode connected first transistor having a source coupled to the first power supply node,a first divider resistor coupled between the drain of the first transistor and a trip node, anda second divider resistor coupled between the trip node and the second power supply node.

20. The method of claim 19, wherein: a reset signal generator includes a reset transistor having a source coupled to the first power supply node and a gate coupled to the trip node, the reset transistor having a larger magnitude threshold voltage than a threshold voltage of the first transistor, anda bias impedance coupled between the drain of the reset transistor and the second power supply node.