Patent Application
20160170474
The present invention relates to a technology that enhances a power-saving effect in a server equipped with a non-volatile memory.
In recent years, practical application of a universal memory, such as a non-volatile memory integrating a DRAM (Dynamic Random Access Memory) work memory and a NAND storage memory, is becoming widespread. Consequently, research on practical application of a power-saving computer called normally-off computing has been started. In normally-off computing, power supply to components other than components that should actually operate is actively shut off even when an entire system is in operation, by enabling a file on a storage to be directly executed on a non-volatile memory without being loaded into a memory.
A target of such research is to enhance a power-saving effect by making a power-OFF period of a CPU (Central Processing Unit) and a memory as long as possible. Technologies currently under research mainly focus on a hardware layer and an OS (Operating System) layer.
For example, NPL 1 describes a computing technology that realizes normally-off in which power supply to components other than components that should actually operate is actively shut off, even when an entire system is in operation.
According to NPL 1, increase in power consumption due to power-OFF/ON of a CPU circuit and a memory, and power saving due to reduction of leakage current during a power-OFF period offset each other. Therefore, in order to enhance a power-saving effect, it is required to reduce as much power-OFF/ON frequency as possible to extend a continuous power-OFF period. However, there is a limit in extending a continuous power-OFF period by solely relying on skilled power control in hardware and OS layers.
Further, PTL 1 discloses, although being not normally-off computing, a technology that reduces unnecessary power consumption in a multi-core processor system. The technology is a task scheduling device including a scheduler that, when detecting presence of a processor in an idle state, shuts off power supply to such a processor. However, the task scheduling device measures a workload of each task prior to task processing. Furthermore, the device predicts usage ratios of a plurality of processors in accordance with the measured workloads. Therefore, the technology is accompanied by the complicated processes and is not suitable for normally-off computing that demands instantaneous power-OFF/ON.
Further, PTL 2, PTL 3, PTL 4, and PTL 5 are disclosed as related technologies.
The present invention is made in view of the aforementioned problem and an object of the invention is to realize normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
A power-saving control system according to the present invention includes a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system that operates on the physical machine, and one or more processes that operate on the operating system, wherein the operating system includes a process characteristic collection unit that collects a characteristic of the process, a core allocation determination unit that determines allocation of the CPU core to the process, in accordance with the characteristic of the process, and a process scheduler that executes the process, in accordance with the allocation, and powers OFF/ON the CPU core or the memory, in accordance with execution of the process.
A power-saving control device according to the present invention includes a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system unit that operates on the physical machine, and one or more process units operated by the operating system unit, wherein the operating system unit includes a process characteristic collection unit that collects a characteristic of the process unit, a core allocation determination unit that determines allocation of the CPU core to the process unit, in accordance with the characteristic of the process unit, and a process scheduler that executes the process unit, in accordance with the allocation, and powers OFF/ON the CPU core or the memory, in accordance with execution of the process unit.
A power-saving control method according to the present invention is a power-saving control method of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the operating system collects a characteristic of the process, determines allocation of the CPU core to the process, in accordance with the characteristic of the process, executes the process, in accordance with the allocation, and powers OFF/ON the CPU core or the memory, in accordance with execution of the process.
A power-saving control program according to the present invention is a power-saving control program of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the program causes the operating system to execute processing of collecting a characteristic of the process, processing of determining allocation of the CPU core to the process, in accordance with the characteristic of the process, processing of executing the process, in accordance with the allocation, and processing of powering OFF/ON the CPU core or the memory, in accordance with execution of the process.
A power-saving control system according to the present invention includes a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system that operates on the physical machine, and one or more processes that operate on the operating system, wherein the operating system includes a process characteristic collection unit that collects a load characteristic of the process or an interrupt characteristic of the process, an interrupt coalescing unit that coalesces interrupts to the process, in accordance with the load characteristic or the interrupt characteristic, and a process scheduler that executes interrupts in accordance with coalescing of the interrupts, and powers OFF/ON the CPU core or the memory in accordance with execution of the interrupt.
A power-saving control device according to the present invention includes a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system unit that operates on the physical machine, and one or more process units that operate on the operating system, wherein the operating system unit includes a process characteristic collection unit that collects a load characteristic of the process unit or an interrupt characteristic of the process unit, an interrupt coalescing unit that coalesces interrupts to the process unit, in accordance with the load characteristic or the interrupt characteristic, and a process scheduler that executes interrupts, in accordance with coalescing of the interrupts, and powers OFF/ON the CPU core or the memory, in accordance with execution of the interrupt.
A power-saving control method according to the present invention is a power-saving control method of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the operating system collects a load characteristic of the process or an interrupt characteristic of the process, coalesces interrupts to the process, in accordance with the load characteristic or the interrupt characteristic, executes interrupts, in accordance with coalescing of the interrupts, and powers OFF/ON the CPU core or the memory, in accordance with execution of the interrupt.
A power-saving control program according to the present invention is a power-saving control program of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the program causes the operating system to execute processing of collecting a load characteristic of the process or an interrupt characteristic of the process, processing of coalescing interrupts to the process, in accordance with the load characteristic or the interrupt characteristic, processing of executing an interrupt, in accordance with coalescing of the interrupts, and processing of powering OFF/ON the CPU core or the memory, in accordance with execution of the interrupt.
A power-saving control system according to the present invention includes a physical machine that includes a CPU and a memory, an operating system that operates on the physical machine, and one or more processes that operate on the operating system, wherein the operating system includes a process scheduler that performs scheduling of the process, and a memory power control unit that powers ON/OFF the memory, in accordance with the scheduling.
A power-saving control device according to the present invention includes a physical machine that includes a CPU and a memory, an operating system unit that operates on the physical machine, and one or more process units operated by the operating system unit, wherein the operating system unit includes a process scheduler that performs scheduling of the process unit, and a memory power control unit that powers ON/OFF the memory, in accordance with the scheduling.
A power-saving control method according to the present invention is a power-saving control method of a power-saving control system that includes a physical machine including a CPU and a memory, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the operating system performs scheduling of the process and powers ON/OFF the memory, in accordance with the scheduling.
A power-saving control program according to the present invention is a power-saving control program of a power-saving control system that includes a physical machine including a CPU and a memory, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the program causes the operating system to execute processing of scheduling the process, and processing of powering ON/OFF the memory, in accordance with the scheduling.
The present invention is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Exemplary embodiments of the present invention will be described in detail below with reference to the drawings. Although technically preferred limitations for implementing the present invention are applied to the exemplary embodiments described below, the scope of the invention is not limited thereto.
The present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
The CPU 11 includes a plurality of CPU cores 18 and has a function called power gating capable of shutting off power to part of a CPU circuit at any timing, in addition to ordinary CPU processing. The present exemplary embodiment provides power shut-off/resumption control on a per CPU core 18 basis.
The I/O device 12 includes an interface for data exchange with various devices such as a network.
The memory unit 13 includes the memory 19 capable of operating in response to an operation of each CPU core 18. The memory 19 may be a non-volatile memory and power to an unused memory 19 can be shut off. In that case, stored data are not erased and the data can be read after power is resumed.
The memory unit 13 may also be a memory including one or more memory areas. In this case, a memory area corresponds to the memory 19.
As a non-volatile memory, an ReRAM (Resistive RAM), an MRAM (Magnetoresistive RAM), an STT-MRAM (Spin Transfer Torque-MRAM), a PRAM (Phase change RAM), and an FeRAM (Ferroelectric RAM) may be used. Further, any non-volatile memory may be used without limiting to the memories described above.
The OS 14 includes the process characteristic collection unit 141, the core allocation determination unit 142, and the process scheduler 143, and performs process execution control for an enhanced power-saving effect, by shutting off power to the CPU core 18 in the CPU 11 and the memory 19 in the memory unit 13.
The process characteristic collection unit 141 collects information about the processes 151 to 15n, including a load characteristic such as a CPU utilization rate, a cache hit rate, and context switching frequency, and a resource utilization characteristic such as incoming/outgoing network traffic.
The core allocation determination unit 142 determines allocation of which process is to be executed by which CPU core 18, in accordance with the load characteristics and the resource utilization characteristics of the processes 151 to 15n, collected by the process characteristic collection unit 141. The core allocation determination unit 142 monitors a load and resource usage frequency of each process, assembles processes with a low load and low resource usage frequency, and allocates the processes to a same CPU core 18. Similarly, the core allocation determination unit 142 assembles processes with a high load and high resource usage frequency and allocates the processes to a same CPU core 18. In this case, in order to avoid degradation of a processing capability of the CPU core 18, assembling and allocation are performed within an upper limit of the CPU core 18 and the resource. Thus, in a CPU core 18 where low-load processes are assembled, downtime caused by power gating of the CPU can be extended.
The process scheduler 143 performs scheduling of process execution, in accordance with determination made by the core allocation determination unit 142.
The process characteristic collection unit 141 collects load characteristics and resource utilization characteristics of the processes 151 to 15n operating on the physical machine 1 (Step A1).
Next, the core allocation determination unit 142 determines allocation of which process is to be executed by which CPU core 18, in accordance with the process characteristics collected by the process characteristic collection unit 141 (Step A2).
A CPU utilization rate of each process is used as a criterion here, and processes are allocated to the CPU core 18 in descending order of CPU utilization rates, within a range not exceeding an upper limit of the CPU utilization rate. Therefore, an algorithm such as the best-fit algorithm in the bin packing problem may be used without limiting to a specific algorithm. Thus, in a CPU core 18 where low-load processes are assembled, downtime caused by power gating of the CPU 11 can be extended.
Further, determination and allocation can be made by use of an instantaneous value of a CPU utilization rate, without performing processing time measurement or workload prediction of each process. Thus, instantaneous power-OFF/ON corresponding to normally-off computing can be provided without performing a complicated process.
Next, in accordance with association between each process and a CPU core 18 determined by the core allocation determination unit 142, the process scheduler 143 controls execution of processes (Step A3).
At this time, power-OFF/ON of a CPU core 18 and a memory 19 working with the CPU core 18 is automatically controlled by the power gating function of the CPU 11. In other words, even when an entire system is in operation, components other than components such as a CPU core 18 and a memory 19 that should actually operate at the moment can be powered OFF, and components such as a CPU core 18 and a memory 19 that should actually operate can be powered ON.
Further, since the memory unit 13 uses a non-volatile memory 19, there is no need for saving data stored in the memory 19 into another memory, or restoring data saved in another memory to the memory 19, when powering OFF/ON the memory 19. Therefore, smooth normally-off computing with suppressed delay is provided.
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 1 in
The present exemplary embodiment provides extended idle time for a CPU core allocated with a process with a low CPU utilization rate, and therefore long and continuous downtime of the CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
As illustrated in
Next, a core allocation determination unit 162 determines allocation of which VM is to be executed by which CPU core 18, in accordance with the VM characteristics collected by the VM characteristic collection unit 161 (Step B2).
A CPU utilization rate of each VM is used as a criterion here, and VMs are allocated to a few CPU cores 18 in descending order of CPU utilization rates, within a range not exceeding an upper limit of the CPU utilization rate. Therefore, an algorithm such as the best-fit algorithm in the bin packing problem may be used without limiting to a specific algorithm. Thus, in a CPU core 18 where low-load VMs are assembled, downtime caused by power gating of the CPU can be extended.
Further, determination and allocation can be made by use of an instantaneous value of a CPU utilization rate, without performing processing time measurement or workload prediction of each process. Thus, instantaneous power-OFF/ON corresponding to normally-off computing can be provided without performing a complicated process.
Next, in accordance with association between each VM and a CPU core determined by the core allocation determination unit 162, the VM scheduler 163 controls execution of VMs (Step B3).
At this time, power-OFF/ON of a CPU core 18 and a memory 19 is automatically controlled by the power gating function of the CPU 11. In other words, even when an entire system is in operation, components other than components such as a CPU core 18 and a memory 19 that should actually operate at the moment can be powered OFF, and components such as a CPU core 18 and a memory 19 that should actually operate can be powered ON.
Further, since the memory unit 13 uses a non-volatile memory 19, there is no need for saving data stored in the memory 19 into another memory, or restoring data saved in another memory to the memory 19, when powering OFF/ON the memory 19. Therefore, smooth normally-off computing with suppressed delay is provided.
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 2 in
The present exemplary embodiment provides extended idle time for a CPU core allocated with a VM with a low CPU utilization rate, and therefore long and continuous downtime of the CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a fourth exemplary embodiment of the present invention will be described. The fourth exemplary embodiment of the present invention has a configuration of the physical machine 1 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step A1 in
In Step A2 in
Step A3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 1 in
The present exemplary embodiment provides a similar amount of idle time for each CPU core, and therefore downtime of a CPU core and a memory working therewith due to power shut-off can be evenly secured from all CPU cores. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a fifth exemplary embodiment of the present invention will be described. The fifth exemplary embodiment of the present invention has a configuration of the physical machine 2 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step B1 in
In Step B2 in
Step B3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 2 in
The present exemplary embodiment provides a similar amount of idle time for each CPU core, and therefore downtime of a CPU core and a memory working therewith due to power shut-off can be evenly secured from all CPU cores. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a sixth exemplary embodiment of the present invention will be described. The sixth exemplary embodiment of the present invention has a configuration of the physical machine 1 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step A1 in
In Step A2 in
Step A3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 1 in
The present exemplary embodiment provides extended idle time for a CPU core allocated with a process with low context switching frequency, and therefore long and continuous downtime of the CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a seventh exemplary embodiment of the present invention will be described. The seventh exemplary embodiment of the present invention has a configuration of the physical machine 2 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step B1 in
In Step B2 in
Step B3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 2 in
The present exemplary embodiment provides extended idle time for a CPU core allocated with a VM with low context switching frequency, and therefore long and continuous downtime of the CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, an eighth exemplary embodiment of the present invention will be described. The eighth exemplary embodiment of the present invention has a configuration of the physical machine 1 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step A1 in
In Step A2 in
Step A3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 1 in
The present exemplary embodiment provides a similar amount of idle time for each CPU core, and therefore downtime of a CPU core and a memory working therewith due to power shut-off can be evenly secured from all CPU cores. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a ninth exemplary embodiment of the present invention will be described in detail. The ninth exemplary embodiment of the present invention has a configuration of the physical machine 2 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step B1 in
In Step B2 in
Step B3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 2 in
The present exemplary embodiment provides a similar amount of idle time for each CPU core, and therefore downtime of a CPU core and a memory working therewith due to power shut-off can be evenly secured from all CPU cores. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
The CPU 11 includes a plurality of CPU cores 18 and has a function called power gating capable of shutting off power to part of the CPU circuit at any timing, in addition to ordinary CPU processing. The present exemplary embodiment provides power shut-off/resumption control on a per CPU core 18 basis.
The I/O device 12 includes an interface for data exchange with various devices such as a network.
The memory unit 13 includes the memory 19 capable of operating in response to an operation of each CPU core 18. The memory 19 may be a non-volatile memory and power to an unused memory 19 can be shut off. In that case, stored data are not erased and the data can be read after power is resumed.
The memory unit 13 may also be a memory including one or more memory areas. In this case, a memory area corresponds to the memory 19.
As a non-volatile memory, an ReRAM, an MRAM, an STT-MRAM, a PRAM, and an FeRAM may be used. Further, any non-volatile memory may be used without limiting to the memories described above.
The OS 14 includes the process characteristic collection unit 141, the interrupt coalescing unit 144, and the process scheduler 143, and performs process execution control for an enhanced power-saving effect, by shutting off power to the CPU core 18 in the CPU 11 and the memory 19 in the memory unit 13.
The process characteristic collection unit 141 collects information about the processes 151 to 15n, including a load characteristic such as a CPU utilization rate, a cache hit rate, and context switching frequency, and an interrupt characteristic such as frequency of interrupts caused by input/output of a device or the like.
The interrupt coalescing unit 144 coalesces interrupts to a process with a low load characteristic, in accordance with the load characteristics and the interrupt characteristics of the processes 151 to 15n, collected by the process characteristic collection unit 141. The interrupt coalescing unit 144 monitors a load characteristic and interrupt frequency of each process, and coalesces interrupts to a process with low values of such characteristics. Thus, continuous downtime of a CPU core 18 can be extended in a process with low values of a load characteristic and interrupt frequency.
The process scheduler 143 executes interrupts coalesced by the interrupt coalescing unit 144.
The process characteristic collection unit 141 collects load characteristics and interrupt characteristics, i.e. resource utilization characteristics, of the processes 151 to 15n that operate on the physical machine 1 (Step C1).
Next, the interrupt coalescing unit 144 refers to the process characteristics collected by the process characteristic collection unit 141 and coalesces interrupts to a low-load process (Step C2). A CPU utilization rate and interrupt frequency of each process are used as criteria here, and interrupts are coalesced when the characteristic values are lower than predetermined thresholds. Interrupt coalescing is completed when a certain number of interrupts, occurring randomly and stored in a queue, are accumulated, or a certain period of time elapses. Thus, continuous downtime of a CPU core 18 can be extended in a process with a low load and low interrupt frequency.
Next, the process scheduler 143 executes interrupts coalesced by the interrupt coalescing unit 144 (Step C3).
At this time, power-OFF/ON of a CPU core 18 and a memory 19 is automatically controlled by the power gating function of the CPU 11. In other words, even when an entire system is in operation, components other than components such as a CPU core 18 and a memory 19 that should actually operate at the moment can be powered OFF, and components such as a CPU core 18 and a memory 19 that should actually operate can be powered ON.
Further, since the memory unit 13 uses a non-volatile memory 19, there is no need for saving data stored in the memory 19 into another memory, or restoring data saved in another memory to the memory 19, when powering OFF/ON the memory 19. Therefore, smooth normally-off computing with suppressed delay is provided.
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 1 in
The present exemplary embodiment provides coalescing of interrupts to a process with a low CPU utilization rate and low interrupt frequency, and therefore long and continuous downtime of a CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
As illustrated in
Next, the interrupt coalescing unit 164 coalesces interrupts to a VM with a low load characteristic, in accordance with the VM characteristics collected by the VM characteristic collection unit 161 (Step D2). A CPU utilization rate and interrupt frequency of each VM are used as criteria here, and interrupts are coalesced when the characteristic values are lower than predetermined thresholds. Interrupt coalescing is completed when a certain number of interrupts, occurring randomly and stored in a queue, are accumulated, or a certain period of time elapses. Thus, continuous downtime of a CPU core 18 can be extended in a VM with a low load and low interrupt frequency.
Next, the VM scheduler 163 executes interrupts coalesced by the interrupt coalescing unit 164 (Step D3).
At this time, power-OFF/ON of a CPU core 18 and a memory 19 is automatically controlled by the power gating function of the CPU 11. In other words, even when an entire system is in operation, components other than components such as a CPU core 18 and a memory 19 that should actually operate at the moment can be powered OFF, and components such as a CPU core 18 and a memory 18 that should actually operate can be powered ON.
Further, since the memory unit 13 uses a non-volatile memory 19, there is no need for saving data stored in the memory 19 into another memory, or restoring data saved in another memory to the memory 19, when powering OFF/ON the memory 19. Therefore, smooth normally-off computing with suppressed delay is provided.
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 2 in aforementioned
The present exemplary embodiment provides coalescing of interrupts to a VM with a low CPU utilization rate and low interrupt frequency, and therefore long and continuous downtime of a CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a twelfth exemplary embodiment of the present invention will be described. The twelfth exemplary embodiment of the present invention has a configuration of the physical machine 1 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step C1 in
In Step C2 in
Step C3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 1 in
The present exemplary embodiment provides coalescing of interrupts to a process with low process priority, and therefore long and continuous downtime of a CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a thirteenth exemplary embodiment of the present invention will be described. The thirteenth exemplary embodiment of the present invention has a configuration of the physical machine 2 illustrated in
A flowchart illustrating a procedure of a power-saving control method according to the present exemplary embodiment will be described by use of
Step D1 in
In Step D2 in
Step D3 in
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 2 in aforementioned
The present exemplary embodiment provides coalescing of interrupts to a VM with low VM priority, and therefore long and continuous downtime of a CPU core and a memory working therewith due to power shut-off can be secured. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
The CPU 11 is a CPU that executes the OS 14 and the processes 151 to 15n.
The I/O device 12 includes an interface for data exchange with various devices such as a network.
The memory unit 13 includes one or more memories 19 (m memories in
The memory unit 13 may also be a memory including one or more memory areas. In this case, a memory area corresponds to the memory 19.
As a non-volatile memory, an ReRAM, an MRAM, an STT-MRAM, a PRAM, an FeRAM, and the like may be used. Further, any non-volatile memory may be used without limiting to the memories described above.
The OS 14 includes the process scheduler 143 and the memory power control unit 145, and performs process execution control for an enhanced power-saving effect, by shutting off power to the memory 19 in the memory unit 13.
The process scheduler 143 performs scheduling of the processes 151 to 15n, notifies the memory power control unit 145 of a process 15i (where i is 1 to n) to be executed, and then executes the scheduled process 15i.
The memory power control unit 145 powers ON a memory 19 for the process 15i notified by the process scheduler 143, and, at the same time, powers OFF a memory 19 for a process in execution up to that point.
The power-saving control system according to the present exemplary embodiment powers ON a memory 19 for a process operating on the OS 14 and powers OFF a memory 19 for a remaining process not in execution, and therefore a power shut-off range of the memory unit 13 can be extended to provide an enhanced power-saving effect.
Further, since the memory unit 13 uses a non-volatile memory 19, there is no need for saving data stored in the memory 19 into another memory, or restoring data saved in another memory to the memory 19, when powering OFF/ON the memory 19. Therefore, smooth normally-off computing with suppressed delay is provided.
The process scheduler 143 determines a process 15i to be executed, out of the processes 151 to 15n operating on the physical machine 1 (Step E1). As for selection of a process 15i to be executed, a scheduling algorithm for a general scheduler is assumed without limiting to a specific algorithm.
As an algorithm for the process scheduler, a FIFO (First In, First Out) algorithm that executes processes in order of arrival at an executable queue, or a round robin algorithm that executes each process in a certain sequence, may be used. Further, a priority preemptive algorithm that executes processes for a certain time in order of priority may also be used. An algorithm for the process scheduler is not limited to the algorithms described above.
The process scheduler 143 notifies the memory power control unit 145 of the process 15i to be executed (Step E2).
The memory power control unit 145 powers ON a memory 19 to be operated for the process 15i (Step E3).
The memory power control unit 145 powers OFF a memory 19 operated for a process in execution up to that point (Step E4). At this time, when a memory 19 operated for a process in execution up to that point overlaps with a memory 19 operated for the process 15i to be executed, the memory 19 operated for the process in execution up to that point continues to be powered ON.
The process scheduler 143 executes the process 15i to be executed (Step E5).
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 1 in aforementioned
The present exemplary embodiment provides the process execution control and the memory power control described above that power ON a memory for a process to be executed and power OFF a memory for a remaining process not in execution, and therefore a power shut-off range of a memory can be extended. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
In the present exemplary embodiment, a power shut-off range of the memory unit 13 can be extended to provide an enhanced power-saving effect, by powering ON a memory 19 for a VM in execution and powering OFF a memory 19 for a remaining VM not in execution.
Further, since the memory unit 13 uses a non-volatile memory 19, there is no need for saving data stored in the memory 19 into another memory, or restoring data saved in another memory to the memory 19, when powering OFF/ON the memory 19. Therefore, smooth normally-off computing with suppressed delay is provided.
As illustrated in
As an algorithm for the VM scheduler, a FIFO algorithm that executes VMs in order of arrival at an executable queue, or a round robin algorithm that executes each VM in a certain sequence, may be used. Further, a priority preemptive algorithm that executes VMs for a certain time in order of priority may also be used. An algorithm for the VM scheduler is not limited to the algorithms described above.
The VM scheduler 163 notifies the memory power control unit 165 of the VM 17i to be executed (Step F2).
The memory power control unit 165 powers ON a memory 19 to be operated for the VM 17i (Step F3).
The memory power control unit 165 powers OFF a memory 19 operated for a VM in execution up to that point (Step F4). At this time, when a memory 19 operated for a VM in execution up to that point overlaps with a memory 19 operated for the VM 17i to be executed, the memory 19 operated for the VM in execution up to that point continues to be powered ON.
The VM scheduler 163 executes the VM 17i to be executed (Step F5).
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 2 in aforementioned
The present exemplary embodiment provides the VM execution control and the memory power control described above that power ON a memory for a VM to be executed and power OFF a memory for a remaining VM not in execution, and therefore a power shut-off range of a memory can be extended. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a sixteenth exemplary embodiment of the present invention will be described. The sixteenth exemplary embodiment of the present invention has a configuration of a physical machine 3 illustrated in
The cache information collection unit 146 collects page information of a memory 19 retained in a cache by the CPU 11 (Step G1). It is assumed that the information is collected in synchronization with cache update.
The process scheduler 143 determines a process 15i (where i is 1 to n) to be executed, out of the processes 151 to 15n operating on the physical machine 3 (Step G2). As for selection of a process 15i to be executed, a scheduling algorithm for a general scheduler is assumed without limiting to a specific algorithm.
The process scheduler 143 notifies the memory power control unit 145 of the process 15i to be executed (Step G3).
The memory power control unit 145 acquires page information retained in a cache, with respect to a memory 19 to be operated for the process 15i, from the cache information collection unit 146 (Step G4).
The memory power control unit 145 powers ON a memory 19 that holds a page retained in the cache out of memories for the process 15i (Step G5).
The memory power control unit 145 powers OFF a memory 19 operated for a process in execution up to that point (Step G6). At this time, when a memory 19 operated for a process in execution up to that point overlaps with a memory 19 operated for the process 15i to be executed, the memory 19 operated for the process in execution up to that point continues to be powered ON.
The process scheduler 143 executes the process 15i to be executed (Step G7).
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 3 in aforementioned
The present exemplary embodiment provides process execution control and memory power control that power ON a page retained in a cache out of memories for a process to be executed, and shut off power to a memory with a page not being cached and a memory for a remaining process not in execution. Therefore, a power shut-off range of a memory can be extended. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a seventeenth exemplary embodiment of the present invention will be described. The seventeenth exemplary embodiment of the present invention has a configuration of a physical machine 4 illustrated in
The cache information collection unit 166 collects page information of a memory 19 retained in a cache by the CPU 11 (Step H1). It is assumed that the information is collected in synchronization with cache update.
The VM scheduler 163 determines a VM 17i (where i is 1 to n) to be executed, out of the VMs 171 to 17n operating on the physical machine 4 (Step H2). As for selection of a VM 17i to be executed, a scheduling algorithm for a general VM scheduler is assumed without limiting to a specific algorithm.
The VM scheduler 163 notifies the memory power control unit 165 of the VM 17i to be executed (Step H3).
The memory power control unit 165 acquires page information retained in a cache, with respect to a memory 19 to be operated in the VM 17i, from the cache information collection unit 166 (Step H4).
The memory power control unit 165 powers ON a memory 19 that holds a page retained in the cache out of memories for the VM 17i (Step H5).
The memory power control unit 165 powers OFF a memory 19 operated for a VM in execution up to that point (Step H6). At this time, when a memory 19 operated for a VM in execution up to that point overlaps with a memory 19 operated for the VM 15i to be executed, the memory 19 operated for the VM in execution up to that point continues to be powered ON.
The VM scheduler 163 executes the VM 17i to be executed (Step H7).
A power-saving control device according to the present exemplary embodiment is a power-saving control device that has a configuration of the physical machine 4 in aforementioned
The present exemplary embodiment provides VM execution control and memory power control that power ON a page retained in a cache out of memories for a VM to be executed, and shut off power to a memory with a page not being cached and a memory for a remaining VM not in execution. Therefore, a power shut-off range of a memory can be extended. Thus, an enhanced power-saving effect can be obtained.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, an eighteenth exemplary embodiment of the present invention will be described. The eighteenth exemplary embodiment of the present invention has a configuration of the physical machine 3 in
In the physical machine 3 according to the sixteenth exemplary embodiment illustrated in
On the other hand, in the physical machine 3 according to the present exemplary embodiment illustrated in
The remaining operation of the present exemplary embodiment is the same as the sixteenth exemplary embodiment.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
Next, a nineteenth exemplary embodiment of the present invention will be described. The nineteenth exemplary embodiment of the present invention has a configuration of the physical machine 4 in
In the physical machine 4 according to the seventeenth exemplary embodiment illustrated in
On the other hand, in the physical machine 4 according to the present exemplary embodiment illustrated in
The remaining operation of the present exemplary embodiment is the same as the seventeenth exemplary embodiment.
As described above, the present exemplary embodiment is able to provide normally-off computing with an enhanced power-saving effect in a server equipped with a non-volatile memory.
The aforementioned exemplary embodiments may also be described in whole or part as the following Supplementary Notes but are not limited thereto.
A power-saving control system including a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system that operates on the physical machine, and one or more processes that operate on the operating system, wherein the operating system includes a process characteristic collection unit that collects a characteristic of the process, a core allocation determination unit that determines allocation of the CPU core to the process, in accordance with the characteristic of the process, and a process scheduler that executes the process, in accordance with the allocation, and powers OFF/ON the CPU core or the memory, in accordance with execution of the process.
The power-saving control system according to Supplementary Note 1, wherein the memory is a non-volatile memory.
The power-saving control system according to Supplementary Note 1 or 2, wherein the characteristic of the process is a load characteristic of the process or a resource utilization characteristic.
The power-saving control system according to Supplementary Note 3, wherein the load characteristic of the process is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control system according to Supplementary Note 3, wherein the resource utilization characteristic is incoming/outgoing network traffic.
The power-saving control system according to Supplementary Note 4, wherein the core allocation determination unit performs allocation to the CPU core in descending order of the CPU utilization rate.
The power-saving control system according to Supplementary Note 4, wherein the core allocation determination unit performs allocation to the CPU core so as to level the CPU utilization rate.
The power-saving control system according to Supplementary Note 4, wherein the core allocation determination unit performs allocation to the CPU core in descending order of the context switching frequency.
The power-saving control system according to Supplementary Note 4, wherein the core allocation determination unit performs allocation to the CPU core so as to level the context switching frequency.
The power-saving control system according to any one of Supplementary Notes 1 to 9, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control device including a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system unit that operates on the physical machine, and one or more process units that are operated by the operating system unit, wherein the operating system unit includes a process characteristic collection unit that collects a characteristic of the process unit, a core allocation determination unit that determines allocation of the CPU core to the process unit, in accordance with the characteristic of the process unit, and a process scheduler that executes the process unit, in accordance with the allocation, and powers OFF/ON the CPU core or the memory, in accordance with execution of the process unit.
The power-saving control device according to Supplementary Note 11, wherein the memory is a non-volatile memory.
The power-saving control device according to Supplementary Note 11 or 12, wherein the characteristic of the process unit is a load characteristic of the process unit or a resource utilization characteristic.
The power-saving control device according to Supplementary Note 13, wherein the load characteristic of the process unit is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control device according to Supplementary Note 13, wherein the resource utilization characteristic is incoming/outgoing network traffic.
The power-saving control device according to Supplementary Note 14, wherein the core allocation determination unit performs allocation to the CPU core in descending order of the CPU utilization rate.
The power-saving control device according to Supplementary Note 14, wherein the core allocation determination unit performs allocation to the CPU core so as to level the CPU utilization rate.
The power-saving control device according to Supplementary Note 14, wherein the core allocation determination unit performs allocation to the CPU core in descending order of the context switching frequency.
The power-saving control device according to Supplementary Note 14, wherein the core allocation determination unit performs allocation to the CPU core so as to level the context switching frequency.
The power-saving control device according to any one of Supplementary Notes 11 to 19, wherein the operating system unit is a hypervisor, and the process unit is a virtual machine.
A power-saving control method of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the operating system collects a characteristic of the process, determines allocation of the CPU core to the process, in accordance with the characteristic of the process, executes the process, in accordance with the allocation, and powers OFF/ON the CPU core or the memory, in accordance with execution of the process.
The power-saving control method according to Supplementary Note 21, wherein the memory is a non-volatile memory.
The power-saving control method according to Supplementary Note 21 or 22, wherein the characteristic of the process is a load characteristic of the process or a resource utilization characteristic.
The power-saving control method according to Supplementary Note 23 wherein the load characteristic of the process is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control method according to Supplementary Note 23, wherein the resource utilization characteristic is incoming/outgoing network traffic.
The power-saving control method according to Supplementary Note 24, wherein the determination of core allocation is allocation to the CPU core performed in descending order of the CPU utilization rate.
The power-saving control method according to Supplementary Note 24, wherein the determination of core allocation is allocation to the CPU core performed so as to level the CPU utilization rate.
The power-saving control method according to Supplementary Note 24, wherein the determination of core allocation is allocation to the CPU core performed in descending order of the context switching frequency.
The power-saving control method according to Supplementary Note 24, wherein the determination of core allocation is allocation to the CPU core performed so as to level the context switching frequency.
The power-saving control method according to any one of Supplementary Notes 21 to 29, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control program of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system operating on the physical machine, and one or more processes operating on the operating system, the program causing the operating system to execute processing of collecting a characteristic of the process, processing of determining allocation of the CPU core to the process, in accordance with the characteristic of the process, processing of executing the process, in accordance with the allocation, and processing of powering OFF/ON the CPU core or the memory, in accordance with execution of the process.
The power-saving control program according to Supplementary Note 31, wherein the memory is a non-volatile memory.
The power-saving control program according to Supplementary Note 31 or 32, wherein the characteristic of the process is a load characteristic of the process or a resource utilization characteristic.
The power-saving control program according to Supplementary Note 33, wherein the load characteristic of the process is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control program according to Supplementary Note 33, wherein the resource utilization characteristic is incoming/outgoing network traffic.
The power-saving control program according to Supplementary Note 34, wherein the processing of determining allocation of the core is allocation to the CPU core performed in descending order of the CPU utilization rate.
The power-saving control program according to Supplementary Note 34, wherein the processing of determining allocation of the core is allocation to the CPU core performed so as to level the CPU utilization rate.
The power-saving control program according to Supplementary Note 34, wherein the processing of determining allocation of the core is allocation to the CPU core performed in descending order of the context switching frequency.
The power-saving control program according to Supplementary Note 34, wherein the processing of determining allocation of the core is allocation to the CPU core performed so as to level the context switching frequency.
The power-saving control program according to any one of Supplementary Notes 31 to 39, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control system including a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system that operates on the physical machine, and one or more processes that operate on the operating system, wherein the operating system includes a process characteristic collection unit that collects a load characteristic of the process or an interrupt characteristic of the process, an interrupt coalescing unit that coalesces interrupts to the process, in accordance with the load characteristic or the interrupt characteristic, and a process scheduler that executes interrupts in accordance with coalescing of the interrupts, and powers OFF/ON the CPU core or the memory, in accordance with execution of the interrupt.
The power-saving control system according to Supplementary Note 41, wherein the memory is a non-volatile memory.
The power-saving control system according to Supplementary Note 41 or 42, wherein the load characteristic is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control system according to any one of Supplementary Notes 41 to 43, wherein the interrupt characteristic is frequency of interrupts caused by input/output from/to a device or priority of the process.
The power-saving control system according to any one of Supplementary Notes 41 to 44, wherein the interrupt coalescing unit coalesces interrupts to a process with a low value of the load characteristic or the interrupt characteristic.
The power-saving control system according to any one of Supplementary Notes 41 to 45, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control device including a physical machine that includes a memory and a CPU including a plurality of CPU cores, an operating system unit that operates on the physical machine, and one or more process units that operate on the operating system, wherein the operating system unit includes a process characteristic collection unit that collects a load characteristic of the process unit or an interrupt characteristic of the process unit, an interrupt coalescing unit that coalesces interrupts to the process unit, in accordance with the load characteristic or the interrupt characteristic, and a process scheduler that executes interrupts, in accordance with coalescing of the interrupts, and powers OFF/ON the CPU core or the memory, in accordance with execution of the interrupt.
The power-saving control device according to Supplementary Note 47, wherein the memory is a non-volatile memory.
The power-saving control device according to Supplementary Note 47 or 48, wherein the load characteristic is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control device according to any one of Supplementary Notes 47 to 49, wherein the interrupt characteristic is frequency of interrupts caused by input/output from/to a device or priority of the process.
The power-saving control device according to any one of Supplementary Notes 47 to 50, wherein the interrupt coalescing unit coalesces interrupts to a process unit with a low value of the load characteristic or the interrupt characteristic.
The power-saving control device according to any one of Supplementary Notes 47 to 51, wherein the operating system unit is a hypervisor, and the process unit is a virtual machine.
A power-saving control method of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system that operates on the physical machine, and one or more processes that operate on the operating system, wherein the operating system collects a load characteristic of the process or an interrupt characteristic of the process, coalesces interrupts to the process, in accordance with the load characteristic or the interrupt characteristic, executes interrupts, in accordance with coalescing of the interrupts, and powers OFF/ON the CPU core or the memory, in accordance with execution of the interrupt.
The power-saving control method according to Supplementary Note 53, wherein the memory is a non-volatile memory.
The power-saving control method according to Supplementary Note 53 or 54, wherein the load characteristic is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control method according to any one of Supplementary Notes 53 to 55, wherein the interrupt characteristic is frequency of interrupts caused by input/output from/to a device or priority of the process.
The power-saving control method according to any one of Supplementary Notes 53 to 56, wherein the interrupt coalescing coalesces interrupts to a process with a low value of the load characteristic or the interrupt characteristic.
The power-saving control method according to any one of Supplementary Notes 53 to 57, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control program of a power-saving control system that includes a physical machine including a memory and a CPU including a plurality of CPU cores, an operating system operating on the physical machine, and one or more processes operating on the operating system, the program causing the operating system to execute processing of collecting a load characteristic of the process or an interrupt characteristic of the process, processing of coalescing interrupts to the process, in accordance with the load characteristic or the interrupt characteristic, processing of executing an interrupt, in accordance with coalescing of the interrupts, and processing of powering OFF/ON the CPU core or the memory, in accordance with execution of the interrupt.
The power-saving control program according to Supplementary Note 59, wherein the memory is a non-volatile memory.
The power-saving control program according to Supplementary Note 59 or 60, wherein the load characteristic is a CPU utilization rate, a cache hit rate, or context switching frequency.
The power-saving control program according to any one of Supplementary Notes 59 to 61, wherein the interrupt characteristic is frequency of interrupts caused by input/output from/to a device or priority of the process.
The power-saving control program according to any one of Supplementary Notes 59 to 62, wherein the processing of coalescing interrupts coalesces interrupts to a process with a low value of the load characteristic or the interrupt characteristic.
The power-saving control program according to any one of Supplementary Notes 59 to 63, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control system including a physical machine that includes a CPU and a memory, an operating system that operates on the physical machine, and one or more processes that operate on the operating system, wherein the operating system includes a process scheduler that performs scheduling of the process, and a memory power control unit that powers ON/OFF the memory, in accordance with the scheduling.
The power-saving control system according to Supplementary Note 65, wherein the memory is a non-volatile memory.
The power-saving control system according to Supplementary Note 65 or 66, wherein the process scheduler executes the process, in accordance with the scheduling.
The power-saving control system according to any one of Supplementary Notes 65 to 67, wherein the memory power control unit powers ON the memory related to the process executed by the process scheduler.
The power-saving control system according to any one of Supplementary Notes 65 to 68, wherein the memory power control unit powers OFF the memory other than the memory related to the process executed by the process scheduler.
The power-saving control system according to any one of Supplementary Notes 65 to 69, wherein the operating system includes a cache information collection unit that collects page information of a memory retained in a cache by the CPU, and the memory power control unit acquires the page information from the cache information collection unit, and powers ON the memory, in accordance with the page information.
The power-saving control system according to any one of Supplementary Notes 65 to 70, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control device including a physical machine that includes a CPU and a memory, an operating system unit that operates on the physical machine, and one or more process units operated by the operating system unit, wherein the operating system unit includes a process scheduler that performs scheduling of the process unit, and a memory power control unit that powers ON/OFF the memory, in accordance with the scheduling.
The power-saving control device according to Supplementary Note 72, wherein the memory is a non-volatile memory.
The power-saving control device according to Supplementary Note 72 or 73, wherein the process scheduler executes the process unit, in accordance with the scheduling.
The power-saving control device according to any one of Supplementary Notes 72 to 74, wherein the memory power control unit powers ON the memory related to the process unit executed by the process scheduler.
The power-saving control device according to any one of Supplementary Notes 72 to 75, wherein the memory power control unit powers OFF the memory other than the memory related to the process unit executed by the process scheduler.
The power-saving control device according to any one of Supplementary Notes 72 to 76, wherein the operating system unit includes a cache information collection unit that collects page information of a memory retained in a cache by the CPU, and the memory power control unit acquires the page information from the cache information collection unit, and powers ON the memory, in accordance with the page information.
The power-saving control device according to any one of Supplementary Notes 72 to 77, wherein the operating system unit is a hypervisor, and the process unit is a virtual machine.
A power-saving control method of a power-saving control system that includes a physical machine including a CPU and a memory, an operating system operating on the physical machine, and one or more processes operating on the operating system, wherein the operating system performs scheduling of the process, and powers ON/OFF the memory, in accordance with the scheduling.
The power-saving control method according to Supplementary Note 79, wherein the memory is a non-volatile memory.
The power-saving control method according to Supplementary Note 79 or 80, wherein the scheduling of the process executes the process, in accordance with the scheduling.
The power-saving control method according to any one of Supplementary Notes 79 to 81, wherein powering ON/OFF of the memory powers ON the memory related to the process executed in accordance with the scheduling.
The power-saving control method according to any one of Supplementary Notes 79 to 82, wherein powering ON/OFF of the memory powers OFF the memory other than the memory related to the process executed in accordance with the scheduling.
The power-saving control method according to any one of Supplementary Notes 79 to 83, wherein the operating system collects page information of a memory retained in a cache by the CPU, and power control of the memory acquires the page information, and powers ON the memory, in accordance with the page information.
The power-saving control method according to any one of Supplementary Notes 79 to 84, wherein the operating system is a hypervisor, and the process is a virtual machine.
A power-saving control program of a power-saving control system that includes a physical machine including a CPU and a memory, an operating system operating on the physical machine, and one or more processes operating on the operating system, the program causing the operating system to execute processing of scheduling the process, and processing of powering ON/OFF the memory, in accordance with the scheduling.
The power-saving control program according to Supplementary Note 86, wherein the memory is a non-volatile memory.
The power-saving control program according to Supplementary Note 86 or 87, wherein processing of scheduling the process executes the process, in accordance with the scheduling.
The power-saving control program according to any one of Supplementary Notes 86 to 88, wherein processing of powering ON/OFF the memory powers ON the memory related to the process executed in accordance with the scheduling.
The power-saving control program according to any one of Supplementary Notes 86 to 89, wherein processing of powering ON/OFF the memory powers OFF the memory other than the memory related to the process executed in accordance with the scheduling.
The power-saving control program according to any one of Supplementary Notes 86 to 90, further causing the operating system to execute processing of collecting page information of a memory retained in a cache by the CPU, wherein processing of powering ON/OFF the memory acquires the page information, and powers ON the memory, in accordance with the page information.
The power-saving control program according to any one of Supplementary Notes 86 to 91, wherein the operating system is a hypervisor, and the process is a virtual machine.
The present invention is not limited to the aforementioned exemplary embodiments and may be modified in various ways within the scope of the invention described in CLAIMS, and such modifications are also included in the scope of the invention.
This application claims priority based on Japanese Patent Application No. 2013-161302 filed on Aug. 2, 2013, Japanese Patent Application No. 2013-161303 filed on Aug. 2, 2013, and Japanese Patent Application No. 2013-161304 filed on Aug. 2, 2013, the disclosure of which is hereby incorporated by reference thereto in its entirety.
The present invention is available as a technology enhancing a power-saving effect in a normally-off computing technology in a server equipped with a non-volatile memory.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013-161302 | Aug 2013 | JP | national |
| 2013-161303 | Aug 2013 | JP | national |
| 2013-161304 | Aug 2013 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2014/003848 | 7/22/2014 | WO | 00 |
