Patent Application
20080158117
Low power consumption is a design goal for many electronic devices. This is particularly true for mobile computing devices, and those using color displays. Improvements in display technology have provided bright, colorful displays with many more capabilities than previous displays. Along with the improved display technology, however, has come increased power consumption.
Some display drivers provide a partial display or partial refresh feature. In one example of such a feature, a display driver may switch from providing full display data to a liquid crystal display (LCD) to providing partial display data to the LCD from a dedicated memory. This may allow the display driver to enter a lower power mode and further allow a microprocessor or application-specific integrated circuit providing the display data to the display driver to enter a low power or sleep mode. However, further reductions in power consumption are needed.
Accordingly, what is needed is an improved system and method for reducing power consumption in a display system. Further what is needed is a mobile computing device which has a longer operating time on a single battery charge than in previous devices. Further still what is needed is a system and method for further reducing power consumption in a partial display mode or in a full display mode. Further still, what is needed is a system and method for providing other advantageous features associated with periodically removing a power supply signal from a liquid crystal display.
The teachings herein extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
Referring first to
Device 10 comprises a display 12 (which may be a plurality of displays of different types and sizes) and a user input device 14 (e.g., a QWERTY keyboard, buttons, touch screen, speech recognition engine, etc.). Device 10 also comprises an earpiece speaker 15. Earpiece speaker 15 may be a speaker configured to provide audio output with a volume suitable for a user placing earpiece 15 against or near the ear. Earpiece 15 may be positioned above display 12 or in another location on device 10. Device 10 comprises a housing 11 having a front side 13 and a back side 17 (
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Device 10 comprises a transceiver 24 which comprises analog and/or digital electrical components configured to receive and transmit wireless signals via antenna 28 to provide cellular telephone and/or data communications with a fixed wireless access point, such as a cellular telephone tower, in conjunction with a network carrier, such as, Verizon Wireless, Sprint, etc. Device 10 can further comprise circuitry to provide communication over a local area network, such as Ethernet or according to an IEEE 802.11x standard or a personal area network, such as a Bluetooth or infrared communication technology.
Device 10 further comprises a microphone 30 configured to receive audio signals, such as voice signals, from a user or other person in the vicinity of device 10, typically by way of spoken words. Microphone 30 is configured as an electro-acoustic sense element to provide audio signals from the vicinity of device 10 and to convert them to an electrical signal to provide to processor 22. Processor 22 can provide a digital memo recorder function, wireless telephone function, etc. with words spoken into microphone 30. Processor 22 may also provide speech recognition and/or voice control of features operable on device 10. Display 12 can comprise a touch screen display in order to provide user input to processor 22 to control functions, such as to dial a telephone number, enable/disable speakerphone audio, provide user inputs regarding increasing or decreasing the volume of audio provided through earpiece 15 and/or loudspeaker 16, etc. Alternatively or in addition, user input device 14 can provide similar inputs as those of touch screen display 12. Device 10 can further comprise a stylus 31 to assist the user in making selections on display 12. Processor 22 can further be configured to provide video conferencing capabilities by displaying on display 12 video from a remote participant to a video conference, by providing a video camera on device 12 for providing images to the remote participant, by providing text messaging, two-way audio streaming in full- and/or half-duplex mode, etc.
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Display driver 36 is configured to receive power signal 46 and to drive pixels on display 12 based on the power signal and based on display data received via a display data signal 58 from system ASIC 40 and, more particularly, a display controller portion 60 (e.g., LCD controller) of system ASIC 40. Display driver 36 is further configured to receive serial display data via a serial display data signal 62 from a serial interface portion 64 of system ASIC 40 for storage in a display driver memory 66, for example, for a partial display or partial refresh mode as will be described below. Suitable clock and enable signals 68 are also provided from display controller 60 to digital circuit portion 54. Other data, control, and power signals may be provided between processing circuit 20 and display driver 36 according to various alternative embodiments. In this exemplary embodiment, display driver 36 may be an FPD95120, FPD95220 or FPD93140 display driver manufactured by National Semiconductor Corporation, but may be other display drivers.
As mentioned, display driver 36 is configured to receive power signal 46 and to drive pixels on display 12 via their corresponding electrodes based on power supply signal 46 and based on display data 58, 62 received from system ASIC 40 or replayed from memory 66. Processing circuit 20 is further configured to use a switch 70 or other mechanism (e.g., a high side switch, a field-effect transistor, such as a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET) designed for high side switching, etc.) to periodically remove power signal 46 (or in an alternative embodiment power signal 32) from at least a portion of display driver 36, in this embodiment power supply circuit 48. Switch 70 may have a rating over the max Vbatt, such as 4.2 Volts and a low Rds(on). In an alternative embodiment, switch 70 is placed between battery 50 and power supply 44. Removing power signal 46 to disable power supply 44 from a portion of display driver 36 also disables the voltage required to turn on or refresh a display pixel of display 12. Residual voltages across the pixels will maintain an image being displayed on display 12 for a period of time. By removing power from power supply circuit 48, power consumption may be reduced. The persistence of the liquid crystals may be utilized to allow powering down subsystems of display driver 36 (and not refreshing display 12 regularly) while maintaining a consistent image on display 12. Power signals 46 or 32 may be removed, cycled, pulsed, attenuated, reduced, disconnected, or decreased.
According to one exemplary embodiment, display 12 and display driver 36 require a plurality of power signals, one regulated for digital power, such as the digital voltage power supply signal and one which may be unregulated (e.g., Vbatt, such as power signal 46) that display driver 36 may use to generate various display driving voltages (which may include +5V, −5V, etc., depending on the display technology and specifications of display driver 36). In this exemplary embodiment, Vbatt, which is the source of display driving voltages, may be removed while maintaining the supply of digital voltage power supply signal to display driver 36. As a result, display driver 36 may continue to function, but it does not have the driving voltage or voltages needed to actively switch on the pixels as it would have in a normal operating mode. By removing Vbatt, in this exemplary embodiment, a high power consuming portion or perhaps the most power consuming portion of display driver 36 will no longer be consuming power because the power supply signal to that portion has been removed.
A regular or normal refresh rate of display 12 may be fixed or variable according to software and/or ASIC programming and may, in an exemplary embodiment, provide a display refresh rate of between 50 and 70 Hertz (Hz). The periodic removal or cycling of power signal 46 may be provided with a variety of frequencies and/or duty cycles. In an exemplary embodiment, power may be removed or the display may be refreshed with a frequency of approximately 0.005 to 10 Hz (corresponding to a period of between approximately greater than 0.1 seconds and/or less than approximately 200 seconds between power cycling). According to another exemplary embodiment, processing circuit 20 is configured to remove the power signal with a period of less than approximately 20 seconds. The removal of power may happen automatically, without user interaction.
Further, the removal or cycling of power signal 46 can happen with a rate or frequency or duty cycle which is dynamically adjusted. For example, at least one of a duty cycle and frequency can be adjusted or set based on a criteria, such as a temperature (e.g. an ambient temperature). The settling time of crystals may vary based on temperature, and power savings can be optimized by providing a dynamic control based on this criteria. The removal of power signal 46 can further be dynamically adjusted based on whether display driver 36 is operating in a normal display mode or a partial display mode, as will be described below. The removal of power signal 46 can further be dynamically varied based on the type of display data being provided on display. For example, in a situation when backlight 42 is on and display 12 is displaying a static image such as a calendar, a black and white e-mail, etc., power signal 46 can be cycled to provide power savings. Thus, processing circuit 20 can be configured to cycle or remove power from power supply circuit 48 or another portion of display driver 36 in varying frequencies and duty cycles during a plurality of different modes of operations and/or based on display data, temperature, and/or other criteria.
According to one exemplary embodiment, power can be saved in situations when display data updates less frequently than a normal or regular display mode. Power can be reduced or removed from one or more portions of display driver 36 and/or display 12. In one embodiment, power signal 46 is removed or reduced. In another embodiment, digital voltage power signal 56 may also be removed or reduced, along with or independent of power signal 46. Further, signals provided to display 12 from display driver 36 may also be reduced or removed. A persistence effect of the liquid crystals within display 12 can be used to increase the period of activating or refreshing the portions of display driver 36 with little or no user-perceptable effect.
According to one exemplary embodiment, display driver 36 is operable in a first display mode (e.g., a normal or regular display mode having a conventional refresh rate of between 50 and 70 Hz or other refresh rate) and a second display mode (e.g., a partial display mode). In the second display mode, display driver 36 is configured to refresh display 12 with substantially less display data than in the first display mode. For example, partially refreshing display 12 may comprise reducing a refresh rate, a display size, and/or switching from color to black and white, monochrome or grayscale or a reduced bit-depth color mode. According to one embodiment, memory 26 is a buffer (e.g., static random access memory (SRAM) or dynamic random access memory (DRAM)) on driver 36 which can allow refresh of a portion of display data without requiring system ASIC 40 and display controller 60 to continuously transmit display data to driver 36. According to one example, a full screen or normal image may be provided on display 12 with 320 by RGB (red, green, blue) by 320 pixels with 16 bits per pixel (bpp), but in a second display mode, memory 66 provides 320 by RGB by 80 pixels at 3 bpp. In one embodiment, in a partial display mode, every pixel on the screen or on display 12 is refreshed, wherein pixels not having display data stored in memory 66 may be refreshed with blank, default or no data. Partial refresh may occur at 30-45 Hz refresh rate or other rates.
The second display mode may also comprise at least one of microprocessor 38, system ASIC 40, and display driver 36 or portions thereof, entering a low power mode (e.g., a mode in which power consumption is lower than another, typically normal operating mode). According to another embodiment, a second display mode may comprise a mode in which processing circuit 20 is configured to dim or turn off backlight 42, wherein the partial display data displayed on display 12 is illuminated by reflected light or another low power light source. According to one exemplary embodiment, in second display mode, display 12 is configured to show the time of day, battery charge status, date, wireless signal strength, wireless communication type, whether a message has been received in an inbox, etc.
Second display mode can comprise a partial display mode in which the entire display is used (e.g., an image is provided on substantially all of the screen) but only a black and white image is shown or the image is refreshed at a lower rate than a normal refresh mode.
Referring to
According to one embodiment, in a first display mode, system ASIC 40 is configured to provide data via display data signal 58 (e.g., a parallel bus, comprising 16 bits, though serial or other buses may be used) to display driver 36. Digital circuit 54 is configured to provide the display data via control lines 78 to display 12 in this first mode. System ASIC 40 provides a timing signal to shift display data into driver 36 which latches the data to display 12, for example line after line. First display mode may provide a full 16-bit, high-contrast, display and/or other display characteristics associated with a typical normal display mode. In second display mode, memory 66 can be configured to receive display data on a serial display data signal 62 via serial interface 64 of system ASIC 40 along a serial interface port. Alternatively, memory 66 can be configured to receive data via parallel ports or other communication ports. In second display mode, memory 66 provides data through digital circuit 54 to continually refresh at least a portion of display 12. In one exemplary embodiment, prior to entering a sleep or low power mode, processing circuit 20 shifts into memory 66 display data sufficient to provide a partial display on display 12. Portions of processing circuit 20 then enter a sleep mode, while a portion or a subsystem of display driver 36 continues to refresh display 12 with a sufficient refresh rate to provide a steady image from a user's perspective (e.g., or even to provide a blinking display which dims over time, or even a blinking display separated by a period of no display for several seconds or more). In the first display mode, display refresh rates can be between 50 and 55 Hz, or other display refresh rates. In the second display mode, refresh rates can be 30 Hz or less, or other display refresh rates.
According to another exemplary embodiment, a first display mode can be a display mode in which display 12 is refreshed at a first refresh rate, for example 50 to 70 Hz. Second display mode may also be a display mode in which substantially all of display 12 is refreshed, optionally in full color, but in this exemplary second display mode, the refresh frequency is reduced to a lower refresh rate, such as, less than 50 Hz, less than 20 Hz, etc. In this exemplary embodiment, memory 66 need not be used, and instead, data is continually provided from system ASIC or from a different memory either on driver device 36, or off-chip comprising sufficient data for a full screen display. As another alternative, in this embodiment, power may be removed from any portion or portions of display driver 36. Alternatively, power can be maintained on display driver 36 throughout second mode, wherein power savings is realized from a lower refresh rate of display 12.
According to one embodiment, power supply 48 can be an analog power supply for display 12, configured to provide a main or primary power to display 12 via power line 80 (e.g., power provided to the LCD glass or other electrodes).
According to various alternative embodiments, the components of processing circuit 20 may be on different chips or on a single chip. For example, display driver 36 and processor 20 may be disposed on a single integrated circuit. Microprocessor 38 and system ASIC 40 may be disposed on a single integrated circuit. Display driver 36 and system ASIC 40 may be disposed on a single integrated circuit. Furthermore, switch control signal 82 which is configured to remove power via switch 70 may be provided by system ASIC 40 or a component thereof, such as LCD controller 60, by microprocessor 38, by driver 36 or by another control circuit.
Referring to
While the exemplary embodiments illustrated in the Figs., and described above are presently exemplary, it should be understood that these embodiments are offered by way of example only. For example, other display drivers may allow for removing power from different subsystems or portions of the driver to save power. Further, the features disclosed herein may be applied to other electronic devices, such as laptop computers, handheld navigation devices comprising location determination circuitry, etc. Further still, the backlight can be selectively turned on or off, or even pulsed, in any of the different embodiments or modes of embodiments disclosed herein to provide further power savings. Accordingly, the present invention is not limited to a particular embodiment, but extends to various modifications that nevertheless fall within the scope of the appended claims.
