Patent Application
20080155287
When a command-based architecture is used with non-volatile memory devices, one or more commands may be sent to multiple memory devices on a common bus. The commands may indicate which of the multiple memory devices is to perform a memory operation, and also what memory operation the selected device is to perform. Other information, such as address and data for the selected memory device, may then follow on the same bus lines. Once the command has selected a particular memory device, the other memory devices can ignore the remaining address and data information, but must still remain powered up so they can monitor the bus for the next command. This need to stay powered up can result in consuming a lot of power by individual memory devices that are inactive most of the time.
Some embodiments of the invention may be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:
In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
References to “one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) of the invention so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” is used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” is used to indicate that two or more elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.
As used in the claims, unless otherwise specified the use of the ordinal adjectives “first”, “second”, “third”, etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
Some embodiments of the invention may use a single signal line as both a wake up indicator and as a selection command indicator. In a command-based protocol on a non-volatile memory bus, a host memory controller may issue a wake up signal concurrently with a command to select a particular memory device for an operation. The subsequent memory bus cycles may then be used for identifying the particular type of operation, providing address information, and/or transferring data to/from the selected memory device. The non-selected memory devices may go into a sleep mode after the selection command and only wake up when a new wake up signal is issued.
Each memory device 120-12n may be controlled by a host controller 110, which in the illustrated embodiment controls the memory devices through a common bus containing a set of input/output (I/O) lines D[15:0], a clock line CLK, and a control line WAK that connects in parallel to all the memory devices on the bus. Although specific labels are used here to describe the various lines and their functions, these are for convenience only and other embodiments may use any convenient set of labels. Sixteen I/O lines are indicated by D[15:0] in the drawing, but other embodiments may contain other quantities of I/O lines (e.g., 4, 8, 32, 64, etc.). In some embodiments, the bus may contain no other signal lines than the ones shown. Power lines to provide operating power to the memory devices are not shown, and may take any feasible form. During operation, the host controller may select, and communicate with, any of the memory devices 120-12n over the bus, by placing a command on the I/O lines and asserting a signal on the WAK line. In some embodiments, the host controller may reside in a separate integrated circuit from the memory devices.
In the illustrated embodiment, the host controller 110 may transfer data to or from one of the memory devices by first sending a selection command over the I/O lines that indicates which of the memory devices is being selected for an operation. Concurrently with this command, the WAK line may be asserted to cause the memory devices on the bus to wake up and sense the I/O lines. The particular memory device that sees its own identification number on those I/O lines may then stay active to continue communications with the host controller, while the remaining memory devices may return to a sleep mode. In subsequent clock cycles on the bus, the selected memory device may receive further information on the I/O lines about the intended operation, and may also transfer data over those I/O lines. For example, the clock cycle following the selection command may contain an indicator of what type of operation the selected device is to perform. Clock cycles may also contain an address at which a data transfer operation is to start in the memory array of the selected memory device.
In some embodiments, the host controller may also initiate operations that do not involve memory addresses. For instance, the host controller may issue a command that the selected memory device is to return some type of status information to the host controller. In such a case, no memory address need be sent, and the selected memory device might follow the operations command by placing its requested status on the I/O lines for reading by the host controller. Similarly, the host controller might issue a command that configuration data is to be written into the memory device, in which case the host controller might follow the command by placing the configuration data on the I/O lines, for reading and implementation by the selected memory device.
In the embodiment shown, a WAK signal is asserted (in the example, low is asserted, high is deasserted) to cause the memory devices on the memory bus to wake up and sense the I/O lines. The data on the I/O lines during that time may be latched in the memory device by the CLK signal and used to determine which memory device is being selected for an operation. All non-selected memory devices may return to the sleep mode after the WAK signal is deasserted, while the selected memory device may remain active to continue with the communications sequence. The illustrated embodiment implements the wakeup and selection operation in a single clock cycle, implying for this example that all versions of a selection command may be contained within the 16 available I/O lines, and that the non-selected devices don't need to perform other operations before going back into a sleep mode. Other embodiments may use other conventions. In the clock cycle following the wakeup command, an operation command may be placed on the I/O lines by the host controller to define what type of operation is to be performed by the selected memory device. Some examples might be read data, write data, read status, write configuration, etc. In some embodiments the number of clock cycles in the selection command and/or the operation command may be fixed, but in other embodiments the first part of the command itself may contain an indication of how many clock cycles are to be used to transfer the entire command.
In some embodiments if the command indicates a data transfer is to be conducted involving the selected device's memory array, the operation command may contain a starting address for that data transfer. In other embodiments, the subsequent clock cycles may be used for that information. All subsequent clock cycles after the operation command have been labeled DATA in the drawing. The exact nature of that data may vary, depending on the operation. Some embodiments may use a separate signal (not shown) that will wake up the memory devices even though a selection command is not in progress. For example, a reset signal might cause all the memory devices to wake up and place themselves in a known initial configuration
Note: as used in this document, a ‘sleep mode’ may represent any low power mode that the memory device can be placed in that makes the memory device non-operational and reduces its power consumption but does not cause loss of stored data in the memory device. This may encompass low power modes that may be described by others with other terms.
In some embodiments the length of the sequence (or of some portion of the sequence, such as the data portion) may be fixed. In other embodiments, the length may be variable, and a portion of the selection and/or operation command may specify that length.
By following the techniques described here, a non-volatile memory system may keep all the memory devices on the bus in a sleep mode until a device selection command is issued, and return all but the selected memory device to a sleep mode while the indicated operation is being performed with the selected memory device. Alternately, any memory device that is already awake and performing an operation when the selection command is received may remain awake and continue performing its task even though it was not selected by the selection command. Thus, multiple memory devices may each perform individual operations at the same time without departing from the protocol, allowing operations with long execution times (e.g., array read, array write, erase) to be performed in an efficient, time-overlapping manner across multiple devices.
The foregoing description is intended to be illustrative and not limiting. Variations will occur to those of skill in the art. Those variations are intended to be included in the various embodiments of the invention, which are limited only by the spirit and scope of the following claims.
