Patent Application
20080101175
The present invention generally relates to a power saving method and a power saving system applied in an optical disk drive, and more particularly, to a power saving method and system for powering down the circuits not being used during the operation of the optical disk drive.
As the development of the portable electronic products, the requirements for power saving are more and more critical. For a notebook personal computer (NB, or called laptop PC), each component is required to consume power as less as possible so as to save the power of a battery used in the NB.
Similarly, the optical disk drive used in the notebook PC is also required to diminish its power consumption. Conventional optical disk drive only stops the spindle motor while the optical disk drive is not reading or writing an optical disk to reduce the power consumption. However, the conventional optical disk drive supplies power to all circuits of chip(s) thereof all the time, no matter being used or not.
The operation of the optical disk drive can be divided into several operation modes, and each mode is executed by some specific circuits in a control chip. When the optical disk drive is operated in a specific mode, only some circuits in the control chip are used, the other circuits not used in this mode can be powered down without effecting the normal operation of the optical disk drive.
Accordingly, the circuits not being used in the chip can be powered down for reducing the power consumption of the optical disk drive when the optical dick drive is operated in a specific operation mode. Therefore, the portable electronic product which comprises an optical disk drive can maximally save power by reducing the power consumption of the optical disk drive thereof.
A primary objective of the present invention is to provide a power saving method applied in an optical disk drive. The power saving method is capable of reducing the power consumption of the optical disk drive by powering down the circuits not being used during the operation of the optical disk drive.
The present invention sets forth a power saving method and a power saving system applied in an optical disk drive. The power saving system comprises a central processing unit, a spindle motor, an optical pick-up unit, an analog portion of control circuits and a digital portion of control circuits. Each of the analog or digital portions of control circuits can be divided into several sets of control circuits. Each set of control circuits is related to an operation mode of the optical disk drive. The power saving system further comprises a power controlling unit for differentiating the sets of control circuits not being used in the specific operation mode and powering them down. Those powered-down sets of control circuits will be powered up when an operation mode in which they are required to operate is nearly started.
The power saving method comprises following steps of:
In Step 4, the time point for powering down the first set of rest circuits not being used in the first operation mode can be determined by delaying a predetermined period from the time point of issuing the power up signal to power up the first set of control circuits related to the first operation mode. Therefore, the first set of rest circuits not being used in the first operation mode are powered down after the predetermined period ends. In other words, the second operation mode is finished before or when the predetermined period ends. The predetermined period can be predetermined according to the length of warm-up time of first set of control circuits related to the first operation mode. Alternatively, the time point for powering down the first set of rest circuits not being used in the first operation mode can be determined when the power controlling unit receives a signal for indicating that the first operation mode is actually started.
The present invention provides the power saving system and method applied in an optical disk drive. The power saving system and method of the present invention are adapted for powering down at least a set of control circuits not being used during a specific operation mode of the optical disk drive without effecting the normal operation of the optical disk drive. Therefore, the power saving system and method according to the present invention are capable of reducing the power consumption of the optical disk drive.
a-4d show an embodiment of detailed structure of logic unit.
a and 5b show a structure of determination rule for determining which power controlling signal should be outputted.
The present invention is directed to a power saving method and a power saving system applied in an optical disk drive. The power saving method and the power saving system in accordance with the present invention are capable of powering down the specific set of control circuits not being used during the operation of the optical disk drive.
As known, an optical disk drive includes several operation modes for executing a completed reading or writing operation. The optical disk drive activates different sets of control circuits in different operation modes. TABLE 1 illustrates the different operation modes of the optical disk drive. The whole operation of an optical disk drive can be mainly divided into two operation modes, e.g. a Seek mode and a Following mode. Furthermore, the Seek mode can be subdivided into two sub-operation modes, e.g. a Sled Follow Lens Kick mode (Short Seek mode) and a Sled Move mode (Long Seek mode). And, the Following mode can be subdivided into two sub-operation modes, e.g. a Data-Reading mode and a Data-Writing mode.
In each sub-operation mode, there are corresponding sets of control circuits operate. The sets of control circuits not being used in this sub-operation mode (or operation mode) can be powered down during the period that the sub-operation mode is executed. TABLE 2 illustrates the sets of control circuits not being used in the respective operation modes.
The sets of control circuits not being used can be powered down in a specific operation mode for saving the power consumption. For example, the RFEQ processor, RFAGC block, TE (DPD or DPP) generator, RFRP generator, RF decoder, PLL, wobble signal generator, ADIP/PPIT/ATIP decoder and ADIP/PPIT processor can be powered down without effecting the normal operation of an optical recordable drive while the optical recordable drive is in the Long Seek Mode.
Please refer to
It should be noted that the warm-up time of circuit depends on the inherent characteristic of the specific circuit. The specific circuit should be powered up before associated operation mode starts in order to maintain the smooth operation of the optical disk drive. The problem of warm-up time of circuit can be overcome by advancing the powering up a predetermined period of time, such as the time interval from A to B. Alternatively, it can be done by counting the remaining tracks for short seek mode, such as the time interval from C to D. Additionally, the warm-up time of circuit can be achieved by counting the remaining steps for long seek mode.
a-4d show an embodiment of detailed structure of logic unit 160. The logic unit 160 can be realized by combining a plurality of logic gates for determining which set of circuits should be powered down according to different power controlling signals. The logic gates of logic unit 160 are arranged in accordance with a predetermined power controlling setting, such as Following Mode Power Control Setting 402 and Seek Mode Power Control Setting 404. The predetermined power controlling setting determines the power states of different sets of circuits in the optical disk drive 10 according to different power controlling signals, such as FollowPD, SeekPD signals, different enable signals etc. For example, if FollowPD signal is in logic “1” state and Read RFEQ PD enable is in logic “1” state, AND gate 4101 will output logic “1” signal to OR gate 4201, OR gate 4201 will output logic “1” signal to AND gate 4123, then AND gate 4123 will output logic “1” signal to OR gate 4223. Finally, OR gate 4223 will output a RFEQ processor PD signal to the RFEQ processor 124 for powering down thereof. Accordingly, any set of circuits can be powered down according to different power controlling signals which are preset in the Following Mode Power Control Setting 402 and Seek Mode Power Control Setting 404. It should be noted that this topology of arrangement of logic gates in logic unit 160 is just one embodiment for exemplifying the detailed structure of logic unit 160. The arrangement of logic gates in logic unit 160 also can be realized in another arrangement of logic gates.
a-5b show a structure of determination rule for determining which power controlling signal should be outputted. For example, a SeekPD signal can be determined according to the logic states of TRON signal, SCSKOK signal and the number of remaining tracks or remaining steps. Similarly, a FollowPD signal also can be determined according to the logic states of TRON signal, SCSKOK signal and a Seek command. In the embodiment of Seek PD signal, for example, if TRON and SCSKOK signal are all in logic “0” state and Stepping motor Long Seek signal is in logic “1” state, the NOR gate 508 and the multiplexer 506 both output logic “1” signal, then the AND gate 510 will output a SeekPD signal to power down corresponding set of circuits. In the embodiment of Follow PD signal, contrarily, if TRON and SCSKOK signal are all in logic “1” state and Seek command is in logic “0” state, the AND gate 512 and inverter 516 both output logic “1” signal, then the AND gate 514 will output a FollowPD signal to power down corresponding set of circuits. If the Seek command is in the logic “1” state, the High-Low element 518 outputs a logic “1” signal and the inventor 516 outputs a logic “0” signal, then the AND gate 514 outputs a logic “0” state signal. In the meantime, the delay unit 520 delays the Seek command for a predetermined period and then inputs the Seek command to the Seek Block 522 to make the TRON and SCSKOK signal all in logic “0” state. The delay unit 520 also outputs the delay Seek command to the High-Low element 516 to make the High-Low element output a logic “0” state signal to the inverter 516. Then the AND gate 512 outputs a logic “0” signal and the inverter 516 outputs logic “1” signal to make the AND gate 514 output a logic “0” signal. Said delay unit 520 delays the seek command for a predetermined time that could be a warm-up time for seeking circuits. It also should be noted that structure of determination rule of power controlling signal can be realized by other structures which are conformed to the spirit of the present invention.
In step S608, the time point for powering down the first set of rest control circuits not being used in the first operation mode can be determined by delaying a predetermined period from the time point of issuing the power up signal to power up the first set of control circuits related to the first operation mode. Therefore, the first set of rest control circuits not being used in the first operation mode are powered down after the predetermined period ends. In other words, the second operation mode is finished when the predetermined period ends. The predetermined period can be predetermined according to the length of warm-up time of first set of control circuits related to the first mode. Alternatively, the time point for powering down the first set of rest control circuits not being used in the first operation mode also can be determined when the power controlling unit 108 receives a signal for indicating that the first operation mode is started.
The power up criterion is predetermined according to the characteristic of different operation modes. For example, the power up criterion can be realized by counting the remaining tracks when a Seek mode is interchanges with a Following mode. The power up criterion is used to power up the next set of control circuits related to the next operation mode in advance due to the warm-up time of related circuits of corresponding operation mode. Further, for another example, the power up criterion can be realized by counting the remaining steps for a step motor of a pick-up head. The remaining steps means how far the pick up head can reach the target position and the operation mode would be changed in the target position. Suppose that the warm-up time of specific set of control circuits is 0.2 ms (minisecond) and a step update rate of step motor is 500 Hz, it means that the specific set of control circuits should be warmed up before last remaining step is transmitted. It should be noted that the power up criterion can be varied according to different characteristic of operation modes.
Consequently, the present invention provides the power saving system and the power saving method applied in an optical disk drive. The power saving system and method of the present invention are adapted for powering down the sets of control circuits not being used during a specific operation mode of the optical disk drive without effecting the normal operation of the optical disk drive. Therefore, the power saving system and the power saving method according to the present invention are capable of efficiently reducing the power consumption of the optical disk drive.
As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrative rather than limiting of the present invention. It is intended that they cover various modifications and similar arrangements be included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.
