Patent Application
20090300395
This Application claims priority of Taiwan Patent Application No. 097107856, filed on Mar. 6, 2008, the entirety of which is incorporated by reference herein.
1. Field of the Invention
The invention relates to a power saving circuit, and more particularly, to a power saving circuit applied in computer systems.
2. Description of the Related Art
In a conventional computer system, all peripheral devices will be waked up when powered on. In other words, all controller chips corresponding to the peripheral devices will also be activated for operation.
However, users may not utilize all of the computer peripheral devices all the time or users may only utilize some computer peripheral devices during a specific time period. The peripheral devices which are not frequently used and controller chips corresponding thereto, however, still consume power, thus causing the conventional computer systems to inefficiently utilize and waste power.
Five ACPI (Advanced Configuration and Power Interface) states, such as S0, S1, S3, S4 and S5 states, are commonly utilized in computer systems. However, computer systems can only normally operate in the S0 state, while computer systems enter a sleep state in the S1-S5 states. Thus, while computer system power can be saved, computer system operation is inconvenient.
A power saving method for use in an electronic system is disclosed, wherein the electronic system comprises at least one controller respectively connecting to at least one peripheral device. The method comprises the following steps. First, whether any of the peripheral devices is coupled to the respective controllers is detected. The controller is powered off by the electronic system when no peripheral device is coupled to the respective controllers. A device configuration table is updated and next peripheral device is continuously detected.
A power saving system for determining whether a peripheral device being coupled thereto for power saving control is further disclosed, comprising a system chip, a controller coupled to the system chip and a switch. When the system detects that the controller is not connect to the peripheral device, the GPIO port sends a control signal to the switch such that the switch turns off a power supplied to the controller for power saving.
The invention can be more fully understood by reading the subsequent detailed description and examples with reference to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
In one embodiment of the invention, each of the switches 322, 332, 342 and 352 is coupled between a supplied power Vdd and the corresponding controller, and each switch is turned on or off according to a GPIO signal. For example, the switch 322 is turned on or off according to a GPIO signal GPIO1. When the device 324 is connected to the controller 320 through the connector, the GPIO signal GPIO1 is at a high voltage level such that the NMOS transistor 322 is turned on and the LAN controller 320 is activated due to reception of the supplied power Vdd. The South-Bridge chip 310 thus connects to the LAN controller 320 through the PCI interface and the LAN controller 320 and starts transmitting data to/receiving data from therebetween. When the device 324 is not connected to the South-Bridge chip 310 through the connector and the LAN controller 320, the AP will issue a GPIO signal GPIO1 to turn off the switch 322 thereby powering off the LAN controller 320 for reducing power consumption.
When the device 334 is not connected to the South-Bridge chip 310 through the connector and the Card Bus controller 330, the AP will issue a GPIO signal GPIO2 to turn off the switch 332 thereby powering off the Card Bus controller 330 for reducing power consumption. Similarly, when the 1394 controller 340 and the ESATA controller 350 are not being used, i.e. both the peripheral devices 344 and 354 are not connected to the controllers 340 and 350, the AP will issue GPIO signals GPIO3 and GPIO4 to turn off the switches 342 and 352 respectively thereby power off the 1394 controller 340 and the ESATA controller 350 for reducing power consumption. It is to be understood that although the switches 322, 332, 342 and 352, in this embodiment, are implemented by NMOS transistors, the invention is not limited thereto. In other words, the switches can be implemented by any other devices or elements with similar functionality.
In summary, compared with conventional computer systems where all controllers of peripheral devices are activated when powered up, specific controllers, according to the invention, is activated only when a corresponding peripheral device is connected to the system chip through the connector and the controller for avoiding unnecessary power consumption. Moreover, scanning of all of the peripheral devices may be performed while the computer system is being powering up or it may be performed only when a trigger event occurs.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to the skilled in the art). Therefore, the scope of the appended claims should be accorded to the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 97107856 | Jun 2008 | TW | national |
