Patent Application
20230314895
This application claims priority under 35 USC 119 from Japanese Patent Application No. 2022-063037, filed on Apr. 5, 2022, the disclosure of which is incorporated by reference herein.
The present disclosure relates to a power source device, an electrophoresis device, a power source device control method, and an electrophoresis device control method.
Japanese Patent No. 6856495, discloses an electrophoresis device. The electrophoresis device includes a power source device, and the power source device generates a voltage to induce electrophoresis (hereafter referred to as “electrophoresis voltage”), and the electrophoresis voltage is applied to a capillary in the electrophoresis device.
The power source device of Japanese Patent No. 6856495, applies the electrophoresis voltage in a direction defined by internal connections of the power source device. There is a demand for technology in a single power source device that enables a polarity of the electrophoresis voltage (direction of voltage application) to be selected for both one direction and a reverse direction.
The present disclosure provides a power source device that may enable selection of both one direction and a reverse direction in relation to a polarity of an electrophoresis voltage, and to an electrophoresis device including such a power source device, a method to control such a power source device, and a method to control such an electrophoresis device.
A first aspect of the present disclosure is a power source device configured for an electrophoresis device employing a measurement tool including a capillary, the power source device including: a high voltage generation circuit configured to generate a voltage for electrophoresis; a first external terminal and a second external terminal configured to apply the electrophoresis voltage to the capillary; a polarity switching circuit including a first internal conductor connected to the high voltage generation circuit and a second internal conductor, the polarity switching circuit being configured to selectably apply a potential difference between the second internal conductor and the first internal conductor across the first external terminal and the second external terminal by application with either a forward direction polarity or a reverse direction polarity; and a switching control circuit configured to control polarity switching of the polarity switching circuit to select either one of application with the forward direction polarity or application with the reverse direction polarity.
In a second aspect of the present disclosure, in the first aspect, the polarity switching circuit may include a forward direction switch pair of a first forward direction switch and a second forward direction switch, and a reverse direction switch pair of a first reverse direction switch and a second reverse direction switch; the first forward direction switch may be connected between the first internal conductor and the first external terminal; the second forward direction switch may be connected between the second internal conductor and the second external terminal; the first reverse direction switch may be connected between the first internal conductor and the second external terminal; the second reverse direction switch may be connected between the second internal conductor and the first external terminal; and the switching control circuit may be configured to control the polarity switching circuit so as to make either one of the forward direction switch or the reverse direction switch exclusively conductive.
In a third aspect of the present disclosure, in the second aspect, each of the first forward direction switch, the second forward direction switch, the first reverse direction switch, and the second reverse direction switch, may include an input side that receives a switching signal according to the forward direction polarity or the reverse direction polarity and an output side that operates in response to the switching signal; and the output side may be electrically insulated from the input side.
In a fourth aspect of the present disclosure, in the second aspect or the third aspect, the switching control circuit may include an interval generation circuit configured to generate a signal for switching between the forward direction switch pair and the reverse direction switch pair, so as to provide an interval of time during which both the forward direction switch pair and the reverse direction switch pair are nonconductive, in a case in which switching between one and the other of the forward direction switch pair and the reverse direction switch pair.
In a fifth aspect of the present disclosure, in any one of the first aspect to the fourth aspect, the switching control circuit may include an input that receives a polarity signal that defines the forward direction polarity or the reverse direction polarity; and the switching control circuit may include a hold circuit configured to hold a polarity state as indicated by the polarity signal.
In a sixth aspect of the present disclosure, in the fifth aspect, the polarity signal may be generated based on an operation mode designation input through an input device of the electrophoresis device.
In a seventh aspect of the present disclosure, in the fifth aspect or the sixth aspect, the power source device may further include a voltage detection circuit connected to an output of the high voltage generation circuit, the voltage detection circuit being configured to generate a detection signal indicating voltage generation or non-generation in the high voltage generation circuit; the switching control circuit may include an inhibit circuit that receives the detection signal and the polarity signal; the hold circuit may be connected to an output of the inhibit circuit; and the inhibit circuit may generate an output value that holds the polarity state of the hold circuit irrespective of the polarity signal, in a case in which the detection signal indicates that the high voltage generation circuit is performing voltage generation operation, and generates an output value corresponding to a value of the polarity signal, in a case in which the detection signal indicates that the high voltage generation circuit is not performing voltage generation operation.
In an eighth aspect of the present disclosure, in any one of the first aspect to the seventh aspect, the high voltage generation circuit may include a generation circuit configured to generate a voltage, and an amplification circuit configured to amplify the voltage generated by the generation circuit and output the electrophoresis voltage; and the amplification circuit may include a Cockcroft-Walton circuit.
In a ninth aspect of the present disclosure, in any one of the first aspect to the eighth aspect, the polarity switching circuit may further include a current detection circuit to receive a current from the capillary through the polarity switching circuit; and the current detection circuit may be connected to the second internal conductor.
A tenth aspect of the present disclosure is an electrophoresis device that employs a measurement tool including a capillary, the electrophoresis device including: a power source device configured to generate an electrophoresis voltage, wherein the power source device includes a first external terminal and a second external terminal configured to apply the electrophoresis voltage to the capillary, and is configured to selectably apply the electrophoresis voltage across the first external terminal and the second external terminal by application with either a forward direction polarity or a reverse direction polarity; and an input device configured to receive designation of an operation mode indicting either the forward direction polarity or the reverse direction polarity.
An eleventh aspect of the present disclosure is a method of controlling a power source device of an electrophoresis device employing a measurement tool including a capillary, the method including: connecting an output of a high voltage generation circuit of the power source device to either one of a first external terminal or a second external terminal of the power source device according to a selectable voltage polarity indicating either one of a forward direction polarity or a reverse direction polarity in the power source device; and operating the high voltage generation circuit after the output of the high voltage generation circuit has been connected to either one of the first external terminal or the second external terminal, and applying an electrophoresis voltage from the high voltage generation circuit to the capillary of the measurement tool set up in the electrophoresis device through the first external terminal or through the second external terminal.
A twelfth aspect of the present disclosure is a method for controlling an electrophoresis device, the method including: preparing an electrophoresis device employing a measurement tool including a capillary, wherein the electrophoresis device is an electrophoresis device prepared including a power source device and an input device; receiving, through the input device, an instruction designating a selectable voltage polarity indicating either one of one of a forward direction polarity or a reverse direction polarity in the power source device; and performing setting of the voltage polarity in the power source device according to the instruction and applying an electrophoresis voltage according to the set voltage polarity to the capillary of the measurement tool set up in the electrophoresis device.
According to the above aspects, the present disclosure may provide the power source device that enables selection of both one direction and a reverse direction in relation to a polarity of an electrophoresis voltage, and to a method to control such a power source device, an electrophoresis device including such a power source device, and a method to control such an electrophoresis device.
Exemplary embodiments will be described in detail based on the following figures, wherein:
Description follows regarding an exemplary embodiment for implementing the present disclosure, with reference to the drawings.
As can be seen from
The electrophoresis device 1 is an analysis device capable of implementing capillary electrophoresis, and this analysis device is capable of measuring or analyzing a sample in a measurement tool such as, for example, a sample 40 electrophoresing through a capillary 4 of a microchip 2, using capillary electrophoresis. More specifically, the sample 40 electrophoreses inside the capillary 4 of the microchip 2. An example of a measurement tool of the present disclosure is illustrated as the microchip 2. The microchip 2 includes the sample 40 containing a migration body 44 in a state in which current flows sufficiently. The sample 40 encompasses a sample 40 containing the migration body 44, or a sample 40 containing a solution of a migration solution diluted with a diluent (a solution state migration body 44). The sample 40 may be diluted in a case in which the sample 40 needs to be diluted for analysis.
The microchip 2 includes the capillary 4 serving as a flow path, an introduction reservoir 6, and a discharge reservoir 8. The sample 40 to be subjected to analysis and the migration body 44 are introduced into the introduction reservoir 6. The migration solution (the migration body 44) function as a buffer in capillary electrophoresis. An example of the migration solution (the migration body 44) is 100 mM malic acid - arginine buffer (pH 5.0) + 1.5% sodium chondroitin sulfate C, and an example of the sample 40 is blood. The microchip 2 is a disposable type of chip and is, for example, intended to be discarded after analysis has been performed once or a specific number of times. The microchip 2 is, for example, formed from silica.
The capillary 4 contains a sample to induce electrophoresis in for analysis using capillary electrophoresis. In order to implement capillary electrophoresis, the capillary 4 has a tubular shape extending in one direction, and examples of dimensions thereof are given below. A cross-section of the tubular shaped profile is, for example, a circular shape having a diameter of from 25 µm to 100 µm, or is preferably a rectangular shape having sides of from 25 µm to 100 µm. Although a length of the tubular shaped profile is preferably, for example, about 30 mm, there is no limitation thereto.
The discharge reservoir 8 is positioned at the downstream side of the capillary 4 in the migration direction under capillary electrophoresis. The sample 40 and the migration body 44 that have electrophoresed through the capillary 4 and completed analysis are stored in the discharge reservoir 8. The already analyzed sample 40 and migration body 44 in the discharge reservoir 8 are, for example, discharged from the discharge reservoir 8 using a discharge nozzle (omitted in the drawings) and a suction pump (omitted in the drawings). The discharge nozzle (omitted in the drawings) is attached to the discharge reservoir 8, or the suction pump (omitted in the drawings) is employed for discharge through the discharge nozzle (omitted in the drawings).
A first external terminal 70a and a second external terminal 70b are respectively connected to the first electrode 22 and the second electrode 24. The first electrode 22 and the second electrode 24 are, for example, rod shaped electrodes made from copper (Cu) with a cross-sectional diameter of from 0.8 mm to 1.0 mm. The first electrode 22 is immersed in the introduction reservoir 6 and the second electrode 24 is immersed in the discharge reservoir 8 so as to enable a voltage to be applied to the capillary 4. In this exemplary arrangement the first electrode 22 and the second electrode 24 are able to apply a voltage to the capillary 4, the sample 40 is filled into the capillary 4 of the microchip 2 so as to be able to migrate, and the introduction reservoir 6 and the discharge reservoir 8 are positioned at one end and the other end of the capillary 4, respectively. However, the placement of the first electrode 22 and the second electrode 24 is not limited thereto.
The analysis device 26 is employed, for example, to execute light absorption measurement and, as illustrated in
The light source device 30 is configured so as to generate light of a wavelength according to the analysis target. The illumination device 28b is, for example, coupled to the light emitting device 28a through a waveguide device configured by an optical fiber, and the waveguide device shines the light from the light emitting device 28a on part of the capillary 4 as illumination light. The light emitting device 28a is configured so as to generate light employed for light absorption measurement and, for example, may include a laser device. The light emitting device 28a may generate light at a wavelength of 415 nm in a case in which, for example, a concentration of a hemoglobin variant of hemoglobin A1c in blood is being analyzed, however, the wavelength of the light emitting device 28a is not limited thereto. The detection device 34 receives light from the capillary 4 and generates an electrical signal. The photoreceptor 32a is connected to the photoelectric converter 32b through a waveguide device such as, for example, an optical fiber. The detection device 34 performs processing on the electrical signal from the photoelectric converter 32b.
The control device 10 controls operation of each section of the electrophoresis device 1, and performs a cycle of control so as to implement analysis with the electrophoresis device 1. As illustrated in
As illustrated in
The illumination device 28b illuminates the illumination light onto this part of the capillary 4, and some of this illuminated light is absorbed by the specific component. The photoreceptor 32a detects non-absorbed light as transmitted light. The detection device 34 receives a signal indicating an amount of light (amount transmitted) as detected by the photoelectric converter 32b, and detects a concentration of the specific component of the sample 40 using the principals of light absorption measurement based on an amount of light of the illumination light and an amount of light of the transmitted light.
The electrophoresis device 1 includes the power source device 20 configured so as to generate the electrophoresis voltage, and an input device 90 configured so as to receive a designation of operation mode indicating either forward direction polarity or reverse direction polarity. The power source device 20 includes the first external terminal 70a and the second external terminal 70b configured so as to apply the electrophoresis voltage to the capillary 4. The power source device 20 enables selection of application of the electrophoresis voltage across the first external terminal 70a and the second external terminal 70b with either the forward direction polarity (for example, making the potential of the first external terminal 70a a high positive polarity, and making the potential of the second external terminal 70b a low negative polarity), or with the reverse direction polarity (for example, making the potential of the first external terminal 70a a low negative polarity, and making the potential of the second external terminal 70b a high positive polarity). The electrophoresis device 1 is accordingly able to designate an operation mode that defines either the forward direction polarity or the reverse direction polarity, and to perform electrophoresis measurement in this operation mode. Namely, electrophoresis can be performed on the sample 40 as designated by one operation mode from out of voltage application in two polarity directions, these being the forward direction polarity and the reverse direction polarity. The electrophoresis device 1 is furthermore equipped with the light source device 30 provided so as to illuminate light onto the capillary 4 and with the detection device 34 optically coupled to the light source device 30.
The power source device 20 is, broadly speaking, configured to generate a voltage of several kilovolts, for example a voltage of about 1.5 kV, for generating the voltage needed for capillary electrophoresis in the electrophoresis device 1 employing the measurement tool including the capillary 4. The power source device 20 is equipped with the first external terminal 70a serving as an output terminal and the second external terminal 70b serving as an input terminal.
Detailed explanation follows regarding the power source device 20.
As illustrated in
The voltage generation section 50a includes a high voltage generation circuit 53 and furthermore, for example, may include an input control circuit 50, an enable circuit 52, an output protection circuit 58, an output voltage control circuit 60, a current detection circuit 62, and a voltage detection circuit 64. The high voltage generation circuit 53 is configured so as to generate a voltage for electrophoresis (hereafter referred to as “electrophoresis voltage”), and in the present exemplary embodiment may also include an inverter transformer circuit 54 serving as a generation circuit, and a Cockcroft-Walton circuit 56 (hereafter referred to as “CCW circuit”) serving as an amplification circuit. In the power source device 20, the high voltage generation circuit 53 is able to take a voltage supplied from the generation circuit for generating a voltage and amplify this voltage in an amplification circuit, so as to generate a voltage for use in electrophoresis measurement.
The first external terminal 70a and the second external terminal 70b are configured so as to apply the electrophoresis voltage to the capillary 4 and are provided to the power source device 20. More specifically, the voltage switching section 50b is connected to the microchip 2 through the first external terminal 70a and the second external terminal 70b. The voltage generation section 50a of the power source device 20 includes a second output electrode 68, a third output electrode 74, a second input electrode 82, a third input electrode 84, and a fourth input electrode 86, and is connected to the control device 10 through these electrodes.
The voltage switching section 50b includes a polarity switching circuit 51 and a switching control circuit 55, with the polarity switching circuit 51 including a first internal conductor 80a (output) and a second internal conductor 80b (input). The first internal conductor 80a is connected to the high voltage generation circuit 53, and the second internal conductor 80b is connected to the current detection circuit 62 configured to receive current from the capillary 4 through the polarity switching circuit 51. The power source device 20 enables the current from the capillary 4 to be provided to the current detection circuit 62 for both, the forward direction polarity or the reverse direction polarity, according to the polarity switching circuit 51.
The switching control circuit 55 (the voltage switching section 50b) provides a switching signal to a control input 80e so as to perform switching of the polarity switching circuit 51. The polarity switching circuit 51 is able to select to apply a potential difference between the first internal conductor 80a (output) and the second internal conductor 80b (input) across the first external terminal 70a and the second external terminal 70b, in either the forward direction polarity or the reverse direction polarity. The switching control circuit 55 controls the polarity switching of the polarity switching circuit 51, and selects application of the electrophoresis voltage in either one of the forward direction polarity or the reverse direction polarity.
In the power source device 20, switching the polarity switching circuit 51 enables switching between supply of the electrophoresis voltage from the high voltage generation circuit 53 to the first external terminal 70a through the first internal conductor 80a (for example application with the forward direction polarity), or supply of the voltage from the high voltage generation circuit 53 to the second external terminal 70b through the first internal conductor 80a (for example application with the reverse direction polarity that is the opposite direction to the forward direction polarity). The switching control circuit 55 controls the polarity switching circuit 51 so as to select either one of application with the forward direction polarity or application with the reverse direction polarity. According to this switching, the second internal conductor 80b receives current from the capillary 4 either through the first external terminal 70a or through the second external terminal 70b. The first external terminal 70a and the second external terminal 70b are spaced apart from each other so as to maintain dielectric strength against the electrophoresis voltage from the high voltage generation circuit 53. The polarity switching circuit 51 includes a first external conductor 80c and a second external conductor 80d respectively connected to the first external terminal 70a and the second external terminal 70b.
As illustrated in
In the power source device 20, one out of the forward direction switch pair 71 or the reverse direction switch pair 72 being conductive enables the polarity switching circuit 51 to exclusively switch between application with the forward direction polarity or application with the reverse direction polarity. Due to being exclusively conductive, the forward direction switch pair 71 and the reverse direction switch pair 72 can be prevented from transitionally being conductive at the same time during a transition period in a case in which switching between the forward direction switch pair 71 and the reverse direction switch pair 72.
In the power source device 20, the input side 73a and the output side 73b are electrically insulated from each other in each of the first forward direction switch 71a, the second forward direction switch 71b, the first reverse direction switch 72a, and the second reverse direction switch 72b. By this insulation, the high voltage of the output side 73b is insulated and isolated from the input side 73a that receives signals having a lower voltage level than this high voltage.
The input side 73a receives a switching signal according to either the forward direction polarity or the reverse direction polarity, and the output side 73b is able to switch the switch 73c in response to such a switching signal. More specifically, the switch device 73 includes a drive element 73d (for example a transistor) to drive the input side 73a in response to the switching signal. A diode 73e is connected between the electrodes of the input side 73a to prevent reverse flow of the drive current. The output side 73b is electrically insulated from the input side 73a, and is also, for example, mechanically and/or magnetically coupled to the input side 73a.
The switch device 73 is not limited to being a relay device, and a voltage control device or a current control device may be employed therefor.
The power source device 20 is accordingly able to perform stable switching of the polarity of the application voltage during the period in which both the forward direction switch pair 71 and the reverse direction switch pair 72 are nonconductive. The interval generation circuit 75 includes an input 75a, a first output 75b, and a second output 75c. The input 75a receives a selection signal SSEL to place one pair out of the forward direction switch pair 71 or the reverse direction switch pair 72 in a conducting state (closed state) and the other pair in a nonconductive state (open state). The first output 75b provides a switch selection signal S1SEL to select the forward direction switch pair 71 of the polarity switching circuit 51. The second output 75c provides a switch selection signal S2SEL to select the reverse direction switch pair 72 of the polarity switching circuit 51. The first output 75b and the second output 75c are equivalent to the control input 80e illustrated in
More specifically, the interval generation circuit 75 includes plural logic gates such as, for example four logic gates (in the present exemplary embodiment a first logic gate 76, a second logic gate 77, a third logic gate 78, and a fourth logic gate 79).
The first logic gate 76 receives the selection signal SSEL (having a logic value of “H” or “L”), and drives a selective delay circuit DEL. The second logic gate 77 receives the selection signal SSEL and drives the selective delay circuit DEL. An output 76a of the first logic gate 76 is connected to an input 79b of the fourth logic gate 79 through the selective delay circuit DEL. An output 77a of the second logic gate 77 is connected to an input 78b of the third logic gate 78 through the selective delay circuit DEL. The selective delay circuit DEL is able to generate a selective delay in one transition from out of two signal transitions (from H to L or from L to H), and is configured by a CR delay circuit including a resistance element Res1, a diode DD1 connected in parallel to the resistance element Res1, and a capacitor element CP1 that is connected to one end of the parallel connected resistance element Res1 and diode DD1.
In the present exemplary embodiment, the first logic gate 76 includes, for example an exclusive-OR gate, with the exclusive-OR gate being provided with an output 76a, an input 76b, and an input 76c. The input 76c is connected to the input 75a of the interval generation circuit 75 through a resistance element Res0. The output 76a is connected to the selective delay circuit DEL. The input 76b is connected to the input 75a of the interval generation circuit 75, and receives an “L” level signal both for the selection signal SSEL at a logic value “H” and “L”. The input 76c is connected to a low potential power source line LV. The input 75a of the interval generation circuit 75 is connected to the low potential power source line LV through the resistance element Res0.
The second logic gate 77 includes, for example, an exclusive-OR gate, and this exclusive-OR gate is provided with an output 77a, an input 77b, and an input 77c. The output 77a is connected to the selective delay circuit DEL. The input 77b is connected (directly connected) to the input 75a of the interval generation circuit 75. The input 77c is connected to a high potential power source line HV.
The third logic gate 78 includes, for example, an exclusive-OR gate having an output 78a, an input 78b, and an input 78c. The output 78a is connected to the first output 75b of the interval generation circuit 75. The input 78b is connected to the output 77a of the second logic gate 77 through the selective delay circuit DEL, and receives a selective delay signal from the output 77a. The input 78c is connected to the low potential power source line LV.
The fourth logic gate 79 includes, for example, an exclusive-OR gate having an output 79a, an input 79b, and an input 79c. The output 79a is connected to the second output 75c of the interval generation circuit 75. The input 79b is connected to the output 76a of the first logic gate 76 through the selective delay circuit DEL, and receives a selective delay signal from the output 76a. The input 79c is connected to the low potential power source line LV.
More specifically, the mode control circuit 81 includes a hold circuit 83 and an inhibit circuit 85. The hold circuit 83 holds the polarity state indicated by the polarity signal SPOL. The inhibit circuit 85 inhibits the hold circuit 83 from being changed according to transition of the polarity signal SPOL during operation of the high voltage generation circuit 53. The inhibit circuit 85 allows the hold circuit 83 to be changed according to transition of the polarity signal SPOL while the high voltage generation circuit 53 is stopped. While the high voltage generation circuit 53 is stopped, the inhibit circuit 85 operates as a set-reset circuit to generate a signal that causes a set-reset operation to occur in the hold circuit 83 to change the polarity state of the hold circuit 83 according to change in the polarity signal SPOL.
In the present exemplary embodiment, the hold circuit 83 includes an RS latch circuit of two inputs and two outputs. The latch circuit includes two NAND gates 83a, 83b and changes holding content according to negate set signal and negate reset signal.
The inhibit circuit 85 includes two logic gates such as, for example a first NAND gate 85a and a second NAND gate 85b. The first NAND gate 85a has at least two inputs, and more specifically has a first input to receive the polarity signal SPOL and a second input to receive the forbid signal SFBD that forbids mode transition. The second NAND gate 85b has at least two inputs, and more specifically has a first input to receive the forbid signal SFBD that forbids mode transition and a second input to receive a signal output from the first NAND gate 85a. The outputs of the first NAND gate 85a and the second NAND gate 85b are connected to respective inputs of the RS latch circuit.
In the power source device 20, the inhibit circuit 85 enables a reduction in the possibility of unintentional change to the polarity state of the hold circuit 83. Each of the NAND gates 83a, 83b may have hysteresis characteristics for each individual input. Each of the NAND gates 85a, 85b may also have hysteresis characteristics for each individual input.
The polarity signal SPOL is generated based on an operation mode designation, input through the input device 90 of the electrophoresis device 1 (see
The hysteresis comparator 89a includes an operational amplifier AMP1, and resistance elements Res2, Res3, Res4, Res5, Res6. The resistance element Res2 is connected between the input 87a and an inverting input of the operational amplifier AMP1. The resistance element Res3 is connected between the non-inverting input and the output of the operational amplifier AMP1. The resistance element Res4 is connected between the non-inverting input of the operational amplifier AMP1 and a low potential power source line (ground). The resistance element Res5 is connected between the non-inverting input of the operational amplifier AMP1 and a high potential power source line. The resistance element Res6 is connected between the output of the operational amplifier AMP1 and an input of a Schmitt logic gate 89b. The output of the Schmitt logic gate 89b is connected to the output 87b and a capacitor element CAP.
Providing the hysteresis comparator 89a at an initial stage of the forbid signal generation circuit 87 can prevent oscillation of output. The Schmitt logic gate 89b is provided at a later stage of the forbid signal generation circuit 87.
At step S101, the electrophoresis device 1 employing a measurement tool including a capillary 4 is prepared. The electrophoresis device 1 includes a power source device 20 and an input device 90. Preparation of the electrophoresis device 1 encompasses, for example, being assigned the electrophoresis device 1, manufacturing the electrophoresis device 1, borrowing the electrophoresis device 1, and the like.
At step S102, an instruction designating a selectable voltage polarity indicating either one of forward direction polarity or reverse direction polarity in the power source device 20 is received through the input device 90.
At step S103, the voltage polarity in the power source device 20 is set according to the received instruction. Further, at step S103, the electrophoresis voltage is applied to the measurement tool capillary 4 that has been set up in the electrophoresis device 1 by application through the first external terminal 70a and the second external terminal 70b, according to the voltage polarity set. The setting of the voltage polarity according to the received instruction may indicate the forward direction polarity or may indicate the reverse direction polarity.
According to the method 100, in the power source device 20, the electrophoresis voltage can be applied according to the selectable voltage polarity set to indicate either one of the forward direction polarity or the reverse direction polarity. Prior to operating the high voltage generation circuit 53, the output of the high voltage generation circuit 53 is connected to either one of the first external terminal 70a or the second external terminal 70b, according to the selectable voltage polarity in relation to the application voltage to the capillary 4. The capillary 4 that has been set up in the electrophoresis device 1 receives the electrophoresis voltage through the first external terminal 70a and the second external terminal 70b.
The method 100 for controlling the electrophoresis device 1 may, for example, further include the following steps.
In step S104, the operation of the high voltage generation circuit 53 is stopped after the voltage from the high voltage generation circuit 53 has been applied to the capillary 4.
In step S105, a separate instruction related to voltage polarity is received through the input device 90 after operation of the high voltage generation circuit 53 has been stopped.
At step S106, the voltage polarity in the power source device 20 is set according to the separate instruction. The electrophoresis voltage is applied to the measurement tool capillary 4 that has been set up in the electrophoresis device 1 according to the set voltage polarity by application through the first external terminal 70a and the second external terminal 70b of the power source device 20. The setting of the voltage polarity according to the received instruction may indicate the forward direction polarity or may indicate the reverse direction polarity.
According to the method 100, the operation of the high voltage generation circuit 53 can be stopped in a case in which the separate instruction related to the voltage polarity is received. This separate instruction may be the same as the previous instruction, or may be different thereto.
At step S111, the output of the high voltage generation circuit 53 of the power source device 20 is connected to either one of the first external terminal 70a or the second external terminal 70b of the power source device 20 according to the selectable voltage polarity indicating either one of the forward direction polarity or the reverse direction polarity in the power source device 20.
At step S112, the high voltage generation circuit 53 is operated after the output of the high voltage generation circuit 53 has been connected to either one of the first external terminal 70a or the second external terminal 70b. The electrophoresis voltage from the high voltage generation circuit 53 is applied to the measurement tool capillary 4 that has been set up in the electrophoresis device 1 through the first external terminal 70a or the second external terminal 70b.
In the method 110, prior to operating the high voltage generation circuit 53, the output of the high voltage generation circuit 53 is connected to either one of the first external terminal 70a or the second external terminal 70b according to the selectable voltage polarity of the application voltage to the capillary 4. The capillary 4 set up in the electrophoresis device 1 receives the electrophoresis voltage through the first external terminal 70a and the second external terminal 70b.
Detailed description follows regarding the power source device 20, with reference again to
As illustrated in
The power source device 20 includes a function to generate the application voltage that induces a current of a prescribed magnitude needed for measurement to flow in the microchip 2 according to an enable signal SENB received from the control device 10 through the second input electrode 82. The power source device 20 includes a function to change the input voltage to the inverter transformer circuit 54 based on the magnitude of a current control signal SICNT corresponding to the magnitude of an assumed voltage that is assumed to be applied to the microchip 2. Changing the input voltage is performed in an initial process of voltage application to induce electrophoresis of the sample 40 in the capillary 4.
As illustrated in
In the enable circuit 52, a base of the transistor Tr1 of a common emitter circuit is connected to the second input electrode 82 through a resistance element R1, and is connected to the emitter of the transistor Tr1 through a resistance element R2. The collector of the transistor Tr1 is connected to a power source line of a drive voltage Vdd through a resistance element R3. The gate of the transistor Tr2 is connected to a common node between the collector of the transistor Tr1 and the resistance element R3, and as a result thereof the gate of the transistor Tr2 is connected to the source of the transistor Tr2 through the resistance element R3.
The input control circuit 50 compares a magnitude of a current monitoring signal SIMON input through the third input electrode 84 to the current control signal SICNT input through the fourth input electrode 86. Next, the input control circuit 50 controls the magnitude of an input voltage input to the inverter transformer circuit 54 such that the magnitude of the current monitoring signal SIMON matches the magnitude of the current control signal SICNT. The current monitoring signal SIMON is changed in response to this control.
More specifically, the input control circuit 50 includes operational amplifiers Ap1, Ap2, resistance elements R4 to R13, capacitor elements C1, C2, and transistors Tr3, Tr4, Tr5. Each of the transistors Tr3, Tr5 may be an npn-type bipolar transistor, and the transistor Tr4 may be an N-channel type MOSFET.
The non-inverting input of the operational amplifier Ap1 is connected to the fourth input electrode 86, and receives the current control signal SICNT through the fourth input electrode 86. The inverting input and the output of the operational amplifier Ap1 are connected together so as to configure a voltage follower. The output of the operational amplifier Ap1 is connected to the non-inverting input of the operational amplifier Ap2 through a resistance element R9.
The inverting input of the operational amplifier Ap2 is connected to the third input electrode 84 through a resistance element R8, and receives the current monitoring signal SIMON through the third input electrode 84. The output of the operational amplifier Ap2 is connected to the inverting input of the operational amplifier Ap2 through a resistance element R10 and a capacitor element C1 that are connected in parallel. Such connection enables the operational amplifier Ap2 to be configured as an inverting amplification circuit. The output of the inverting amplification circuit, and more specifically the output of the operational amplifier Ap2, is connected to a base of the transistor Tr5 through the resistance element R11. The emitter of the transistor Tr5 is connected to the low potential power source line (ground) through a capacitor element C2 and a resistance element R13 that are connected in series. Moreover, the base of the transistor Tr5 is connected to the emitter of the transistor Tr5 through a resistance element R12. The collector of the transistor Tr5 is connected to the drain of the transistor Tr2 of the enable circuit 52.
The base of the transistor Tr3 of a common emitter circuit is connected to the second input electrode 82 through the resistance element R4, and the base of the transistor Tr3 is connected to the emitter of the transistor Tr3 through the resistance element R5. The collector of the transistor Tr3 is connected to the high potential power source line Vcc through the resistance element R6, and is connected to the gate of the transistor Tr4. The drain of the transistor Tr4 is connected to the output of the operational amplifier Ap1 through the resistance element R9, and is directly connected to the non-inverting input of the operational amplifier Ap2. The non-inverting input of the operational amplifier Ap2 is connected to the low potential power source line (ground) through the resistance element R7. The base of the transistor Tr4 is connected to the low potential power source line (ground).
The input of voltage at the primary side of the inverter transformer circuit 54 is connected to the output of the input control circuit 50. The inverter transformer circuit 54 raises the input voltage of direct current (DC) input from the input control circuit 50, and also generates a raised voltage of alternating current (AC) and outputs this to the CCW circuit 56.
The CCW circuit 56 amplifies the voltage output from the inverter transformer circuit 54 and rectifies this into a direct current voltage and outputs the direct current voltage. The CCW circuit 56 includes plural capacitor elements (for example, capacitor elements C3 to C8) and plural diodes (for example, diodes D1 to D6). More specifically, the connections thereof configure a 3 stage CCW circuit that outputs a voltage of a magnitude that is six times the peak input voltage of the voltage that was input. This voltage is the actual application voltage.
As illustrated in
As illustrated in
The voltage output from the output protection circuit 58 is applied to the microchip 2. The output voltage control circuit 60 monitors the output voltage of the CCW circuit 56, and in a case in which the magnitude of this output voltage is a prescribed magnitude or greater, suppresses the output voltage from becoming an excessive voltage by interrupting current input to the primary side of the inverter transformer circuit 54.
The output voltage control circuit 60 includes the operational amplifier Ap3, the resistance elements R14 to R17, the capacitor element C9, and the transistors Tr6, Tr7. The transistor Tr6 may be an npn-type bipolar transistor, and the transistor Tr7 may be an N-channel type MOSFET.
The inverting input of the operational amplifier Ap3 is connected to a reverse direction diode DI1 and to a voltage divider circuit between the CCW circuit 56 and the low potential power source line (ground). More specifically The inverting input of the operational amplifier Ap3 is connected to a voltage divider circuit that provides a divided voltage divided by resistance elements R18, R19 that are connected in series (divided voltage of the output voltage of the CCW circuit 56). In the present exemplary embodiment, due to making the resistance value of the resistance element R18 high and the resistance value of the resistance element R19 low (at least lower than that of the resistance element R18), the voltage value of the voltage input to the non-inverting input of the operational amplifier Ap3 is made lower. As a specific example, a resistance value of the resistance element R18 may be 100 MΩ, and the resistance value of the resistance element R19 may be 100 kΩ.
The non-inverting input of the operational amplifier Ap3 is connected to a reference voltage source. The reference voltage source includes a voltage divider circuit that provides a voltage from dividing the high potential power source line Vcc, and a capacitor element C9 connected to the output of the voltage divider circuit. The voltage divider circuit, for example, includes resistance elements R14 and R15 that are connected in series. The magnitude of the voltage resulting from dividing the voltage of the high potential power source line Vcc may be matched to an output voltage of the voltage divider circuit connected between the CCW circuit 56 and the low potential power source line (ground).
The output of the operational amplifier Ap3 is connected to the collector of the transistor Tr6 and the gate of the transistor Tr7 of a common emitter circuit through the resistance element R16. The source of the transistor Tr7 is connected to the low potential power source line (ground) through the resistance element R17. The base of the transistor Tr6 is connected to the source of the transistor Tr7. Such connection means that the transistor Tr6 and the resistance element R17 function as a current control circuit to control current input to the primary side of the inverter transformer circuit 54. The drain of the transistor Tr7 is connected to the low potential side line of the primary side of the inverter transformer circuit 54.
The current detection circuit 62 receives current that flowed in the microchip 2 through the second internal conductor 80b in a case in which the application voltage has been applied through the first external terminal 70a. The current detection circuit 62 monitors the current flow and provides the current monitoring signal SIMON corresponding to the magnitude of this current to the second output electrode 68. The current monitoring signal SIMON is input from the second output electrode 68 to the input control circuit 50 through the control device 10 and the third input electrode 84. In the current detection circuit 62 the current monitoring signal SIMON is a signal corresponding to the magnitude of the actual application voltage.
More specifically, the current detection circuit 62 includes the operational amplifier Ap4, resistance elements R24 to R26, and a capacitor element C13. The non-inverting input of the operational amplifier Ap4 is connected to the second external terminal 70b, and is connected to the low potential power source line (ground) through the resistance element R24. The magnitude of the input voltage to the non-inverting input of the operational amplifier Ap4 is determined by the magnitude of the current flow in the microchip 2 and the resistance value of the resistance element R24. The resistance value of the resistance element R24 is, for example, determined according to the magnitude of an assumed load on the microchip 2.
The output of the operational amplifier Ap4 is connected to the inverting input thereof through a resistance element R26 and a capacitor element C13 that are connected in parallel. The inverting input of the operational amplifier Ap4 is grounded through the resistance element R25. Such connection causes the operational amplifier Ap4 to operate as an inverting amplification circuit. The output of the operational amplifier Ap4 is connected to the second output electrode 68, and provides the current monitoring signal SIMON.
The voltage detection circuit 64 monitors the application voltage output from the output protection circuit 58, and generates the voltage monitoring signal SVMON corresponding to the magnitude of the output voltage of the output protection circuit 58. Then, the voltage monitoring signal SVMON is provided to the third output electrode 74. The voltage monitoring signal SVMON is output from the third output electrode 74 and input to the control device 10. In the voltage detection circuit 64, the voltage monitoring signal SVMON is a signal corresponding to the magnitude of the actual application voltage.
The voltage detection circuit 64 includes an operational amplifier Ap5, resistance elements R27 to R30, and a capacitor element C14. The non-inverting input of the operational amplifier Ap5 is connected to a voltage divider circuit (the resistance element R27 and resistance element R28 connected in series) and to a reverse direction diode DI2. The voltage divider circuit is connected between the low potential power source line (ground) and the output of the output protection circuit 58 (the first internal conductor 80a). The non-inverting input of the operational amplifier Ap5 receives a voltage resulting from dividing the voltage output from the CCW circuit 56 using the resistance elements R20 to R27 and R28. The output of the operational amplifier Ap5 is connected to the inverting input of the operational amplifier Ap5 through a resistance element R30 and a capacitor element C14 that are connected in parallel. The inverting input of the operational amplifier Ap5 is connected to the low potential power source line (ground) through the resistance element R29. Such connection means that the operational amplifier Ap5 operates as an inverting amplification circuit. The output of the operational amplifier Ap5 is connected to the third output electrode 74 and provides the voltage monitoring signal SVMON to the third output electrode 74.
The output voltage control circuit 60 and the voltage detection circuit 64 both include a function to monitor the voltage output from the CCW circuit 56, and the voltage detection circuit 64 is connected to the CCW circuit 56 through the output protection circuit 58. This approach is adopted because the magnitudes of the voltages respectively applied to the output voltage control circuit 60 and the voltage detection circuit 64 are different from each other, and the circuit configurations of the output voltage control circuit 60 and the voltage detection circuit 64 are also different from each other.
Description follows regarding operation of the power source device 20. The electrophoresis device 1 performs control in the following manner at an initial stage of voltage application to electrophorese the sample 40 in the capillary 4. In a case in which measurement of the microchip 2 (the sample 40) is performed, the control device 10 outputs the enable signal SENB to operate the power source device 20. The storage device 403 of the control device 10 stores data of the voltages arising in cases assuming a current of a prescribed magnitude flows in the microchip 2 (hereafter referred to as “assumed voltage”), and the control device 10 outputs the current control signal SICNT corresponding to the assumed voltage.
In a case in which the enable signal SENB is input from the control device 10 to the enable circuit 52, the power source device 20 operates to generate the electrophoresis voltage. More specifically, the transistor Tr1 of the enable circuit 52 adopts an ON state in response to the enable signal SENB. In response to this ON state, the transistor Tr2 of the enable circuit 52 also adopts an ON state, and the drive voltage Vdd is supplied to the input control circuit 50.
On receiving the drive voltage Vdd, the input control circuit 50 provides the input voltage to the inverter transformer circuit 54. More specifically, the transistor Tr3 adopts an ON state in response to the enable signal SENB from the second input electrode 82, the transistor Tr3 becomes conductive, and the transistor Tr4 adopts an OFF state. The operational amplifier Ap1 receives the current control signal SICNT through the fourth input electrode 86. The operational amplifier Ap2 receives the current control signal SICNT from the operational amplifier Ap1 at its non-inverting input, and receives the current monitoring signal SIMON through the third input electrode 84 at its inverting input. In response thereto, the operational amplifier Ap2 generates a voltage signal corresponding to the magnitude of the current control signal SICNT and the magnitude of the current monitoring signal SIMON. This voltage signal is provided to the base of the transistor Tr5. In response to this signal, the transistor Tr5 adopts an ON state, and an input voltage to the inverter transformer circuit 54 is provided through the transistor Tr5.
A control loop is started. The inverter transformer circuit 54 receives an input voltage through the transistor Tr5. The inverter transformer circuit 54 outputs an alternating current voltage resulting from raising the input voltage.
The CCW circuit 56 voltage-amplifies the raised voltage output from the inverter transformer circuit 54 (for example by six times) and then outputs the amplified voltage. In a case in which the magnitude of the output voltage output from the CCW circuit 56 has reached a value that is a prescribed magnitude corresponding to the magnitude of the application voltage or greater, then current being input to the primary side of the inverter transformer circuit 54 is interrupted.
The output voltage from the CCW circuit 56 is output as the application voltage from the first external terminal 70a through the output protection circuit 58.
The output voltage from the CCW circuit 56 is provided to the voltage divider circuit including the resistance elements R27 and R28 that are connected in series through the output protection circuit 58, and the voltage divider circuit provides the voltage divided value to the voltage detection circuit 64. The voltage detection circuit 64 generates the voltage monitoring signal SVMON according to the voltage (voltage divided value) output from the output protection circuit 58. Then, the voltage monitoring signal SVMON is provided to the control device 10 through the third output electrode 74.
However, the microchip 2 receives the application voltage at its two ends, from the first electrode 22 connected to the first external terminal 70a and from the second electrode 24 connected to the second external terminal 70b, and is accordingly able to measure the sample 40. During measurement a current flows in the microchip 2 (the sample 40) according to the actual application voltage.
This current is input to the current detection circuit 62, the current detection circuit 62 generates the current monitoring signal SIMON corresponding to the magnitude of this current flow in the microchip 2, and the current monitoring signal SIMON is provided to the control device 10 through the second output electrode 68. The current monitoring signal SIMON is provided to the input control circuit 50 through the control device 10 and the third input electrode 84.
In the input control circuit 50, the operational amplifier Ap2 compares the magnitude of the current monitoring signal SIMON against the magnitude of the current control signal SICNT, and generates a signal to change the input voltage of the inverter transformer circuit 54 based on this comparison result. More specifically, the operational amplifier Ap2 provides a signal to the base of the transistor Tr5 that is a signal having a magnitude corresponding to a difference between the magnitude of the current monitoring signal SIMON and the magnitude of the current control signal SICNT. In response thereto, the magnitude of the base-emitter voltage VBE is changed in the transistor Tr5. In response to this change, the output from the input control circuit 50 to the inverter transformer circuit 54 changes. Thus, in a case in which there is a substantial difference between the magnitude of the current monitoring signal SIMON and the magnitude of the current control signal SICNT, the magnitude of the input voltage input to the inverter transformer circuit 54 is updated according to this difference. In a case in which there is no longer a substantial difference between the magnitude of the current monitoring signal SIMON and the magnitude of the current control signal SICNT, the magnitude of the input voltage input to the inverter transformer circuit 54 is maintained.
This completes the description of a cycle of updating. Processing then returns to a “control loop is started”, and the update operation is repeated.
In a case in which this processing is performed repeatedly, the assumed voltage stored in the storage device 403 is updated for each loop, and the current control signal corresponding to this updated assumed voltage is output in the next loop. By repeatedly performing the operations in the loop in this manner, a current of the prescribed magnitude corresponding to the assumed voltage flows in the microchip 2, and setting of the current is completed. The voltage corresponding to the current of this prescribed magnitude is thereafter applied to the microchip 2. The sample 40 being electrophoresed in the capillary 4 enables, for example, a specific component such as hemoglobin A1c or the like in the blood to be analyzed. During this electrophoresis, each of the operations in the loop as described above may be performed repeatedly.
In a case in which a disposable type of the microchip 2 is employed as the measurement tool, the load is not fixed, and in a case in which a conventional power source device is employed, there may be cases in which the magnitude of the assumed voltage does not match the magnitude of the actual application voltage based on the actual current flow in the microchip 2. Namely, in a case in which the measurement tool is the disposable type microchip 2, sometimes the prescribed magnitude of current does not flow in the microchip 2. However to address such situations, the power source device 20 enables a current of the prescribed magnitude to flow irrespective of the microchip 2 as described above, while also enabling a high voltage to be provided by forward polarity application and reverse polarity application.
Moreover, in the power source device 20 the raised voltage output from the inverter transformer circuit 54 is amplified by the CCW circuit 56, and so there is no need for a large current, and forward polarity application and reverse polarity application of the high voltage can be provided with a comparatively small current.
The power source device 20 enables a high accuracy to be maintained for the accuracy in the magnitude of the voltage for application with a small current, while also enabling forward polarity application and reverse polarity application of the high voltage. Moreover, the power source device 20 employs the inverter transformer circuit 54 and the CCW circuit 56 as described above, enabling forward polarity application and reverse polarity application of the high voltage while suppressing the power source device 20 from becoming bulky and also suppressing the cost thereof.
Moreover, for example, the power source device 20 may be applied to a measurement device and an analysis device other than the electrophoresis device 1. Note that the power source device 20 enables forward polarity application and reverse polarity application of the high voltage irrespective of variation in load of the measurement tool.
Moreover, the current detection circuit 62 enables control of the magnitude of current to be performed with higher accuracy by adjustment based on the magnitude of the assumed voltage and magnitude of the current corresponding to the assumed voltage.
The present disclosure is not limited to the exemplary embodiment described above, and various modifications may be implemented within a range not departing from the spirit of the present disclosure. All of such modifications are encompassed in the technical concept of the present disclosure.
As described above, the present exemplary embodiment provides a power source device having a polarity of electrophoresis voltage selectable in both one direction and a reverse direction, and provides an electrophoresis device including such a power source device and a method to control such an electrophoresis device.
All publications, patent applications and technical standards mentioned in the present specification are incorporated by reference in the present specification to the same extent as if each individual publication, patent application, or technical standard was specifically and individually indicated to be incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-063037 | Apr 2022 | JP | national |
