1. Technical Field
The present disclosure relates to a power supply circuit for a power control chip.
2. Description of Related Art
Portable computers include power control chips to receive an input voltage. The power control chip drives a transformer outputting a +48 volts voltage. The +48 volts voltage is provided to a number of loads in the portable computer. A conventional power supply circuit for power control chips does not have over voltage protection functions. The power control chips may be damaged when the input voltage is over voltage.
Therefore, there is a need for improvement in the art.
Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.”
The voltage output circuit 20 includes a MOSFET Q1 and a transformer T. The MOSFET Q1 includes a gate, a source and a drain. The transformer T includes a driving terminal, a first voltage input terminal, a second voltage input terminal, a first voltage output terminal and a second voltage output terminal. The gate of the MOSFET Q1 is electrically connected to the driving voltage output terminal OUT. The source of the MOSFET Q1 is grounded via a third resistor R3. The drain of the MOSFET Q1 is electrically connected to the driving terminal of the transformer T.
The first voltage input terminal of the transformer T receives the first DC voltage. The second voltage input terminal of the transformer T is electrically connected to a connecting point between the first resistor R1 and the capacitor C via a fourth resistor R4 and a first diode D1. The first voltage output terminal of the transformer T is electrically connected to an anode of a second diode D2. A cathode of the second diode D2 outputs a second DC voltage. In one embodiment, the MOSFET Q1 is a N channel MOSFET. The second DC voltage is +48 volts.
The feedback protect circuit 30 includes a first transistor Q2, a second transistor Q3, a first photocoupler U2, a second photocoupler U3, a third diode D3, a fourth diode D4, a fifth resistor R5 and a sixth resistor R6. Each of the first transistor Q2 and the second transistor Q3 includes a base, an emitter and a collector. The first photocoupler U2 includes a first light emitting unit and a first switch unit. The second photocoupler U3 includes a second light emitting unit and a second switch unit. In one embodiment, the first transistor Q2 is a pnp type transistor. The second transistor Q3 is a npn type transistor. The third diode D3 and the fourth diode D4 are Zener diodes.
The base of the first transistor Q2 is electrically connected to the power terminal VDD via the fifth resistor R5. The emitter of the first transistor Q2 is electrically connected to the power terminal VDD. The collector of the first transistor Q2 is grounded via the sixth resistor R6. The collector of the first transistor Q2 is electrically connected to the base of the second transistor Q3. The emitter of the second transistor Q3 is grounded. The collector of the second transistor Q3 is electrically connected to the base of the first transistor Q2.
Each of the first switch unit and the second switch unit includes a first terminal and a second terminal. Each of the first light emitting unit and the second light emitting unit includes an anode and a cathode. The first terminal of the first switch unit is electrically connected to the collector of the second transistor Q3. The second terminal of the first switch unit is grounded. The anode of the first light emitting unit is electrically connected to an anode of the third diode D3. The cathode of the first light emitting unit is grounded. A cathode of the third diode D3 is electrically connected to an anode of the fourth diode D4.
A cathode of the fourth diode D4 is electrically connected to the cathode of the second diode D2. The first terminal of the second switch unit is electrically connected to the reference terminal REF. The second terminal of the second switch unit is electrically connected to the feedback terminal FB via a seventh resistor R7. The anode of the second light emitting unit is electrically connected to a cathode of a fifth diode D5 via an eighth resistor R8. The cathode of the second light emitting unit receives a voltage feedback signal. An anode of the fifth diode D5 is electrically connected to the second voltage output terminal of the transformer T.
In use, the first DC voltage charges the capacitor C via the first resistor R1 and the second resistor R2. When the capacitor C is fully charged, the capacitor C provides the first DC voltage to the power control chip U1 via the power terminal VDD. The power control chip U1 is power on and outputs a voltage driving signal at the driving voltage output terminal OUT. The gate of the MOSFET Q1 receives the voltage driving signal. The MOSFET Q1 turns on. The drain of the MOSFET Q1 outputs the voltage driving signal to the driving terminal of the transformer T. The first voltage input terminal and the second voltage input terminal of the transformer T receives the first DC voltage. The transformer T outputs the +48 volts second DC voltage to a load (not shown) via the first voltage output terminal according to the voltage driving signal and the first DC voltage.
The load outputs the voltage feedback signal when the second DC voltage is abnormal. The cathode of the second light emitting unit receives the voltage feedback signal. The second light emitting unit turns on and emits light. The second switch unit detects the light from the second light emitting unit. The second switch unit turns on. The reference terminal REF and the feedback terminal FB are electrically connected. The power control chip U1 adjusts the voltage driving signal output by the driving voltage output terminal OUT. Therefore, the second DC voltage output by the first voltage output terminal of the transformer T is adjusted.
When the first DC voltage received by the power terminal VDD is over voltage, the second DC voltage output by the first voltage output terminal of the transformer T is greater than +48 volts. The third diode D3 and the fourth diode D4 are breakdown and turn on. The anode of the first light emitting unit receives the second DC voltage. The first light emitting unit turns on and emits light. The first switch unit detects the light from the first light emitting unit. The first switch unit turns on. The base of the first transistor Q2 is low voltage level. The first transistor Q2 turns on. The base of the second transistor Q3 receives the first DC voltage via the first transistor Q2. The second transistor Q3 turns on.
The capacitor C discharges to ground via the first transistor Q2 and the sixth resistor R6. The capacitor C discharges to ground via the fifth resistor R5 and the second transistor Q3. The capacitor C cannot provide the first DC voltage to the power control chip U1 via the power terminal VDD. The power control chip U1 is power off. Therefore, the power control chip U1 is protected from being damaged when the first DC voltage is over voltage.
Even though numerous characteristics and advantages of the present disclosure have been set forth in the foregoing description, together with details of the structure and function of the disclosure, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of shape, size, and the arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Number | Date | Country | Kind |
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2013102965599 | Jul 2013 | CN | national |