1. Field of the Invention
The present invention relates to power supply circuits and, particularly to a power supply circuit for a pulse width modulation (PWM) controller on a motherboard.
2. Description of Related Art
Switched-mode power supplies such as PWM controllers are being increasingly used in computers to provide a number of precisely regulated output voltages to power various integrated circuits and other components contained within the computers. Input voltages of the PWM controllers are provided by a computer power supply. Computer users often cannot wake their computers from sleep mode because input voltages of the PWM controllers in the computers are often lower than a predetermined value.
What is needed, therefore, is to provide a power supply circuit to wake up a computer from sleep mode.
The drawing is a circuit diagram of a power supply circuit for a PWM controller according to an embodiment of the present invention.
Referring to the drawing, a power supply circuit for a PWM controller 20 in a computer according to an embodiment of the present invention includes a diode D10, an electric switch Q, first and second resistors R10 and R20. The anode of the diode D10 is connected to a system power supply 12_SYS of the computer. The cathode of the diode D10 is connected to a power input terminal PWM_Vcc of the PWM controller 20 via the resistor R10. The electric switch Q includes first, second, and third terminals 1, 2 and 3. The first electric switch terminal 1 is configured for receiving a power good (PWRGD) signal of the computer via the second resistor R20. The second electric switch terminal 2 is connected to a stand-by power supply 5V_SB of the computer. The third electric switch terminal 3 is connected to the cathode of the diode D10. In this embodiment, the type of the PWM controller 20 is RT9214. The electric switch Q is a P-channel metallic oxide semiconductor field effect (PMOS) transistor or a positive-negative-positive (PNP) transistor. The first to third electric switch terminals 1, 2 and 3 are the gate, the drain, and the source of the PMOS transistor or the base, the collector, and the emitter of the PNP transistor respectively. When the power input terminal PWM_Vcc receives a voltage higher than a predetermined value, for example, 4.75V, the computer can be wakened from a sleep mode.
When the computer is wakened from the sleep mode, the system power supply 12V_SYS outputs no voltage. The PWRGD signal is at a low level, and the electric switch Q is on. The voltage difference between the terminals 2 and 3 is nearly 0V. The stand-by power supply 5V_SB provides an input voltage to the PWM controller 20 via the switch Q and the first resistor R10. The voltage at the power input terminal PWM_Vcc is greater than 4.75V because no voltage is dropped across the electric switch 20 when it is on.
When the computer is working normally, the PWRGD signal is at a high level, and the electric switch Q is off. The system power supply 12V_SYS provides the input voltage to the PWM controller 20 via the diode 10 and the second resistor 20.
The embodiment is chosen and described in order to explain the principles of the invention and their practical application so as to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains without departing from its spirit and scope. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.
Number | Date | Country | Kind |
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200810302655.9 | Jul 2008 | CN | national |