Patent Application
20240258972
This application relates to the field of communication device technologies, and in particular, to a power supply circuit, a processing circuit, and a wireless communication system.
As mobile wireless communication technologies gradually transition from being in a conventional voice communication-centric era to being in a fourth generation mobile communication technology (the 4th generation mobile communication technology, 4G) era with a mobile broadband and a 5G era with a networked society, electronic devices with a mobile communication function or a wireless communication function have become increasingly popular and are used to provide a wireless communication service for users. As users have increasingly strong requirements on application of mobile wireless communication technologies, there are increasingly high requirements on communication rates, and users require access to wireless communication networks anytime and anywhere. These requirements have spurred the vigorous development of the mobile wireless communication technologies. Electronic devices need to support various communication modes and standards, from 4G long term evolution (long term evolution, LTE) to 5G new radio (new radio, NR), from early wireless fidelity (wireless fidelity, Wi-Fi) to today's Wi-Fi 6, and the like. A communication bandwidth becomes increasingly wide: from 4G LTE with a bandwidth of 1.4 MHz to 5G NR with a bandwidth of 100 MHz or even 200 MHz. In addition, in broadband Wi-Fi and millimeter-wave communication systems, a bandwidth of a signal is wider. These electronic devices usually perform corresponding processing on radio frequency (radio frequency, RF) signals. For example, before a radio frequency signal is transmitted, a power amplifier (power amplifier, PA) needs to be used to increase output power of the radio frequency signal (for example, to maintain sufficient energy per bit).
A service life of an electronic device is closely related to a battery capacity and system efficiency. Against a current background that a battery capacity cannot be expanded anymore while power consumption of another part in an electronic device becomes increasingly large, improving transmit efficiency of a radio frequency part, especially a radio frequency PA system that occupies a large proportion of power consumption, is highly important for prolonging a service life of a terminal.
Embodiments of this application provide a power supply circuit, a processing circuit, and a wireless communication system, to improve transmit efficiency of a PA.
To achieve the foregoing objective, the following technical solutions are used in this application.
According to a first aspect, a wireless communication system is provided. The wireless communication system includes: a processing circuit, at least one linear amplification circuit, a switch amplification circuit, at least one first filter capacitor, and at least one power amplifier. An output end of the switch amplification circuit, an output end of the linear amplification circuit, and a power supply end of the power amplifier are coupled at a first node. The first filter capacitor is coupled to an input end of the linear amplification circuit or the output end of the linear amplification circuit. The processing circuit is configured to: output a first radio frequency signal of a first transmit signal, and output a first envelope signal and a first drive signal that are of the first transmit signal. The first drive signal includes a switch signal of the switch amplification circuit or a second envelope signal. The switch signal of the switch amplification circuit is generated by the processing circuit based on the second envelope signal. The linear amplification circuit is configured to: receive the first envelope signal, and output a first power supply voltage to the first node. The switch amplification circuit is configured to: receive the first drive signal, and output a second power supply voltage to the first node. The power amplifier is configured to amplify the first radio frequency signal based on the first power supply voltage and the second power supply voltage. It should be noted that the first filter capacitor can filter out a low frequency part and a direct current part in the first envelope signal, or filter out a low frequency part and a direct current part in the first power supply voltage. The switch amplification circuit SA may include a control chip, for example, a drive chip, configured to convert the second envelope signal ET2_DAC41 to the switch signal of the switch amplification circuit SA. The switch signal of the switch amplification circuit may be a square wave signal, for example, a pulse width modulation (pulse width modulation) PWM square wave signal. When the switch amplification circuit SA includes the control chip, the processing circuit may directly send the second envelope signal ET2_DAC41 to the switch amplification circuit SA. When the switch amplification circuit SA does not include the control chip, the processing circuit may alternatively convert the second envelope signal ET2_DAC41 to the switch signal of the switch amplification circuit SA, and send the switch signal to the switch amplification circuit SA. In the foregoing solution, when the first filter capacitor C1 is disposed at the output end of the linear amplification circuit LA, as the low frequency part and the direct current part in the first power supply voltage are filtered out through filtering performed by the first filter capacitor C1, the first power supply voltage is an alternating current voltage that swings around 0 V. In this way, because the first filter capacitor C1 exists, as the first filter capacitor C1 couples the output end of the linear amplification circuit LA to the output end of the switch amplification circuit SA, a voltage swing amplitude (that is, the first power supply voltage filtered by the first filter capacitor) may be provided between the second power supply voltage output by the SA and a power supply voltage at the power supply end of the power amplifier. In this way, a power supply voltage of the linear amplification circuit LA only needs to be equal to the voltage swing amplitude, but does not need to be equal to a voltage value of a highest crest in the first power supply voltage before the filtering of the first filter capacitor C1, so that the power supply voltage of the linear amplification circuit LA can be reduced. In addition, because a final power supply voltage of the power amplifier depends on superposition of an output voltage of the switch amplification circuit SA and a voltage swing amplitude output by the linear amplification circuit LA, this solution can support a peak voltage of an envelope signal higher than the power supply voltage of the linear amplification circuit LA. Therefore, with a lower power supply voltage of the LA, a larger power output of the power amplifier can be supported, so that transmit efficiency of the power amplifier is improved. In addition, when the first filter capacitor C1 is disposed at the input end of the LA, the first filter capacitor C1 may directly filter out the low frequency part and the direct current part in the first envelope signal ET1_DAC41. A waveform of the first envelope signal ET1_DAC41 is similar to that of the first power supply voltage. However, when the first envelope signal ET1_DAC41 is not amplified by the LA, an overall amplitude of the waveform of the first envelope signal ET1_DAC41 is smaller than that of the first power supply voltage. After the first filter capacitor C1 filters out the low frequency part and the direct current part in the first envelope signal ET1_DAC41, a voltage of the first envelope signal ET1_DAC41 is an alternating current voltage that swings around 0 V. Because the first filter capacitor C1 is disposed at the input end of the LA, the low frequency part and the direct current part in the first envelope signal ET1_DAC41 are filtered out before the first envelope signal ET1_DAC41 is input to the LA. Therefore, the LA only needs to amplify a high frequency part in the first envelope signal ET1_DAC41. In addition, because the direct current part is removed, the power supply voltage of the LA can be effectively reduced. Therefore, with a lower power supply voltage of the LA, larger output power of the power amplifier can be supported, so that the transmit efficiency of the power amplifier PA is improved.
In a possible implementation, the first envelope signal includes an envelope signal of a high frequency part in the first transmit signal; and/or the second envelope signal includes an envelope signal of a low frequency part and a direct current part in the first transmit signal. Because the first filter capacitor C1 can isolate the direct current part and the low frequency part in the first power supply voltage, the LA with low efficiency only needs to amplify an envelope signal of a part of the first transmit signal BS1 (the envelope signal of the high frequency part, where for example, the first envelope signal ET1_DAC41 includes the envelope signal of the high frequency part in the first transmit signal) to generate the first power supply voltage, and an envelope signal of most of the first transmit signal (all the signal or the low frequency part and the direct current part, where for example, the second envelope signal ET_DAC42 includes all the first transmit signal or the envelope signal of the low frequency part and the direct current part in the first transmit signal) is amplified by the SA with high efficiency to generate the second power supply voltage. Finally, the first power supply voltage and the second power supply voltage are superposed at the first node a to obtain the power supply voltage of the power amplifier PA. For example, a highest frequency of the first envelope signal is greater than a highest frequency of the second envelope signal; and/or a lowest frequency of the first envelope signal is greater than a lowest frequency of the second envelope signal.
In a possible implementation, a second filter capacitor is further included, where the first filter capacitor is coupled to the output end of the linear amplification circuit, and the second filter capacitor is coupled to the input end of the linear amplification circuit. The first filter capacitor is configured to filter out the low frequency part and the direct current part in the first power supply voltage. The second filter capacitor is configured to filter out the low frequency part and the direct current part in the first envelope signal.
In a possible implementation, an analog high-pass filter is further included, where the first filter capacitor is coupled to the output end of the linear amplification circuit, and the analog high-pass filter is coupled to the input end of the linear amplification circuit. The first filter capacitor is configured to filter out the low frequency part and the direct current part in the first power supply voltage. The analog high-pass filter is configured to filter out the low frequency part and the direct current part in the first envelope signal.
In a possible implementation, the processing circuit is further configured to: perform shaping filtering on the first transmit signal to generate the first envelope signal; and perform shaping filtering on the first transmit signal to generate the second envelope signal. A function of performing shaping filtering on the first transmit signal BS1 is to enable the signal to better match a subsequent hardware channel (for example, to enable an amplitude and a phase of the first envelope signal ET1_DAC41 to better match a hardware capability of the LA, and to enable an amplitude and a phase of the second envelope signal ET2_DAC41 to better match a hardware capability of the SA).
In a possible implementation, the first filter capacitor is coupled to the output end of the linear amplification circuit. The processing circuit is configured to filter out the low frequency part and the direct current part in the first transmit signal to generate the first envelope signal. The first filter capacitor filters out the low frequency part and the direct current part in the first power supply voltage in analog domain. The processing circuit may filter out the low frequency part and the direct current part in the first transmit signal in digital domain by using a digital filtering function, to generate the first envelope signal.
In a possible implementation, the processing circuit is further configured to perform amplitude and/or phase compensation on the first transmit signal to generate the first envelope signal, or is further configured to perform amplitude and/or phase compensation on the first transmit signal to generate the second envelope signal. Transmission paths of the subsequent hardware channels of the first envelope signal ET1_DAC41 and the second envelope signal ET2_DAC41 are different, where the first envelope signal ET1_DAC41 is input to the LA, and the second envelope signal ET2_DAC41 is input to the SA. Therefore, a difference in hardware causes a phase difference between signals at the output ends of the LA and the SA and an amplitude loss. The processing circuit may further perform equalization processing on the first transmit signal BS1. For example, the processing circuit performs amplitude and/or phase compensation on the first transmit signal BS1 to generate the first envelope signal ET1_DAC41, or performs amplitude and/or phase compensation on the first transmit signal BS1 to generate the second envelope signal ET2_DAC41. A specific value of the amplitude and/or phase compensation depends on a hardware parameter of the LA or the SA. A value of the amplitude and/or phase compensation corresponding to the first envelope signal ET1_DAC41 may be determined by using the hardware parameter of the LA or by detecting a voltage at the output end of the LA. A value of the amplitude and/or phase compensation corresponding to the second envelope signal ET2_DAC41 may be determined by using the hardware parameter of the SA or by detecting a voltage at the output end of the SA.
In a possible implementation, in an embodiment of this application, the LA mainly processes the high frequency part in the first envelope signal ET_DAC41, and inductive reactance or capacitive reactance of a trace between the LA and the PA causes degradation of a high frequency signal. Therefore, it is necessary to shorten a trace length between the LA and the PA as much as possible, to reduce the inductive reactance or the capacitive reactance of the trace. A length of the trace between the linear amplification circuit and the power amplifier is less than a length of a trace between the switch amplification circuit and the power amplifier.
In a possible implementation, the linear amplification circuit and the power amplifier are packaged on a same package substrate, or the linear amplification circuit and the power amplifier are manufactured on a same die, to reduce the length of the trace between the switch amplification circuit SA and the power amplifier PA.
In a possible implementation, to better arrange the switch amplification circuit SA and the power amplifier PA to reduce the length of the trace between the switch amplification circuit SA and the power amplifier PA, the linear amplification circuit and the switch amplification circuit are manufactured on different dies.
In a possible implementation, the switch amplification circuit includes a multi-phase and/or multi-voltage switch amplification circuit. A multi-potential switch amplification circuit may use a plurality of different power supply voltages as input voltages of the switch amplification circuit, and the switch amplification circuit can separately output the second power supply voltage based on the plurality of different power supply voltages, to increase a range of a voltage value of the second power supply voltage. In addition, a multi-phase switch amplification circuit may provide, based on the power supply voltages input to the switch amplification circuit, a plurality of output voltages of different phases as the second power supply voltage, so that the SA is capable of outputting a second power supply voltage with a higher frequency when processing most of the first transmit signal (all the signal or the low frequency part and the direct current part).
In a possible implementation, at least one linear amplifier includes a first linear amplifier and a second linear amplifier. The at least one power amplifier includes a first power amplifier and a second power amplifier. The at least one first filter capacitor includes a third filter capacitor and a fourth filter capacitor. The output end of the switch amplification circuit, an output end of the first linear amplification circuit, and a power supply end of the first power amplifier are coupled at the first node. The third filter capacitor is coupled to an input end of the first linear amplification circuit or the output end of the first linear amplification circuit. The output end of the switch amplification circuit, an output end of the second linear amplification circuit, and a power supply end of the second power amplifier are coupled at a second node. The fourth filter capacitor is coupled to an input end of the second linear amplification circuit or the output end of the second linear amplification circuit. The first linear amplification circuit is configured to: receive the first envelope signal, and output the first power supply voltage to the first node. The second linear amplification circuit is configured to: receive the first envelope signal, and output a third power supply voltage to the second node. In a beamforming (beamforming) architecture or a multiple-input multiple-output (multiple-input multiple-output, MIMO) architecture, when the processing circuit transmits a same radio frequency signal on a plurality of channels, each channel corresponds to one power amplifier. In this case, to reduce hardware costs, a plurality of linear amplification circuits may share one switch amplification circuit, and a same radio frequency signal is simultaneously transmitted on different power amplifiers.
In a possible implementation, at least one linear amplifier includes a first linear amplifier and a second linear amplifier. The at least one power amplifier includes a first power amplifier and a second power amplifier. The at least one first filter capacitor includes a third filter capacitor and a fourth filter capacitor. The output end of the switch amplification circuit, an output end of the first linear amplification circuit, and a power supply end of the first power amplifier are coupled at the first node. The third filter capacitor is coupled to an input end of the first linear amplification circuit or the output end of the first linear amplification circuit. The output end of the switch amplification circuit, an output end of the second linear amplification circuit, and a power supply end of the second power amplifier are coupled at a second node. The fourth filter capacitor is coupled to an input end of the second linear amplification circuit or the output end of the second linear amplification circuit. When the first power amplifier is enabled by using an enable signal, the first linear amplification circuit is configured to: receive the first envelope signal, and output the first power supply voltage to the first node; or when the second power amplifier is enabled by using an enable signal, the second linear amplification circuit is configured to: receive the first envelope signal, and output a third power supply voltage to the second node. In a scenario of a plurality of transmit channels, for example, in an uplink multiple-input multiple-output (multiple-input multiple-output, MIMO) or uplink carrier aggregation (carrier aggregation, CA) scenario, the processing circuit may provide radio frequency signals of a plurality of channels, and the processing circuit may transmit a same radio frequency signal on some channels, and transmit different radio frequency signals on the other channels. Specifically, each channel corresponds to one power amplifier. The processing circuit may transmit a radio frequency signal of a corresponding channel on a power amplifier enabled by using the enable signal. In this way, different radio frequency signals may be transmitted on different power amplifiers in a time-sharing manner.
According to a second aspect, a power supply circuit is provided, including: at least one linear amplification circuit, a switch amplification circuit, and at least one first filter capacitor. An output end of the linear amplification circuit and an output end of the switch amplification circuit are coupled at a first node. A power supply end of a power amplifier is coupled at the first node. The first filter capacitor is coupled to an input end of the linear amplification circuit or the output end of the linear amplification circuit. The linear amplification circuit is configured to: receive a first envelope signal sent by a processing circuit, and output a first power supply voltage to the first node. The switch amplification circuit is configured to: receive a first drive signal sent by the processing circuit, and output a second power supply voltage to the first node. The first envelope signal and the first drive signal are generated by the processing circuit based on a first transmit signal. The first drive signal includes a switch signal of the switch amplification circuit or a second envelope signal. The switch signal of the switch amplification circuit is generated by the processing circuit based on the second envelope signal. The power amplifier amplifies, based on the first power supply voltage and the second power supply voltage, a first radio frequency signal generated by the processing circuit based on the first transmit signal. It should be noted that the first filter capacitor can filter out a low frequency part and a direct current part in the first envelope signal, or filter out a low frequency part and a direct current part in the first power supply voltage.
In a possible implementation, the first envelope signal includes an envelope signal of a high frequency part in the first transmit signal; and/or the second envelope signal includes an envelope signal of a low frequency part and a direct current part in the first transmit signal.
In a possible implementation, a second filter capacitor is further included, where the first filter capacitor is coupled to the output end of the linear amplification circuit, and the second filter capacitor is coupled to the input end of the linear amplification circuit. The first filter capacitor is configured to filter out the low frequency part and the direct current part in the first power supply voltage. The second filter capacitor is configured to filter out the low frequency part and the direct current part in the first envelope signal.
In a possible implementation, an analog high-pass filter is further included, where the first filter capacitor is coupled to the output end of the linear amplification circuit, and the analog high-pass filter is coupled to the input end of the linear amplification circuit. The first filter capacitor is configured to filter out the low frequency part and the direct current part in the first power supply voltage. The analog high-pass filter is configured to filter out the low frequency part and the direct current part in the first envelope signal.
In a possible implementation, a length of a trace between the linear amplification circuit and the power amplifier is less than a length of a trace between the switch amplification circuit and the power amplifier.
In a possible implementation, the linear amplification circuit and the power amplifier are packaged on a same package substrate, or the linear amplification circuit and the power amplifier are manufactured on a same die.
In a possible implementation, the linear amplification circuit and the switch amplification circuit are manufactured on different dies.
In a possible implementation, the switch amplification circuit includes a multi-phase and/or multi-voltage switch amplification circuit.
According to a third aspect, a power supply circuit is provided, including: at least one first analog low-pass filter, at least one second analog low-pass filter, at least one linear amplification circuit, a switch amplification circuit, and at least one first filter capacitor. An output end of the linear amplification circuit and an output end of the switch amplification circuit are coupled at a first node. A power supply end of a power amplifier is coupled at the first node. The first filter capacitor is coupled to an input end of the linear amplification circuit or the output end of the linear amplification circuit. The second analog low-pass filter is configured to filter out a high frequency part in a predetermined envelope signal received from a processing circuit, to generate a first envelope signal. The first analog low-pass filter is configured to perform delay adjustment on the predetermined envelope signal received from the processing circuit, to generate a second envelope signal. The linear amplification circuit is configured to: receive the first envelope signal, and output a first power supply voltage to the first node. The switch amplification circuit is configured to: receive the second envelope signal, and output a second power supply voltage to the first node. The predetermined envelope signal is generated by the processing circuit based on a first transmit signal. The power amplifier amplifies, based on the first power supply voltage and the second power supply voltage, a first radio frequency signal generated by the processing circuit based on the first transmit signal. It should be noted that the first filter capacitor can filter out a low frequency part and a direct current part in the first envelope signal, or filter out a low frequency part and a direct current part in the first power supply voltage.
In the wireless communication system provided in the first aspect, in addition to improving a power supply circuit in analog domain, in digital domain, the processing circuit further needs to be capable of separately generating, based on the first transmit signal BS1, the first envelope signal ET1_DAC41 provided to the LA and a first drive signal DR (which, for example, may be the second envelope signal ET2_DAC41) provided to the SA. In other words, the processing circuit 501 is also correspondingly improved. In the third aspect, in another solution, the processing circuit is not improved. That is, compared with the power supply circuit provided in the second aspect, for the predetermined envelope signal ET_DAC41 received from the processing circuit in the third aspect, one first analog low-pass filter AF2 is added to an input end of the SA to perform low-pass filtering on an input predetermined envelop signal ET_DAC41 (filtering out a high frequency part in the predetermined envelope signal ET_DAC41) to extract a waveform input to the SA (that is, the second envelope signal ET2_DAC41). A bandwidth of the first analog low-pass filter AF2 may be determined based on a switching frequency of the SA, for example, 1 MHz, 5 MHz, or 10 MHz. One second analog low-pass filter AF3 is added to the input end of the SA to perform delay adjustment on the predetermined envelope signal ET_DAC41 to generate the first envelope signal ET1_DAC41, to implement delay difference adjustment of two signals on the SA and the LA and ensure phase alignment of voltages output by the SA and the LA. Therefore, the processing circuit does not need to be changed, and the predetermined envelope signal ET_DAC41 may be directly and compatibly used to supply power to the power amplifier PA. In addition, in the solution provided in the third aspect, a structure and a function of another part are similar to those in the solution provided in the first aspect. Details are not described herein again.
In a possible implementation, a second filter capacitor is further included, where the first filter capacitor is coupled to the output end of the linear amplification circuit, and the second filter capacitor is coupled to the input end of the linear amplification circuit. The first filter capacitor is configured to filter out the low frequency part and the direct current part in the first power supply voltage. The second filter capacitor is configured to filter out the low frequency part and the direct current part in the first envelope signal.
In a possible implementation, the second analog low-pass filter is further configured to filter out the low frequency part and the direct current part in the first envelope signal.
In a possible implementation, a length of a trace between the linear amplification circuit and the power amplifier is less than a length of a trace between the switch amplification circuit and the power amplifier.
In a possible implementation, the linear amplification circuit and the power amplifier are packaged on a same package substrate, or the linear amplification circuit and the power amplifier are manufactured on a same die.
In a possible implementation, the linear amplification circuit and the switch amplification circuit are manufactured on different dies.
In a possible implementation, the switch amplification circuit includes a multi-phase and/or multi-voltage switch amplification circuit.
According to a fourth aspect, a signal generation method is provided, including: outputting a first envelope signal of a first transmit signal, and outputting a first drive signal of the first transmit signal. The first drive signal includes a switch signal of a switch amplification circuit or a second envelope signal. The switch signal of the switch amplification circuit is generated by a processing circuit based on the second envelope signal. The first envelope signal includes an envelope signal of a high frequency part in the first transmit signal; and/or the second envelope signal includes an envelope signal of a low frequency part and a direct current part in the first transmit signal.
In a possible implementation, the outputting a first envelope signal of a first transmit signal includes: performing shaping filtering on the first transmit signal to generate the first envelope signal. The outputting a first drive signal of the first transmit signal includes: performing shaping filtering on the first transmit signal to generate the first drive signal.
In a possible implementation, the outputting a first envelope signal of a first transmit signal includes: filtering out the low frequency part and the direct current part in the first transmit signal to generate the first envelope signal.
In a possible implementation, the outputting a first envelope signal of a first transmit signal includes: performing amplitude and/or phase compensation on the first transmit signal to generate the first envelope signal.
The outputting a first drive signal of the first transmit signal includes: performing amplitude and/or phase compensation on the first transmit signal to generate the first drive signal.
According to a fifth aspect, a processing circuit is provided. The processing circuit is configured to implement the signal generation method according to the fourth aspect. The processing circuit may be user equipment, a chip (for example, a processor chip), or the like.
It should be understood that the technical solutions in the second aspect to the fifth aspect of this application are consistent with the technical solution in the first aspect of this application, and beneficial effects achieved in the aspects and the corresponding feasible implementations are similar. Details are not described again.
To describe technical solutions in embodiments of this application or in the background more clearly, the following describes the accompanying drawings used in embodiments of this application or in the background.
The following describes embodiments of this application with reference to the accompanying drawings in embodiments of this application. In the following descriptions, refer to the accompanying drawings that form a part of this application and show, in an illustrative manner, specific aspects of embodiments of this application or specific aspects in which embodiments of this application may be used. It should be understood that embodiments of this application may be used in another aspect, and may include structural or logical changes that are not depicted in the accompanying drawings. For example, it should be understood that disclosed content with reference to the described method may also be applied to a corresponding device or system configured to perform the method, and vice versa. For example, if one or more specific method steps are described, a corresponding device may include one or more units such as a functional unit for performing the described one or more method steps (for example, one unit for performing the one or more steps; or a plurality of units, each of which performs one or more of a plurality of steps), even if such one or more units are not explicitly described or illustrated in the accompanying drawings. In addition, for example, if a specific apparatus is described based on one or more units such as a functional unit, a corresponding method may include one step for implementing functionality of one or more units (for example, one step for implementing functionality of one or more units; or a plurality of steps, each of which performs functionality of one or more units in a plurality of units), even if such one or more of steps are not explicitly described or illustrated in the accompanying drawings. Further, it should be understood that, unless otherwise specified, features of various example embodiments and/or aspects described in this specification may be combined with each other.
In this application, unless otherwise clearly specified and limited, the term “coupling” may be a manner of implementing an electrical connection for signal transmission, and the term “coupling” may be a direct electrical connection, or may be an indirect electrical connection through an intermediate medium.
A low frequency part in embodiments of this application is also referred to as a low frequency component, and a high frequency part is also referred to as a high frequency component. In embodiments of this application, the low frequency part and the high frequency part are merely relative concepts. In embodiments of this application, a signal includes a low frequency part, a high frequency part, and a direct current part. There is an intersection or no intersection between the low frequency part and the high frequency part. The low frequency part includes a part of the signal whose frequency is below a reference frequency threshold, and the high frequency component includes a part of the signal whose frequency is higher than a reference frequency threshold, where the reference frequency threshold of the low frequency part may be the same as or different from the reference frequency threshold of the high frequency part.
A linear amplification circuit/linear amplifier (linear amplifier, LA) is also referred to as a linear power amplifier. The linear amplification circuit LA is an amplifier whose amplitude of an output signal is directly proportional to an amplitude of an input signal. A typical linear amplification circuit LA includes: a class B power amplifier (class B) and a class AB power amplifier (class AB).
A switch amplification circuit/switch amplifier (switch amplifier, SA) is also referred to as a switch power amplifier or a switch-type power amplifier. Compared with the LA, efficiency of the SA is high. Generally, the efficiency of the SA may reach at least 90%, and may even reach 100% in an ideal state. A typical switch amplifier includes a class D power amplifier.
An embodiment of this application provides a wireless communication system. The wireless communication system may be applied to an electronic device such as a mobile phone, a tablet computer, a personal computer (personal computer, PC), a personal digital assistant (personal digital assistant, PDA), a smartwatch, a netbook, a wearable electronic device, an augmented reality (augmented reality, AR) device, a virtual reality (virtual reality, VR) device, a vehicle-mounted device, a smart automobile, a smart speaker, a robot, or smart glasses.
Refer to
The front cover 101 may be a glass cover, and a display 194 is disposed below the front cover 101. A structure corresponding to an input/output component may be disposed on a periphery of the housing 100A. For example, an opening 105A corresponding to a front-facing camera and/or an opening 106 corresponding to a receiver are disposed at the top of the front cover 101. A button 190 may further be disposed on one side of the frame 103. An opening 107 corresponding to a microphone, an opening 108 corresponding to a speaker, and an opening 109 corresponding to a USB interface are disposed at the bottom of the frame 103. An opening 105B corresponding to a rear-facing camera may further be disposed at the top of the rear cover 102. Certainly, there may be another structure disposed around the housing 100A. This is not specifically limited in this embodiment of this application.
Further, a cavity may be formed inside the housing 100A. The foregoing internal components may be accommodated in the cavity. For example, as shown in
It should be noted that a filter, a low noise amplifier, an audio codec, an internal memory, a sensor, an inductor, a capacitor, and the like may further be disposed on the PCB 110. Herein, to clearly display this embodiment of this application, the filter, the low noise amplifier, the audio codec, the internal memory, the sensor, the inductor, and the capacitor are not shown in
For example, refer to
Specifically,
Further, the processing circuit 40 may further provide a predetermined envelope signal ET_DAC41 to the envelope tracking modulator ETM 41 and the envelope tracking modulator ETM 42.
The envelope tracking modulator ETM 41 is configured to supply power to the power amplifier PA 41 based on the predetermined envelope signal ET_DAC41. When the first radio frequency signal TX41 is in a bandwidth range A (for example, when the first radio frequency signal TX41 is in a bandwidth range of a frequency band of a 4G network), the power amplifier PA 41 is configured to: amplify output power of the first radio frequency signal TX41 based on a power supply voltage Vpa41 output by the envelope tracking modulator ETM 41, and output a first amplified output signal RF_out41.
The envelope tracking modulator ETM 42 is configured to supply power to the power amplifier PA 42 based on the predetermined envelope signal ET_DAC41. When the first radio frequency signal TX41 is in a bandwidth range B (for example, when the first radio frequency signal TX41 is in a bandwidth range specified by medium frequency bands n41, n77, n78, and n79 of a 5G network), the power amplifier PA 42 is configured to: amplify the output power of the first radio frequency signal TX41 based on a power supply voltage Vpa42 output by the envelope tracking modulator ETM 42, and output a second amplified output signal RF_out42.
In some possible implementations, refer to
In some possible implementations, the processing circuit 111 shown in
During actual application,
It should be noted that the foregoing one or more communication technologies can be understood as one or more mobile communication technologies, for example, a global system for mobile communications (global system for mobile communications, GSM), a general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time-division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), an emerging wireless communication technology (which may also be referred to as a fifth generation mobile communication technology, English: 5th generation mobile networks or 5th generation wireless systems, 5th-Generation, or 5th-Generation New Radio, and may be briefly referred to as 5G, a 5G technology, or 5G NR), and the like. A wireless communication technology may include a wireless local area network (wireless local area network, WLAN) (for example, a wireless fidelity (wireless fidelity, Wi-Fi) network), Bluetooth (Bluetooth, BT), a global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), a near field communication (near field communication, NFC) technology, an infrared (infrared, IR) technology, or the like.
Certainly, the processing circuit 11 may further include an application circuit. The application circuit may include one or more processors. For example, the application circuit may include a circuit such as, but not limited to, one or more single-core or multi-core processors. The (one or more) processors may include a combination of a general-purpose processor and a dedicated processor (for example, a graphics processing unit or an application processor), such as an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a neural-network processing unit (neural-network processing unit, NPU), a video codec, or a digital signal processor (digital signal processor, DSP). These processors may be coupled to a memory/storage or may include a memory/storage, and may be configured to execute instructions stored in the memory/storage to enable various applications or systems to be run on an electronic device 100.
In some possible implementations, the baseband circuit and the radio frequency circuit may be integrated, in an independent device, with another component in the processing circuit 111. Alternatively, the baseband circuit and the radio frequency circuit may be independent devices independent of the processing circuit 111. In some embodiments, one baseband circuit and one radio frequency circuit may be integrated in one independent device, and the independent device and the processing circuit 111 are separately disposed.
During specific application, the foregoing baseband circuit may include a circuit such as, but not limited to, one core processor. The baseband circuit (having multiple cores or more single cores) may include one or more baseband processors or control logic, and these processors or the control logic generates a baseband signal used for a transmit path of the radio frequency circuit. The baseband circuit may be coupled to an application circuit interface, to generate and process the baseband signal and control an operation of the radio frequency circuit.
In some possible implementations, the baseband circuit may include a third generation (3G) baseband processor, a fourth generation (4G) baseband processor, a fifth generation (5G) baseband processor, or another future baseband processor. The baseband circuit may process various radio control functions used for communication between the radio frequency circuit and one or more wireless networks.
In some other implementations, some or all functions of the baseband processor may be included in a module stored in the memory, and may be executed by a central processing unit (CPU). The radio control functions may include but is not limited to signal modulation/demodulation, encoding/decoding, radio frequency shifting, and the like.
During actual application, a modulation/demodulation function of the baseband circuit may include a function such as fast Fourier transform (fast Fourier transform, FIT), precoding, or constellation mapping/demapping. An encoding/decoding function of the baseband circuit may include a function such as convolution, tail-biting convolution, turbo, Viterbi, or low-density parity check (low-density parity check, LDPC) encoder/decoder. Certainly, implementations of the foregoing modulation/demodulation and encoder/decoder functions are not limited to these examples, and another suitable function may be included in another implementation.
In some implementations, the baseband circuit may further include one or more audio digital signal processors (digital signal processors, DSPs). The (one or more) audio DSPs may include an element for compression/decompression and echo cancellation, and may include another suitable processing element in another implementation.
In some implementations, components in the baseband circuit may be suitably combined in a single chip machine or a single chipset, or may be arranged on a same PCB. In addition, some or all components of the baseband circuit and the application circuit may be disposed on a system on chip (system on chip, SOC).
With development of the wireless communication technology, the baseband circuit may support one or more wireless communication technologies. In this case, the baseband circuit may support communication with an evolved universal terrestrial radio access network (evolved universal mobile telecommunication system terrestrial radio access network, E-UTRAN) or another wireless metropolitan area network (wireless metropolitan area network, WMAN), a wireless local area network (wireless local area network, WLAN), a wireless personal area network (wireless personal area network communication technologies, WPAN), or the like. The baseband circuit configured to support a plurality of wireless communication protocols may be referred to as a multi-mode baseband circuit.
It should be noted that because functions of the electronic device 100 are increasingly complete, a quantity of internal components of the electronic device 100 is also increasing. In this case, a cavity 104 may further include a sensor, for example, a pressure sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, an optical proximity sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, or a bone conduction sensor.
With development of communication technologies, a fifth generation mobile communication system (5G) has been widely considered as a next generation wireless communication technology that surpasses a current third generation (3G) communication technology (for example, WCDMA) and fourth generation (4G) communication technology (for example, long term evolution LTE). Compared with wireless communication systems of a 3G communication technology and a 4G communication technology, a 5G wireless communication system provides a higher data rate and a lower latency. In addition, a radio frequency signal of a 5G communication system covers a wider bandwidth range, including a 5G low frequency band (band) (for example, lower than 1 GHz), a 5G medium frequency band (for example, 1 GHz to 6 GHz), and a 5G high frequency band (for example, higher than 24 GHz). Different communication technologies specify different frequency bands and different maximum bandwidths. For example, a maximum bandwidth specified in a 2G standard is 200 kHz (an uplink bandwidth is less than 100 kHz, and the uplink bandwidth is an uplink bandwidth allocated by an operator), a maximum bandwidth specified in a 3G standard is 10 MHz (an uplink bandwidth is less than 2 kHz), a maximum bandwidth specified in a 4G standard may reach 100 MHz (an uplink bandwidth may reach 20 MHz), and a maximum bandwidth specified in a 5G standard may reach 1 GHz to 2 GHz (an uplink bandwidth may reach at least 100 MHz). It is common that a same operator can simultaneously operate communication systems of a plurality of different standards. A plurality of different communication technologies can be simultaneously applied to a same electronic device having a mobile communication function and/or a wireless communication function. In addition, in a same communication technology, bandwidth ranges of different frequency bands can differ greatly. These electronic devices usually perform corresponding processing on radio frequency (radio frequency, RF) signals. For example, before the radio frequency signal is transmitted, a power amplifier (power amplifier, PA) needs to be used to increase output power of the radio frequency signal (for example, maintain sufficient energy per bit).
A service life of an electronic device is closely related to a battery capacity and system efficiency. Against a current background that the battery capacity cannot be expanded anymore while power consumption of another part in the electronic device becomes increasingly large, improving transmit efficiency of a radio frequency part, especially a radio frequency PA system that occupies a large proportion of power consumption, is highly important for prolonging a service life of a terminal.
To resolve the foregoing problem, an embodiment of this application provides a wireless communication system, including: a processing circuit 501, at least one linear amplification circuit LA, a switch amplification circuit SA, at least one first filter capacitor C1, and at least one power amplifier PA 1. With reference to
Specifically, the processing circuit 501 is configured to: output a first radio frequency signal TX41 of a first transmit signal BS1, and output a first envelope signal ET1_DAC41 and a first drive signal DR1 of the first transmit signal BS1. The first drive signal DR1 includes a switch signal of the switch amplification circuit or a second envelope signal ET2_DAC41. The switch signal of the switch amplification circuit is generated by the processing circuit 501 based on the second envelope signal ET2_DAC41. The linear amplification circuit LA is configured to: receive the first envelope signal ET1_DAC41, and output a first power supply voltage to the first node a. The switch amplification circuit SA is configured to: receive the first drive signal DR1, and output a second power supply voltage to the first node a. The power amplifier PA 1 is configured to amplify the first radio frequency signal TX41 based on the first power supply voltage and the second power supply voltage to generate a first amplified output signal RF_out41.
It should be noted that the first filter capacitor C1 can filter out a low frequency part and a direct current part in the first envelope signal ET1_DAC41, or filter out a low frequency part and a direct current part in the first power supply voltage. In addition, as shown in
With reference to the wireless communication system shown in
In addition, as shown in
In another solution, with reference to
In another solution, with reference to
In another solution, as shown in
In another example, as shown in
In another example, transmission paths of subsequent hardware channels of the first envelope signal ET1_DAC41 and the second envelope signal ET2_DAC41 are different, where the first envelope signal ET1_DAC41 is input to the LA, and the second envelope signal ET2_DAC41 is input to the SA. Therefore, a difference in hardware causes a phase difference between signals at the output ends of the LA and the SA and an amplitude loss. Therefore, refer to
In addition, it should be noted that functions shown in
In the wireless communication system provided in the foregoing solution, in addition to improving the EMT 502 used as a power supply circuit in the analog domain, in the digital domain, the processing circuit 501 further needs to be capable of separately generating, based on the first transmit signal BS1, the first envelope signal ET1_DAC41 provided to the LA and the first drive signal DR (which, for example, may be the second envelope signal ET2_DAC41) provided to the SA. In other words, the processing circuit 501 is also correspondingly improved.
In another solution, to directly adapt to the processing circuit 40 provided in
The second analog low-pass filter AF3 is configured to filter out a high frequency part in a predetermined envelope signal ET_DAC41 received from a processing circuit 501, to generate a second envelope signal ET2_DAC41. The first analog low-pass filter AF 2 is configured to perform delay adjustment on the predetermined envelope signal ET_DAC41 received from the processing circuit 501, to generate a first envelope signal ET1_DAC41. The predetermined envelope signal ET_DAC41 is generated by the processing circuit based on a first transmit signal BS1. The linear amplification circuit LA is configured to: receive the first envelope signal ET1_DAC41, and output a first power supply voltage to the first node a. The switch amplification circuit SA is configured to: receive the second envelope signal ET2_DAC41, and output a second power supply voltage to the first node a. The power amplifier PA 1 amplifies, based on the first power supply voltage and the second power supply voltage, a first radio frequency signal TX41 generated by the processing circuit 501 based on the first transmit signal BS1. The first analog low-pass filter AF 2, the second analog low-pass filter AF 3, the linear amplification circuit LA, the switch amplification circuit SA, and the first filter capacitor C1 form an EMT 502 of the PA 1. The first filter capacitor C1 is configured to: filter out a low frequency part and a direct current part in the first envelope signal ET1_DAC41, or filter out a low frequency part and a direct current part in the first power supply voltage.
Compared with an example provided in
During actual application,
In some possible implementations,
The foregoing baseband circuit 301, radio frequency circuit 302, packaged die 303a, and packaged die 304a may form a chipset (chipset), to process to-be-transmitted data and then transmit the processed data by using an antenna circuit. The chipset is a group of integrated circuits that work together.
In an embodiment of this application, the foregoing wireless communication system may further support a beamforming (beamforming) architecture. In one beamforming architecture, when a processing circuit 501 transmits a same radio frequency signal TX41 on a plurality of channels, as shown in
In an architecture such as MIMO that supports dual-channel or multi-channel transmission, the processing circuit 501 may provide radio frequency signals of a plurality of channels: a TX41, a TX42, . . . , or a TX4n. Refer to
In addition, in a scenario of a plurality of transmit channels, for example, in an uplink multiple-input multiple-output (multiple-input multiple-out, MIMO) or uplink carrier aggregation (carrier aggregation, CA) scenario, the processing circuit 501 may provide radio frequency signals of a plurality of channels, for example, the TX41 or the TX42. The processing circuit 501 may transmit a same radio frequency signal on some channels, and transmit different radio frequency signals on the other channels. Refer to
In addition, as shown in
As shown in
In the solution described in
To avoid a limitation on the maximum value or the minimum value of the output voltage of the SA, a multi-voltage SA is provided. Refer to
In addition, when a second power supply voltage with a higher frequency is required, the SA may be a multi-phase switch amplification circuit shown in
In addition, in another solution, refer to
In the foregoing embodiments, the description of each embodiment has respective focuses. For a part that is not described in detail in an embodiment, refer to related descriptions in other embodiments.
Although this application is described with reference to specific features and embodiments thereof, it is clear that various modifications and combinations may be made to them without departing from the scope of this application. Correspondingly, this specification and accompanying drawings are merely example descriptions of this application defined by the appended claims, and are considered as any of or all modifications, variations, combinations, or equivalents that cover the scope of this application. Obviously, a person skilled in the art can make various modifications and variations to this application without departing from the scope of this application. In this way, this application is intended to cover these modifications and variations of this application provided that they fall within the scope of the claims of this application and their equivalent technologies.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110625120.0 | Jun 2021 | CN | national |
This application is a National Stage of International Application No. PCT/CN2022/083788, filed on Mar. 29, 2022, which claims priority to Chinese Patent Application No. 202110625120.0, filed on Jun. 4, 2021, both of which are hereby incorporated by reference in their entireties.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/083788 | 3/29/2022 | WO |
