The subject matter herein generally relates to power supply circuits.
Fans are arranged in electronic devices to dissipate heat. Power supply circuits are used to provide power to the fans.
Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.
Numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.
Several definitions that apply throughout this disclosure will now be presented.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.
The present disclosure is described in relation to a power supply circuit 100.
The first power supply module 10 can comprise a fuse FS1, a power input terminal P12V3, and a diode D1. An anode of the diode D1 is coupled to the power input terminal P12V3 through the fuse FS1. A cathode of the diode D1 is coupled to the power pin VCC of the connector 10.
The second power supply module 20 can comprise a fuse FS2, a diode D2, three electronic switches Q1, Q2, and Q3, a trigger U1, two resistors R1, R2, a power input terminal P3V3, and a power input terminal P3V3_AUX. A control terminal of the electronic switch Q1 is coupled to the anode of the diode D1. A first terminal of the electronic switch Q1 is coupled to the power input terminal P3V3 through the resistor R1. A second terminal of the electronic switch Q1 is coupled to ground. A control terminal of the electronic switch Q2 is coupled to the first terminal of the electronic switch Q1. A first terminal of the electronic switch Q2 is coupled to the power input terminal P3V3 through the resistor R2. A second terminal of the electronic switch Q2 is coupled to ground. An input terminal of the trigger U1 is coupled to the first terminal of the electronic switch Q2. A power terminal of the trigger U1 is coupled to the power input terminal P3V3_AUX. A ground terminal of the trigger U1 is coupled to ground. A control terminal of the electronic switch Q3 is coupled to an output terminal of the trigger U1. A first terminal of the electronic switch Q3 is coupled to the power input terminal P12V3. An anode of the diode D2 is coupled to a second terminal of the electronic switch Q3 through the fuse FS2. A cathode of the diode D2 is coupled to the power pin VCC of the connector 10.
In at least one embodiment, the fuse FS1 is a resettable fuse used to protect against over-current.
In operation, the power input terminal P12V3 supplies power to the power pin VCC of the connector 10 through the fuse FS1 and the diode D1. The fuse FS1 disconnects the anode of the diode D1 from the power input terminal P12V3 when a current flowing through the fuse FS1 exceeds a certain limit. No voltage is output to the control terminal of the electronic switch Q1 and the electronic switch Q1 is deactivated. The electronic switch Q2 is instantly activated and the output terminal of the trigger U1 outputs a low level signal when the input terminal of the trigger U1 receives a low level signal. The electronic switch Q3 is activated, and the power input terminal P12V3 supplies power to the power pin VCC of the connector 10 through the fuse FS2 and the diode D2.
The fuse FS1 connects the anode of the diode D1 to the power input terminal P12V3 when the current flowing through the fuse FS1 returns to a safe value. The control terminal of the electronic switch Q1 is at a high level and the electronic switch Q1 is activated. The electronic switch Q2 is instantly deactivated and the output terminal of the trigger U1 outputs a high level signal when the input terminal of the trigger U1 receives a high level signal. The electronic switch Q3 is deactivated, and no current flows through the fuse FS2 and the diode D2. The power input terminal P12V3 supplies power to the power pin VCC of the connector 10 through the fuse FS1 and the diode D1.
The electronic switch Q5 is activated when the power input terminal P12V3 supplies power to the power pin VCC of the connector 10 through the fuse FS2 and the diode D2. The electronic switch Q6 is deactivated. The input terminal of the trigger U1 receives a high level signal, and the output terminal of the trigger U1 outputs a high level signal to the GPIO pin GPIO1 of the IBMC 5. The pulse pin PWM of the IBMC 5 outputs a pulse signal to the control pin PWM of the connector 10, through the electronic switches Q7 and Q8. The first measuring pin TACH1 and a second measuring pin TACH2 of the connector 10 output speed signals of a fan installed on the connector 10 to the first speed pin TACH1 and the second speed pin TACH2 of the IBMC 5, for proving that the power supply circuit 100 is working normally.
The fuse FS2 disconnects the anode of the diode D2 from the power input terminal P12V3 when a current flowing through the fuse FS1 exceeds a certain limit. The fan on the connector 10 stops operation. The first measuring pin TACH1 and a second measuring pin TACH2 of the connector 10 stop outputting the speed signals of a fan to the first speed pin TACH1 and the second speed pin TACH2 of the IBMC 5, for proving that the power supply circuit 100 is malfunctioning. Meanwhile, no voltage is output to the control terminal of the electronic switch Q5 and the electronic switch Q5 is deactivated. The electronic switch Q6 is activated. The input terminal of the trigger U1 receives a low level signal, and the output terminal of the trigger U1 outputs a low level signal to the GPIO pin GPIO1 of the IBMC 5. The pulse pin PWM of the IBMC 5 stops outputting the pulse signal to the control pin PWM of the connector 10.
In at least one embodiment, the electronic switches Q1, Q2, Q5 and Q6 are N-channel field effect transistors, the electronic switch Q3 is a P-channel field effect transistor, and the electronic switches Q7 and Q8 are NPN bipolar junction transistors.
The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a power circuit. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size and arrangement of the parts within the principles of the present disclosure up to, and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.
Number | Date | Country | Kind |
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2013102908030 | Jul 2013 | CN | national |