1. Technical Field
The present disclosure relates to a power supply circuit.
2. Description of Related Art
Fans are used for heat dissipation in a server. However, if the fans cannot get power, the fans stop operating, and the heat can damage the server.
Therefore, there is room for improvement in the art.
Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views.
Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views.
The power supply circuit 10 comprises a connector 30, a speed adjusting circuit 40, a speed feedback circuit 50, a control module 100, a switching module 200, a first power source 300, and a second power source 301. The connector 30 is connected to the fan 20. The connector 30 comprises a speed pin TACH, a modulation pin PWM, a first power pin VCC1, a second power pin VCC2, and a ground pin GND.
The control module 100 comprises an integrated baseboard management controller (IBMC) 101, a Schmitt trigger 102, a platform controller hub (PCH) 103, and an AND gate 104. The IBMC 101 comprises a speed pin TACH1, a signal pin GPIO, and a modulation pin PWM1. The speed pin TACH1 receives speed signals of the fan 20 from the speed pin TACH of the connector 30 through the speed feedback circuit 50. The signal pin GPIO is connected to an input of the Schmitt trigger 102. An output of the Schmitt trigger 102 is connected to a first input B of the AND gate 104. The modulation pin PWM1 is connected to the modulation pin PWM of the connector 30 through the speed adjusting circuit 40.
A power good pin PWRGD of the PCH 103 is connected to a second input A of the AND gate 104. An output of the AND gate 104 is connected to the switching module 200. When the server starts to operate, the PCH 103 outputs high level signals, such as logic 1, through the power good pin PWRGD.
The switching module 200 comprises a first electronic switch Q1, a second electronic switch Q2, and an inverter 201.
A first terminal of the first electronic switch Q1 is connected to the output of the AND gate 104. A second terminal of the first electronic switch Q1 is connected to the first power source 300. A third terminal of the first electronic switch Q1 is connected to the first power pin VCC1 of the connector 30.
A first terminal of the second electronic switch Q2 is connected to an output of the inverter 201. A second terminal of the second electronic switch Q2 is connected to the second power source 301. A third terminal of the second electronic switch Q2 is connected to the second power pin VCC2 of the connector 30. An input of the inverter 201 is connected to the output of the AND gate 104.
In the embodiment, the first and second electronic switches Q1 and Q2 are n-channel metal-oxide-semiconductor field effect transistors (MOSFETs). The first terminals of the first and second electronic switches Q1 and Q2 are corresponding to gates of the MOSFETs. The second terminals of the first and second electronic switches Q1 and Q2 correspond to sources of the MOSFETs. The third terminals of the first and second electronic switches Q1 and Q2 correspond to drains of the MOSFETs.
The speed feedback circuit 50 comprises resistors R1-R4, a diode D1, a capacitor C1, and a power terminal P12V3. The power terminal P12V3 is connected to the speed pin TACH of the connector 30 through the resistor R1. The power terminal P12V3 is also connected to a cathode of the diode D1. An anode of the diode D1 is connected to the speed pin TACH of the connector 30. The speed pin TACH is connected to the speed pin TACH1 of the IBMC 101 through the resistors R2 and R4 in that order. A node between the resistors R2 and R4 is grounded through the capacitor C1. The resistor R3 and the capacitor C1 are connected in parallel.
The speed adjusting circuit 40 comprises resistors R5-R8, a Bipolar Junction Transistor (BJT) Q3 and a BJT Q4, and a power terminal P3V3. The modulation pin PWM1 of the IBMC 101 is connected to the power terminal P3V3 through the resistor R5. The modulation pin PWM1 of the IBMC 101 is also connected to a base of the BJT Q3 through the resistor R6. An emitter of the BJT Q3 is grounded. A collector of the BJT Q3 is connected to the power terminal P3V3 through the resistor R7. The collector of the BJT Q3 is also connected to a base of the BJT Q4. An emitter of the BJT Q4 is grounded. A collector Q4 is connected to the power terminal P3V3 through the resistor R8 and is also connected to the modulation pin PWM of the connector 30.
In the embodiment, the BJTs Q3 and Q4 are NPN BJTs.
When the server starts to operate, the IBMC 101 outputs a high level signal the first input B of the AND gate 104 through the Schmitt trigger 102. The PCH 103 outputs a high level signal to the second input A of the AND gate 104. The AND gate 104 outputs a high level signal to the first terminal of the first electronic switch Q1. The second terminal of the first electronic switch Q1 is connected to the third terminal of the first electronic switch Q1. The first power source 300 is connected to the fan 20. The IBMC 101 receives speed signals from the fan 20 through the speed feedback circuit 50. When a speed of fan 20 is not zero, the IBMC 101 outputs the high level signal continuously to keep the connection between the first power source 300 and the fan 20. The AND gate also outputs the high level signal to the input of the inverter 201. The inverter 201 outputs a low level signal, such as logic 0, to the first terminal of the second electronic switch Q2. The second terminal of the second electronic switch Q2 and the third terminal of the second electronic switch Q2 are disconnected. The second power source 301 is disconnected from the fan 20.
When the first power source 300 cannot supply power to the fan 20, the speed of the fan 20 is zero. The IBMC outputs a low level signal through the signal pin GPIO. The low level signal is output to the first input B of the AND gate 104 through the Schmitt trigger 102. The PCH 103 outputs the high level signal continuously to the second input B of the AND gate 104. The AND gate 104 outputs a low level signal to the first terminal of the first electronic Q1. The second terminal of the first electronic Q1 and the third terminal of the first electronic Q1 are disconnected. The first power source 300 is disconnected from the fan 20. The AND gate 104 also outputs the low level signal to the input of the inverter 201. The inverter 201 outputs a high level signal to the first terminal of the second electronic switch Q2. The second terminal of the second electronic switch Q2 is connected to the third terminal of the second electronic switch Q2. The fan 20 is connected to the second power source 301. The second power source 301 supplies power for the fan 20.
While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
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2013 1 0728141 | Mar 2013 | CN | national |
Number | Name | Date | Kind |
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20090162039 | Zou | Jun 2009 | A1 |
20090175602 | Qian | Jul 2009 | A1 |
20140119882 | Chen | May 2014 | A1 |
20140184126 | Zhou | Jul 2014 | A1 |
Number | Date | Country | |
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20140255213 A1 | Sep 2014 | US |