This Summary is provided to introduce, in a simplified form, a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
An embodiment of a power-supply controller includes a control circuit and a detection circuit. The control circuit has a signal characteristic, and is operable to generate a regulated output signal. The detection circuit is operable to detect a change in the regulated output signal, and to alter the signal characteristic of the control circuit in response to the detected change.
For example, in an embodiment, such a dual-mode (e.g., steady-state and transient modes) power-supply controller may be part of a switching power supply that provides a regulated output voltage to a load. The detection circuit may detect a transient (e.g., a sudden increase or decrease) in the regulated output voltage due to a transient in the current being drawn by the load, and, in response to the transient in the output voltage, may temporarily increase the bandwidth of the control circuit so that the control circuit can more quickly bring the output voltage back to its regulated value (transient mode). After the temporary increase in the control circuit's bandwidth, the detection circuit allows the bandwidth of the control circuit to return to a lower value. During steady-state operation of the power supply (steady-state mode), this lower bandwidth may allow the control circuit to filter out more noise, and to thus reduce jitter in the switching of the power-supply phase(s), as compared to a control circuit with a higher steady-state bandwidth.
The power supply 10 includes a power-supply controller 14, at least one power-supply phase 161-16n, and at least one filter capacitor 18, which may be modeled as an ideal capacitor 20 an equivalent series resistance (ESR) 22. The controller 14, phases 161-16n, capacitor 18, and a feedback path 23, which couples Vout to an input node of the controller, together form a power-supply control loop 24. Although the load 12 is typically not considered part of the control loop 24, the impedance of the load may affect the frequency response of the control loop.
The power-supply controller 14 includes a reference generator 26, a feedback circuit 28, a phase driver 30, high-side NMOS switching transistors 321-32n, low-side NMOS switching transistors 341-34n, and a transient detector 36.
The reference generator 26 is operable to generate a stable reference signal, in this embodiment a reference voltage Vref.
The feedback circuit 28 is operable to receive the regulated output signal Vout and the reference signal Vref, and, from these signals, is operable to generate a signal CONTROL, which the feedback circuit generates to maintain Vout substantially equal to Vref (or to a voltage derived from Vref). The feedback circuit 28 may also include compensation for stabilizing the control loop 24, and the feedback circuit or another portion of the power-supply controller 14 may have the ability to set this compensation according to the impedance of the load 12 so as to maintain the stability of the control loop 24 over a range of load impedances. Furthermore, the feedback circuit 28 is operable to receive a transient-detection signal TD from the transient detector 36, and is operable to alter the control-loop compensation in response to TD. For example, as discussed below, the feedback circuit 28 may temporarily increase its own bandwidth, and thus may temporarily increase the bandwidth of the control loop 24, in response to the signal TD.
The phase driver 30 controls the switching of the transistors 32 and 34 under the direction of the signal CONTROL. More specifically, the phase driver 30 controls the duty cycles of the phases 161-16n—the duty cycle of a phase is the percentage of the phase's switching period during which the corresponding high-side transistor 32 is conducting (i.e., is “on”)—so as to maintain Vout substantially equal to Vref or to a voltage derived from Vref (e.g., with a voltage divider).
Each of the high-side NMOS transistors 321-32n has a drain coupled to receive a first input voltage Vin, a gate coupled to the phase driver 30, and a source coupled to an input of a respective phase 161-16n.
Each of the low-side NMOS transistors 341-34n has a drain coupled to an input of a respective phase 161-16n, a gate coupled to the phase driver 30, and a source coupled to a second input voltage, which is ground in this embodiment.
The transient detector 36 detects a relatively sudden change in the current Iload drawn by the load 12, and generates the signal TD in response to detecting such a change. Furthermore, the detector 36 may detect not only the presence of a load transient, but also may detect the polarity of the transient. That is, the detector 36 may determine whether the load current Iload has increased or decreased. The detector 36 may detect a change in Iload by detecting a change in Vout. That is, if the detector 36 senses that the magnitude of Vout has increased above to a first threshold, then the detector determines that Iload has decreased to below a second threshold. Conversely, if the detector 36 senses that the magnitude of Vout has decreased to below a third threshold, then the detector determines that Iload has increased to above a fourth threshold. Furthermore, the detector 36 may generate TD only temporarily, e.g., for a specified duration, in response to a load transient so that the feedback circuit 28 returns the transient-mode bandwidth of the control loop 24 to its steady-state-mode value after the transient in Iload has sufficiently dissipated. Alternatively, the detector 36 may generate TD until load or Vout has returned to within a respective threshold window.
Each phase 161-16n includes at least a respective filter inductor 381-38n, each inductor having a respective input end coupled to the drain of the corresponding high-side transistor 321-32n and to the source of the corresponding low-side transistor 341-34n, and having a respective output end coupled to the output node 39 on which Vout is present. Although not shown in
The load 12 may be any type of load. For example, the load 12 may be a processor (not shown in
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During steady-state operation, the current Iout, which is the current output by the at least one phase 16, is substantially constant, and the power-supply controller 14 operates in a steady-mode to maintain the amplitude of Vout at a substantially constant value, e.g., 1.1 Volts (V), that is set by Vref.
During a period of transient operation that commences when the load current Iload increases to above a first threshold level over a relatively short period of time (e.g., microseconds or nanoseconds), Vout decreases to below a corresponding second threshold level. The transient detector 36, which may set this second threshold level, detects this decrease in Vout. In response to the detected decrease in Vout, the transient detector 36 generates the signal TD, which causes the power-supply controller 14 to enter a transient mode of operation. In response to the signal TD, the feedback circuit 28 increases its bandwidth (as compared to its bandwidth in the steady-state mode), and thus increases the bandwidth of the control loop 24. With this increased bandwidth, the control loop 24 acts more quickly than it otherwise would to increase Iout toward the new steady-state value of Iload, and to thus raise Vout back toward its regulated value as set by Vref. That is, this increased bandwidth allows the control loop 24 to reduce the length of the transient period as compared to the length that the transient period might have if the control loop retained its lower steady-state bandwidth. The feedback circuit 28 may increase the bandwidth of the control loop 24 for a set time, for example, a time set at least in part by the duration of the signal TD. Alternatively, the feedback circuit 28 may increase the bandwidth of the control loop 24 until the transient detector 36 stops generating the signal TD in response to detecting that Vout has risen above a third threshold, which may be the same as or different than the second threshold.
Similarly, during a period of transient operation that commences when the load current load decreases to below a fourth threshold level over a relatively short period of time, Vout increases to above a corresponding fifth threshold level. The transient detector 36, which may set this fifth threshold level, detects this increase in Vout. In response to the detected increase in Vout, the transient detector 36 generates the signal TD, which, as discussed above, causes the power-supply controller to enter the transient mode of operation. In response to the signal TD, the feedback circuit 28 increases its bandwidth (as compared to its bandwidth in the steady-state mode), and thus increases the bandwidth of the control loop 24. With this increased bandwidth, the control loop 24 acts more quickly than it otherwise would to decrease Iout toward the new steady-state value of Iload, and to thus lower Vout back toward its regulated value as set by Vref. That is, this increased bandwidth allows the control loop 24 to reduce the length of the transient period as compared to the length that the transient period might have if the control loop retained its lower steady-state bandwidth. The feedback circuit 28 may increase the bandwidth of the control loop 24 for a set time as discussed above. Alternatively, the feedback circuit 28 may increase the bandwidth of the control loop until the transient detector 36 stops generating the signal TD in response to detecting that Vout has fallen below a sixth threshold, which may be the same as or different than the fifth threshold.
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The feedback circuit 28 includes a first compensation network 50, a second compensation network 52, an error amplifier 54, and adjusting circuitry 56, which is operable to change the frequency response (and thus the compensation) provided by the first network 50 in response to the signal TD.
The first compensation network 50 generates a feedback signal FB from Vout, and includes a first resistor R1, a first capacitor C1, a second resistor R2 in parallel with the series combination of R1 and C1, a serially coupled second capacitor C2 and NMOS transistor 58, which are in parallel with the series combination of R1 and C1, and an NMOS transistor 60, which is in parallel with C2. As discussed below, the circuitry 56 may activate or deactivate the transistors 58 and 60 to change the frequency response of the network 50. While the transistor 58 is inactive and the transistor 60 is active, the “off” resistance of the transistor 58, the “on” resistance of the transistor 60, and the second capacitor C2 do not affect the frequency response of the network 50. That is, while the transistor 58 is inactive and the transistor 60 is active, the frequency response of the network 50 is substantially set by R1, R2, and C1 only. Specifically, while the transistor 58 is inactive and the transistor 60 is active, the network 50 adds to the control loop 24 in a known manner a zero in the s (Laplace Transform) plane, where the location of this zero is set substantially by R1, R2, and C1. But while the transistor 58 is active and the transistor 60 is inactive, the frequency response of the first network 50 is substantially set by R1, R2, C1, C2, and the “on” resistance RDSON of the transistor 58 such that the first network adds two zeros to the control loop 24, and thus increases the bandwidth of the control loop. That is, while the transistor 58 is inactive and the transistor 60 is active, the control loop 24 has a lower bandwidth (steady-state mode), and while the transistor 58 is active and the transistor 60 is inactive, the control loop has a higher bandwidth (transient mode).
The second compensation network 52, which is coupled between the inverting input node and the output node of the error amplifier 54, includes a third resistor R3, a third capacitor C3, and a fourth capacitor C4 in parallel with the series combination of R3 and C3. The network 52 adds to the control loop 24 two poles in the s plane in a known manner.
The error amplifier 54 may be a conventional, high-gain differential amplifier, such as an operational amplifier. A noninverting input node of the amplifier 54 receives Vref, and the inverting input node receives FB from the first network 50. The amplifier 54 generates the CONTROL signal so that ideally, Vout=FB=Vref for a constant value of out. But in actuality, offset and other errors introduced by the amplifier 54 may cause Vout ˜FB˜Vref for a constant value of Iout.
The adjusting circuitry 56 includes an inverter 62, and an optional fourth resistor R4 and fifth capacitor C5, which, when present, are coupled in parallel between the gate of the transistor 58 and ground. The inverter 62 receives on an input node the transient-detect signal TD from the transient detector 36, and drives the gate of the transistor 60 with an output node. As discussed below, the transient detector 36 generates TD as a digital signal having a low level during the steady-state operating mode of the power supply 10 and transitions TD to a high-level in response to a load transient to cause the power supply to enter its transient operating mode. In an embodiment where R4 and C5 are omitted, while TD is low, the transistor 58 is inactive and the transistor 60 is active, thus causing the control loop 24 to have a lower bandwidth during steady-state operation as discussed above. And while TD is high, the transistor 58 is active and the transistor 60 is inactive, thus causing the control loop 24 to have a higher bandwidth during transient operation as discussed above. Therefore, one may set the duration of the transient operating mode (during which the control loop 24 has a higher bandwidth) by setting the duration of TD. But in an embodiment where R4 and C5 are present, these two components slow the rise and fall times of TD. A result of the slowed fall time of TD is that the transistors 58 and 60 remain active and inactive, respectively, for a longer time (as measured from the moment when TD transitions from a high level) relative to the embodiment where R4 and C5 are omitted. Therefore, one may set the duration of the transient operating mode by selecting the appropriate values of R4 and C5, setting the duration of TD, or both selecting the values of R4 and C5 and setting the duration of TD.
The phase driver 30 includes two comparators 641 and 642, and two switch drivers 661 and 662, one comparator and switch driver per phase 16.
The comparator 641 receives at a noninverting input node the signal CONTROL, and receives at an inverting input node a pulse-width-modulating (PWM) WAVE1, such as a triangle wave, sawtooth wave, or other wave having a frequency Fsw and at least an increasing-amplitude portion and a decreasing-amplitude portion, where the increasing portion, decreasing portion, or both the increasing and decreasing portions may be linear. Although not shown, a circuit for generating PWM WAVE1 may be part of the power-supply controller 14 or may be located elsewhere. At an output node, the comparator 641 generates a signal PWM1, which causes the switch driver 661 to drive the transistors 321 and 341 in a pulse-width-modulated (PWM) manner. Generally, the signal PWM1 has a substantially constant frequency equal to Fsw, and the amplitude of the signal CONTROL modulates the duty cycle of PWM1 in a manner that maintains Vout˜Vref during a steady-state mode of operation, and that drives Vout toward Vref during a transient mode of operation. Because pulse-width modulation is known, it is not discussed further herein.
The comparator 642 is similar in topology and operation to the comparator 641, except that the signal PWM WAVE2 may be out of phase with PWM WAVE1 by 360°/n, where n is the number (two in this embodiment) of phases in the power supply 10. Shifting the phase of PWM WAVE2 by substantially 360°/2=180° relative to the phase of PWM WAVE1 allows the power-supply controller 14 to reduce the amplitude of the ripple component of Vout by driving the power-supply phase 161 180° out of phase relative to the power-supply phase 162.
The switch driver 662 drives the transistors 321 and 341 in a complementary manner in response to the signal PWM1. That is, when the driver 661 activates the transistor 321, it deactivates the transistor 341, and vice versa. In an embodiment, the driver 661 is an inverter. In another embodiment, the driver 661 is conventionally designed to insure that the transistors 321 and 341 are not simultaneously active. Such a design may prevent a large “crow bar” current from flowing from Vin, through the transistors 321 and 341, to ground.
The switch driver 662 drives the transistors 322 and 342 in a complementary manner in response to the signal PWM2 in a manner similar to that described above for the switch driver 661.
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The path 68 detects a transient caused by an increase in the current Iload, and includes a resistor R5, capacitor C6, current source 74, and comparator 76. The current source 72 sets a detection threshold by generating a voltage drop I1·R5 across the resistor R5, such that a threshold voltage Vthreshold1, which is substantially equal to Vout
The path 70 detects a transient caused by an decrease in the current Iload, and includes a resistor R6, capacitor C7, current source 78, and comparator 80. The current source 78 sets a detection threshold by generating a voltage drop I2·R6 across the resistor R6, such that a threshold voltage Vthreshold2, which is substantially equal to Vout
In an embodiment where R4 and C5 of the circuitry 56 are omitted, then the OR gate 72 may be a conventional OR gate that generates TD having a high level (e.g., ˜Vin) if at least one of the comparators 76 and 80 is outputting a high level, and that generates TD having a low level (e.g., ground) if both of the comparators are outputting low levels.
But in an embodiment where R4 and C5 are present, a conventional OR gate 72 may have an output impedance that is much less than R4 while the signal TD has a low level, and this output impedance may effectively negate the intended effect of R4 and C5, this intended effect at least in part being the slowing of the fall time of the signal TD.
Therefore, where R4 and C5 are present, the OR gate 72 may be designed to tristate its output (i.e., present a high output impedance) when the outputs of both the comparators 76 and 80 have low levels. Consequently, when at least one of the comparators 76 and 80 transitions its output to a high level, the OR gate transitions the signal TD to a high level to increase the bandwidth of the control loop 24, and to thus cause the power supply 10 to enter the transient operating mode. But when the at least one comparator transitions its output back to a low level, the OR gate will tristate its output, thus allowing the signal TD to decay from a high level to a low level at a rate that is set by R4 and C5, and thus allowing the power supply 10 to remain in the transient operating mode for a time that is at least partially set by R4 and C5.
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Furthermore, one may design the feedback circuit 28 such that during the transient operating mode of the power supply 10, the bandwidth of the control loop 24 is sufficiently high to allow the control loop to force Vout back to its regulated level (or to within a specified range of its regulated level) within a specified time. Because the power supply 10 operates in the transient mode for only a relatively short period of time, one may design the feedback circuit 28 such that the control loop 24 has a transient-mode bandwidth that is significantly greater than Fsw/2 without causing the power supply to oscillate. For example, one may design the feedback circuit 28 such that the control loop 24 has transient-mode bandwidth of between approximately ⅔·Fsw and 10·Fsw.
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Referring to FIGS. 2 and 5A-5C, the transient mode of operation of an embodiment of the dual-mode power supply 10 is described.
During a transient mode of operation that is initiated by Iload significantly increasing (e.g., a step increase in Iload per
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The system 100 includes at least one computer circuit 102 for performing computer functions, such as executing software to perform desired calculations and tasks. The circuit 102 may include a controller, processor, or one or more other integrated circuits (ICs).
At least one input device 104, such as a keyboard or a mouse, is coupled to the computer circuitry 102 and allows an operator (not shown) to manually input data thereto.
At least one output device 106 is coupled to the computer circuit 102 to provide to the operator data generated by the computer circuit. Examples of such an output device 106 include a printer and a video display unit.
At least one data-storage device 108 is coupled to the computer circuit 102 to store data on or retrieve data from external storage media (not shown). Examples of the storage device 108 and the corresponding storage media include drives that accept hard and floppy disks, tape cassettes, compact disk read-only memories (CD-ROMs), and digital-versatile disks (DVDs).
At least one memory 110 is coupled to the computer circuit 102, and stores data that the computer circuit may generate or on which the computer circuit may operate.
The power supply 10 provides at least one supply voltage to the computer circuit 102, and although not shown, may provide at least one respective supply voltage to at least one of the input device 104, output device 106, storage device 108, and memory 110.
Furthermore, one or at least any two of the power supply 10, computer circuit 102, input device 104, output device 106, storage device 108, and memory 110 may be disposed on a single integrated-circuit (IC) die, or otherwise within a same IC package.
From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Furthermore, where an alternative is disclosed for a particular embodiment, this alternative may also apply to other embodiments even if not specifically stated.
This application claims priority to U.S. Provisional Application Ser. No. 61/102,344 filed on Oct. 2, 2008, which is incorporated by reference.
Number | Date | Country | |
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61102344 | Oct 2008 | US |