Patent Application
20080055795
A full understanding of the invention can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which:
FIGS. 2A and 2B1-2B2 form a block diagram in schematic form of the power supply of the circuit breaker of
As employed herein, the statement that a part is “electrically interconnected with” one or more other parts shall mean that the parts are directly electrically connected together or are electrically connected together through one or more electrical conductors or generally electrically conductive intermediate parts. Further, as employed herein, the statement that a part is “electrically connected to” one or more other parts shall mean that the parts are directly electrically connected together or are electrically connected together through one or more electrical conductors.
As employed herein, the term “number” means an integer greater than or equal to one.
The invention is described in association with a three-pole circuit breaker, although the invention is applicable to a wide range of circuit interrupters having any number of poles.
Referring to
The power supply 12 includes a current transformer (CT) 14 for each pole having a single turn primary coil 16 and a plural turn secondary coil 18 (
The example startup circuit 40 permits the trip unit 10 to power up when the power signal ST298 from the output 42 of the cathode of diode 64 to the switching resistor input 34 reaches about 16 VDC. The burden resistor 30 burdens the power coils 14 with the approximate trip unit load at about 16 VDC. This allows the trip unit 10 to power up at relatively lower primary currents of the power coils 14. The signal SHUTDOWN/44 (at SHDN/ input 56 of FIG. 2B2) holds the switching regulator 32 in the shutdown mode 36 until sufficient power from the power coils 14 is available. An example of the switching regulator 32 is a model LT3434 step-down switching regulator marketed by Linear Technology of Milpitas, Calif.
Normally, the load current of the trip unit 10 is provided from about 30 mA at 20 VDC and 15 mA at 40 VDC at power signal ST298. Normally, the load current of the trip unit 10 is about 25 mA pulled from the +5V output 38. This represents about 20 mA from power signal ST298 running at 20 VDC and about 15 mA from ST2 when running at 40 VDC. The important point is that the current requirement from ST2 decreases as the voltage of ST2 increases because of the switching regulator 32 providing the +5V. Without the startup circuit 40, as primary current increases, the voltage at ST2 will be pulled down to the minimum operating voltage of the switching regulator 32 as it uses all the available current in an attempt to meet its demand (i.e., startup of the trip unit 10 at the regulator's specified output voltage). The trip unit 10 will finally startup when the available current is large enough to run the trip unit 10 at the regulator's minimum operating voltage.
If the voltage at ST2 is allowed to increase above the switching regulator's minimum voltage, startup at lower primary or secondary currents is possible. However, the increase in voltage at ST2 must be restrained somewhat since CT voltages increase rapidly with no burden resistors. In the case of no burden resistor, the normal operating voltage would be reached before sufficient operating current is available. By placing a resistive burden across the full wave rectified CT output, which is representative of the trip unit load current, while holding the trip unit switching regulator 32 off, it is possible to start the trip unit 10 at a lower current. When the desired operating voltage at ST2 is reached, if the burden resistor is chosen properly, then the switching regulator 32 can be taken out of shutdown at the same time that the burden resistor is removed. If this is done, then the trip unit 10 will startup with no change in the ST2 voltage.
As shown in FIG. 2B1, a zener diode 46 provides temperature compensation. If the ambient temperature increases, then the zener voltage increases and the corresponding reference voltage 48 (e.g., without limitation, about +1.0 VDC) increases. This requires that the voltage of the signal ST298 is suitably high before the SHUTDOWN/ signal 44 is deactivated by the comparator 50 and the FET 28.
Referring again to
This is accomplished by initially (at relatively very low primary current) burdening the CT secondary 18 with the resistive load of burden resistor 30 rather than with the switching regulator 32 and the trip unit 10. This resistive load is electrically interconnected with the CT secondary 18 (and the rectified CT voltage 20 thereof) by the FET 28 tied to circuit ground 52. The resistance of the burden resistor 30 is selected such that its power dissipation at minimum operating conditions is equal to or slightly greater than that of the trip unit 10 operating under the same conditions. As shown in FIG. 2B1, the drain 54 of the FET 28 is electrically connected to the shutdown pin (SHDN/) 56 of the switching regulator 32, thereby keeping it in a high impedance state when the FET 28 is off. A relatively very low power comparator circuit 58 with its own simple and independent power supply 102 provided by resistor 60, zener diode 46 and capacitor 62 is used to sense the rectified CT voltage ST126 through diode 64 at power signal ST298. When the rectified CT voltage ST126 reaches a predetermined level, which is sufficient to power the trip unit 10, the FET 28 is turned off. This removes the resistive burden of resistor 30 and takes the switching regulator 32 out of its shutdown mode 36. As a result, the trip unit 10 “starts-up” cleanly at a relatively lower primary current than without such a circuit and without any “false starts”. Otherwise, a false start would occur when the power supply 12 turns on and then turns off because not quite enough power is available to maintain its operation.
The trip unit 10 presents a resistance to the switching regulator 32 (e.g., on the outputs +5 VDC and −5 VDC). The burden impedance, resistor 30, is structured to approximate the resistance or impedance presented by the trip unit 10. The CT secondary 18 (
Referring to FIGS. 2A and 2B1-2B2, the power supply 12 of the circuit breaker 2 of
Referring to FIGS. 2B1-2B2, the full-wave rectified signal FWR_PWR 68 is preferably approximately limited to a suitable magnitude by a regulator circuit 72 including a comparator circuit 74 and a FET 76. The reference signal 78 for the comparator circuit 74 is established by resistors 80,82 that suitably divide the output voltage (+5 VDC) 84 of the power supply output 38. When the magnitude of the full-wave rectified signal FWR_PWR 68 is too large, the voltage at node 86 exceeds the voltage of the reference signal 78, which turns the output of comparator 88 on. This turns the FET 76 on to further load the full-wave rectified signal FWR_PWR 68, in order to reduce the voltage thereof. The voltage at node 86 is responsive to the voltage of the full-wave rectified signal FWR_PWR 68 through diode 90, diode 64, zener diode 92 and resistor 94. The rectified voltage (ST1) 26, which is established at output 25 from the full-wave rectified signal FWR_PWR 68 through the diode 90, is suitably maintained by capacitors 95. The rectified voltage (ST2) 98 at output 42, which is established from the rectified voltage (ST1) 26 through the diode 64, is suitably maintained by capacitors 96. For example, the trip unit 10 will power up before the regulator circuit 72 starts regulating (e.g., at about 40 VDC).
The startup circuit burden impedance of resistor 30 is a predetermined resistance structured to provide a first power dissipation at the rectifier output 42. The trip unit 10 (
The startup circuit 40 includes the comparator 50 and an independent, relatively low current power supply 102 formed by the zener diode 46, the resistor 60 and the capacitor 62. The comparator 50 and the power supply 102 receive the rectified voltage ST298 from the rectifier output 42 through the diodes 90 and 64 from the rectified voltage FWR_PWR 68. The comparator 50 is structured to turn the FET 28 off when the rectified voltage FWR_PWR 68 reaches the predetermined value (e.g., without limitation, about +20 VDC), which is sufficient to power the trip unit 10 with the CT burdened by resistor 30, and remove the switching regulator 32 from the shutdown mode 36 thereof.
The startup circuit 40 is structured to maintain the switching regulator shutdown mode 36 at a first voltage and a first current flowing from the CT secondary 18 until a suitable second voltage and a second current develop at the CT secondary 18. The second voltage is greater than the first voltage. For example, for increasing voltage, the startup circuit 40 will turn on at about 20 VDC at ST126 and turn off at about 18 VDC for decreasing voltage at ST1 (i.e., hysteresis is preferably employed). The second current flows from the CT secondary 18 and enables the switching regulator 32 to startup. In accordance with an important aspect of this embodiment, the switching regulator 32 starts up without any “false starts”. Otherwise, a false start would occur when the power supply 12 turns on and then turns off because not quite enough power is available to maintain its operation.
Continuing to refer to FIG. 2B2, the trip unit 10 includes a linear regulator 104 structured to power the trip unit 10. The switching regulator output 106 energizes the linear regulator 104. A first linear regulator circuit 108 provides the +5 VDC output 38 to power microprocessor (μP) 110 and analog trip circuit 111 of
The comparator 50 of the startup circuit 40 has a first input (−) 116 electrically interconnected with the rectifier output 42 through a divider formed by resistors 118,120, and also has a second input (+) 122 with the threshold voltage 48. The zener diode 46 of the startup circuit 40 has a positive temperature coefficient. The zener diode 46 is structured to determine the threshold voltage 48 of the comparator second input (+) 122 through another divider formed by resistors 124,126 and through resistor 128. The positive temperature coefficient of the zener diode 46 provides temperature compensation to increase (decrease) the predetermined value (e.g., without limitation, about +1.0 VDC over the full temperature range) of the threshold voltage 48 responsive to an increase (decrease) in ambient temperature. As a result, the startup circuit 40 removes the burden, exits the switching regulator shutdown mode 36 and powers the trip unit 10 from the switching regulator output 42 when the rectified voltage 68 is greater (less) than the predetermined value (e.g., without limitation, about +20 VDC). The startup circuit comparator 50 and the power supply 102 receive the rectified voltage ST298 from the rectifier output 42. The comparator 50 is structured to turn the gate 130 of the FET 28 off when the voltage of the CT secondary 18 reaches the predetermined value, which is sufficient to power the trip unit 10, and remove the switching regulator 32 from the shutdown mode 36 thereof.
The circuit breaker 2 is tripped by either a digital trip signal 146 from μP 110 or a second trip signal 148 that is derived from the outputs 150,152 of the analog trip circuit 111. An OR gate 154 turns on the gate 156 of the FET 138 to trip the circuit breaker 2 in response to either one of the signals 146,148. The 20PU/ trip signal 158 is disabled by the auxiliary switch 160, which opens about 25 mS after the circuit breaker 2 closes. During that time interval, when the auxiliary switch 160 is closed, the analog trip circuit 111 can trip the circuit breaker 2 responsive to load current greater than or equal to 20 per unit of the circuit breaker rated current. The OR gate 162 (shown in reverse logic form) passes a qualified 20PU/ trip signal 164 to one input of NAND gate 166 (shown in reverse logic form). The other input of NAND gate 166 receives the instantaneous (INST/) trip signal 168 from the output 152 of the analog trip circuit 111. The output of the NAND gate 166 has a combined signal 170 and is electrically connected to one input of NAND gate 172. The other input of the NAND gate 172 has an ENABLE signal 174, which is low whenever the SHUTDOWN/ signal 44 is active (i.e., low). Whenever the SHUTDOWN/ signal 44 is inactive (i.e., high), the voltage of the ENABLE signal 174 is established by the voltage of signal ST298 (which voltage is about one diode drop below the voltage of the signal ST126) and the divider formed by the resistor 30 (FIG. 2B1) and resistor 176. This ensures that the analog trip circuit 111 has sufficient operating voltage before any of its outputs 150,152 are considered by the trip logic 136. The output of the NAND gate 172 is inverted by the NAND gate 178 to output the second trip signal 148. A circuit 180 including NAND gate 182 and diode 184 permits a momentary instantaneous trip signal 168 to initiate the second trip signal 148 of suitable duration.
While specific embodiments of the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the invention which is to be given the full breadth of the claims appended and any and all equivalents thereof.
