BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing a conceivable LSI circuit that is provided with a single power supply step-down circuit integrally having a step-down circuit for normal operation mode and a step-down circuit for standby mode;
FIG. 2 is a timing chart for explaining the operation of the power supply step-down circuit shown in FIG. 1;
FIG. 3 is a system block diagram showing an embodiment of the present invention;
FIG. 4 is a circuit diagram showing a power supply step-down circuit;
FIG. 5 is a timing chart for explaining the operation of the power supply step-down circuit;
FIG. 6 is a circuit diagram showing a pulse generating circuit; and
FIG. 7 is a timing chart for explaining the operation of the pulse generating circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the present invention, an LSI circuit is provided with a single power supply step-down circuit that integrally has a step-down circuit for a normal operation mode (or a first step-down circuit for a first operation mode) and a step-down circuit for a standby mode (or a second step-down circuit for a second operation mode) of the LSI circuit, so as to reduce the area occupied by the power supply step-down circuit. The current consumption of the LSI circuit is smaller in the standby mode than in the normal operation mode. The step-down circuit for the normal operation mode has a low (or lower) resistance, a high (or higher) reaction speed and a large (or larger) current consumption compared to the step-down circuit for the standby mode. The step-down circuit for the normal operation mode is activated only when the operation mode of the LSI circuit is the normal operation mode, so as to step down an input power supply voltage and to output an output voltage. On the other hand, the step-down circuit for the standby mode is activated only when the operation mode of the LSI circuit is the standby mode.
The LSI circuit is provided with an output circuit which maintains the output voltage lower than the input power supply voltage for only a predetermined time when the operation mode of the LSI circuit switches to the standby mode, so that the output voltage does not become the same potential as the input power supply voltage for a long time when the operation mode of the LSI circuit makes a transition from the normal operation mode to the standby mode.
Since the output voltage can be maintained lower than the input power supply voltage for the predetermined time when the operation mode of the LSI circuit switches to the standby mode, it is possible to prevent the relatively high input power supply voltage from being applied to the circuit part within the LSI circuit, which originally should not be applied with the input power supply voltage. Accordingly, it is possible to maintain the reliability and serviceable life of the LSI circuit.
A description will now be given of embodiments of the power supply step-down circuit and the semiconductor device according to the present invention, by referring to FIG. 3 and the subsequent figures.
FIG. 3 is a system block diagram showing an embodiment of the present invention. A semiconductor device 21 has a single power supply step-down circuit 31, a clock generating circuit 32, and a CPU (and/or a logic circuit) 33 that are connected as shown in FIG. 3. Preferably, the power supply step-down circuit 31, the clock generating circuit 32 and the CPU 33 are provided on a common single substrate (that is, on the same substrate). In this embodiment, the power supply step-down circuit 31 integrally has a step-down circuit 31-1 for the normal operation mode and a step-down circuit 31-2 for the standby mode. A predetermined (constant) voltage Vcst and a power supply voltage Vcc are input to the power supply step-down circuit 31. A mode signal MODE which indicates whether or not the operation mode of the semiconductor device 21 is the normal operation mode or the standby mode, is input to the power supply step-down circuit 31 and the clock generating circuit 32. The clock generating circuit 32 generates a clock CLK based on the mode, signal MODE, and inputs the clock CLK to the CPU 33. The power supply step-down circuit 31 switches between the step-down circuits 31-1 and 31-2 depending on the operation mode, and supplies a stepped down output voltage Vo to the CPU 33. For example, the power supply voltage Vcc is 5 V, and the output voltage Vo that is output from the power supply step-down circuit 31 is 1.8 V.
For example, the predetermined voltage Vcst may be obtained from a constant voltage source that generates the predetermined voltage Vcst and has a current consumption that changes based on the power supply voltage Vcc and the mode signal MODE or, obtained from a constant voltage generating source that is generally referred to as a band gap reference (BGR) circuit. The circuit that generates the predetermined voltage Vcst may of course be provided within the power supply step-down circuit 31.
FIG. 4 is a circuit diagram showing the power supply step-down circuit 31. The LSI circuit including the power supply step-down circuit 31 includes input terminals 41 and 42, the single power supply step-down circuit 31 integrally having the step-down circuit 31-1 for the normal operation mode and the step-down circuit 31-2 for the standby mode, and an output terminal 49 which are connected as shown in FIG. 4. The power supply step-down circuit 31 has a constant voltage source 43, a differential amplifier (or an operational amplifier) 44, an output transistor 45, an inverter 46, the step-down circuits 31-1 and 31-2, a pulse generating circuit 51, and a transistor 52. The transistors 45 and 52 are formed by P-channel transistors. The output transistor 45 is connected between the input terminal 41 and the output terminal 49. The input power supply voltage Vcc is input to the input terminal 41, and the mode signal MODE that indicates the operation mode of the LSI circuit is input to the input terminal 42.
The step-down circuit 31-1 for the normal operation mode has a series circuit connected between the output terminal 49 and the ground, where the series circuit includes a P-channel transistor 61, resistors 63 and 64 and an N-channel transistor 62 that are connected in series as shown in FIG. 4. The inverter 46 may form a portion of the step-down circuit 31-1 for the normal operation mode. On the other hand, the step-down circuit 31-2 for the standby mode has a series circuit connected between the output terminal 49 and the ground, where the series circuit includes a P-channel transistor 71, resistors 73 and 74 and an N-channel transistor 72 that are connected in series as shown in FIG. 4. The step-down circuit 31-2 for the standby mode further has an inverter 75 that is connected as shown in FIG. 4.
The constant voltage source 43 generates the predetermined voltage Vcst based on the input power supply voltage Vcc and the mode signal MODE, and inputs the predetermined voltage Vcst to an inverting input terminal of the differential amplifier 44. A voltage that is divided by the voltage-dividing resistors of the step-down circuit 31-1 for the normal operation mode or the step-down circuit 31-2 for the standby mode, is input to a non-inverting input terminal of the differential amplifier 44. An output terminal of the differential amplifier 44 and a gate of the output transistor 45 are connected via a node N1.
The mode signal MODE that is input to the input terminal 42 has a low level in the normal operation mode, and the bias current within the differential amplifier 44 and the constant voltage source 43 becomes high. Hence, the step-down circuit 31-1 for the normal operation mode, having the low resistance, is selected and activated, while the step-down circuit 31-2 for the standby mode is deactivated. On the other and, when the mode signal MODE having a high level and indicating the standby mode is input to the input terminal 42, the bias current within the differential amplifier 44 and the constant voltage source 43 becomes low. Thus, the step-down circuit 31-1 for the normal operation mode is deactivated, and the step-down circuit 31-2 for the standby mode, having the high resistance, is selected and activated.
When employing a structure of the power supply step-down circuit 31 that does not control the internal current thereof by the mode signal MODE, it is unnecessary to supply the mode signal MODE to the constant power supply source 43 and the differential amplifier 44.
The mode signal MODE from the input terminal 42 is input to the pulse generating circuit 51. An output terminal of the pulse generating circuit 51 and a gate of the transistor 52 are connected via a node N2. The transistor 52 is connected between the input terminal 41 and the node N1. An output current Io of the power supply step-down circuit 31, that is, a current consumed by the LSI circuit, flows to the output terminal 49, and the output voltage Vo which is obtained by stepping down the power supply voltage Vcc is output from the output terminal 49.
The pulse generating circuit 51 and the P-channel transistors 52 and 45 form an output circuit which maintains the output voltage Vo lower than the input power supply voltage Vcc for only a predetermined time when the operation mode of the LSI circuit switches to the standby mode, so that the output voltage Vo does not become the same potential as the input power supply voltage Vcc for a long time when the operation mode of the LSI circuit makes a transition from the normal operation mode to the standby mode.
FIG. 5 is a timing chart for explaining the operation of the power supply step-down circuit 31. In FIG. 5, (a) shows the mode signal MODE, (b) shows the clock CLK that is supplied to the circuit part, such as the CPU 33, within the LSI circuit, (c) shows the output current Io of the power supply step-down circuit 31, (d) shows the voltage at the node N1 which connects the output terminal of the differential amplifier 44 and the gate of the output transistor 45, and (e) shows the output voltage (stepped down power supply voltage) Vo that is output from the output terminal 49. FIG. 5 shows a case where the operation mode of the LSI circuit undergoes a transition from the normal operation mode to the standby mode.
As shown in FIG. 5, the during the low-level period of the mode signal MODE that indicates the normal operation mode and is input to the input terminal 42, the clock CLK is supplied to the circuit part, such as the CPU 33, within the LSI circuit. In this normal operation mode, the LSI circuit is in a state where the current consumption thereof is large, that is, the output current Io of the power supply step-down circuit 31 is high.
On the other hand, when the mode signal MODE that is input to the input terminal 42 makes a transition to the high level indicating the standby mode, the supply of the clock CLK within the LSI circuit stops, and the output current Io of the power supply step-down circuit 31 rapidly decreases as indicated by an arrow A1 in FIG. 5(c). In this state, the voltage at the node N1 connecting to the gate of the output transistor 45 is raised immediately as indicated by an arrow A2 in FIG. 5(d) so that the output voltage Vo output from the output terminal 49 will not change before and after the operation mode switches. In other words, at the same time as when the operation mode switches from the normal operation mode to the standby mode, the voltage at the node N1 is raised to the input power supply voltage Vcc. Accordingly, even though the power supply step-down circuit 31 is switched to the step-down circuit 31-2 having the slow reaction speed, it will not take time for the voltage at the node N1 to rise. In FIG. 5, (d) shows an ideal voltage waveform at the node N1, and the actual voltage waveform rises as indicated by a dotted line.
Because the voltage at the node N1 is raised t the input power supply voltage Vcc, it is possible to suppress the output voltage Vo from rising, and the output voltage Vo can be maintained to a predetermined voltage. If the voltage at the node N1 has the same potential as the input power supply voltage Vcc, the output voltage Vo will decrease with the current consumption of the LSI circuit since the output transistor 45 is turned OFF completely. But because the LSI circuit is operating in the standby mode, the amount of decrease of the output voltage Vo is 0.3 V or less, for example, and is extremely small as indicated by an arrow A3 in FIG. 5(e). The voltage at the node N1 decreases from the input power supply voltage Vcc depending on the decrease of the output voltage Vo, and finally stabilizes to a certain voltage. At a point in time when the voltage at the node N1 stabilizes, the output voltage Vo also stabilizes to a predetermined voltage from the decreased state. For example, if the end of the output terminal 49 is represented by an equivalent circuit that is made up of a parallel circuit which is connected between the output terminal 49 and the ground, where the parallel circuit is formed by a capacitor having a capacitance of 0.1 μF and a resistor, the current flowing through this resistor is 100 μA. Further, if the amount of decrease of the output voltage Vo in FIG. 5(e) is 0.2 V, the time period in which the output voltage Vo decreases as indicated by the arrow A3 us approximately 200 μsec.
FIG. 6 is a circuit diagram showing the pulse generating circuit 51. The pulse generating circuit 51 has a delay circuit 81, an inverter 82, and a NAND circuit 83 that are connected as shown in FIG. 6. The mode signal MODE from the input terminal 42 is input to an input terminal of the delay circuit 81 and to one input terminal of the NAND circuit 83. The inverter 82 is connected between an output terminal of the delay circuit 81 and the other input terminal of the NAND circuit 83. The inverter 82 and the NAND circuit 83 are connected via a node N3. An output terminal of the NAND circuit 83 is connected to the node N2.
FIG. 7 is a timing chart for explaining the operation of the pulse generating circuit 51. In FIG. 7, (a) shows the mode signal MODE, (b) shows the voltage at the node N3, and (c) shows the voltage at the node N2. In FIG. 7(b), D1 denotes a delay time (amount of delay) of the delay circuit 81. Further, in FIG. 7(c), the pulse that is output from the pulse generating circuit 51 to forcibly make the voltage at the node N1 the same potential as the input power supply voltage Vcc for the delay time D1 is surrounded by a dotted line.
As shown in FIG. 4, the node N2 shown in FIG. 6 is connected to the gate of the P-channel transistor 52 that is connected between the input terminal 41 and the node N1. For this reason, the voltage at the node N1 is forcibly set to the same potential as the input power supply voltage Vcc only during the low-level period of the voltage at the node N2 shown in FIG. 6.
The time period (that is, the output pulse width of the pulse generating circuit 51) in which the voltage at the node N1 is forcibly set to the same potential as the input power supply voltage Vcc, is variable by adjusting the delay time D1 shown in FIG. 7(b). According to the experiments conducted by the present inventor, however, it was confirmed through simulation that it is sufficient to set the delay time D1 to approximately 1 μsec. In other words, it was confirmed that approximately 1 μsec is a sufficiently long time (delay time D1) for the output voltage Vo to be maintained lower than the input power supply voltage Vcc when the operation mode is switched to the standby mode, for the purposes of preventing the output voltage Vo from becoming the same potential as the input power supply voltage Vcc for a long time when the operation mode of the LSI circuit makes a transition from the normal operation mode to the standby mode.
This application claims the benefit of a Japanese Patent Application No.2006-247106 filed Sep. 12, 2006, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
Patent Application
20080061749
