This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-198470, filed Jul. 17, 2003, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device such as a memory having MIS transistors, for example, and more particularly to a power supply voltage lowering circuit.
2. Description of the Related Art
For example, the gate oxide film used in a semiconductor device (which is hereinafter referred to as an LSI) such as a memory device having MIS transistors is made thinner as the element is more miniaturized. External power supply voltage (which is hereinafter referred to as VEXT) applied to this type of LSI is not always changed according to miniaturization of the element. Therefore, high voltage of VEXT determined according to the environment of the user using the LSI is applied to the LSI in some cases. If the high voltage of VEXT is applied to a transistor having a thin gate oxide film in the LSI, the gate oxide film will be destroyed in some cases.
In order to prevent the above problem, a countermeasure for arranging a power supply voltage lowering circuit (which is hereinafter simply referred to as a voltage lowering circuit) in the LSI and lowering VEXT by use of the voltage lowering circuit to generate internal power supply voltage (which is hereinafter referred to as VINT) is taken. Thus, by generating VINT lower than VEXT, the transistor having a thin gate oxide film can be prevented from being destroyed. When VEXT becomes equal to or higher than constant voltage, the voltage of VINT is set to voltage which does not depend on a variation in the voltage of VEXT and a temperature variation and the voltage of VINT becomes equal to a constant value.
As the technique for generating internal power supply voltage based on the external power supply voltage by use of the voltage lowering circuit, for example, a circuit which is turned ON in response to a control signal in a low power consumption mode (deep power down mode) to generate internal power supply voltage lower than the external power supply voltage by threshold voltage VTHN of an NMOS transistor is developed (Jpn. Pat. Appln. KOKAI Publication No. 2002-373490).
Further, a circuit in which a PMOS transistor is turned ON in response to a power-ON reset signal generated at the turn-ON time of the power supply and the external power supply voltage VEXT is forcedly set to the internal power supply voltage VINT in a semiconductor device having a voltage generating circuit which generates the internal power supply voltage based on the external power supply voltage is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 2001-210076).
The conventional voltage lowering circuit includes a reference voltage generating circuit using a band gap reference circuit which generates reference voltage VREF and an internal voltage generating circuit which receives the reference voltage VREF from the voltage generating circuit and generates VINT.
For example, when no access is made to the LSI for a long period of time, the LSI is set in a standby mode in order to suppress the power consumption. When the LSI is set into the standby mode, VEXT is lowered to approximately 1V in some cases in order to suppress a standby current of the LSI. In this case, a voltage of only 0.7V is output as VINT generated from the conventional voltage lowering circuit. Since VINT is also used as the power supply voltage of the memory cell, a voltage of 0.7V is applied to the power supply of the memory cell. For example, the voltage is substantially equal to the threshold voltage VTHN of an N-channel MOS transistor (which is hereinafter referred to as an NMOS transistor) or the threshold voltage |VTHP| of a P-channel MOS transistor (which is hereinafter referred to as a PMOS transistor) which configures a memory cell of a static RAM. Therefore, the data latch ability of the memory cell is weakened. That is, when the threshold voltage VTHN of the NMOS transistor or the threshold voltage |VTHP| of the PMOS transistor which configures the memory cell becomes higher than 0.7V, there occurs a possibility that the NMOS transistor or the PMOS transistor is set into the OFF state and data stored in the memory cell will be lost.
Further, the semiconductor device is required to be miniaturized. Therefore, it is not preferable to increase the circuit scale of the voltage lowering circuit. In order to generate required internal power supply voltage, it is desirable to suppress the number of exclusive control signals and the number of circuits which generate the control signals to the smallest possible value. Therefore, it is desired to develop a semiconductor device which can suppress the internal power supply voltage from becoming lower than the external power supply voltage without using the exclusive control signal in a state such as a standby mode in which the external power supply voltage is set low and enhance the performance of the semiconductor device in the state in which the external power supply voltage is set low.
A semiconductor device according to a first aspect of the invention comprises a reference voltage generating circuit which generates reference voltage based on external power supply voltage, the reference voltage generating circuit outputting the generated reference voltage from an output terminal thereof; a voltage generating circuit whose input terminal is connected to the output terminal of the reference voltage generating circuit, the voltage generating circuit lowering the external power supply voltage according to the reference voltage supplied from the reference voltage generating circuit to output internal power supply voltage from an output terminal thereof; and at least one of first and second transistors provided in the semiconductor device, the first transistor having a current path connected between a terminal to which the external power supply voltage is supplied and the output terminal of the voltage generating circuit and a gate supplied with constant voltage and having negative threshold voltage and the second transistor having a current path connected between a terminal to which the external power supply voltage is supplied and the output terminal of the reference voltage generating circuit and a gate supplied with constant voltage and having negative threshold voltage.
A semiconductor device according to a second aspect of the invention comprises a reference voltage generating circuit having first and second output terminals, the reference voltage generating circuit generating reference voltage based on external voltage, outputting the thus generated reference voltage from the first output terminal, generating a control signal used to control a current source and outputting the thus generated control signal from the second output terminal; a voltage generating circuit whose input terminal is connected to the first output terminal of the reference voltage generating circuit, the voltage generating circuit lowering external power supply voltage according to the reference voltage supplied from the first output terminal of the reference voltage generating circuit to output internal power supply voltage from an output terminal thereof; a first transistor having a current path connected between a terminal to which the external power supply voltage is supplied and the output terminal of the voltage generating circuit and a gate supplied with first voltage and having negative threshold voltage; and at least one of second and third transistors provided in the semiconductor device, the second transistor having a current path connected between a terminal to which the external power supply voltage is supplied and the first output terminal of the reference voltage generating circuit and a gate supplied with second voltage and having negative threshold voltage, and the third transistor having a current path connected between a terminal to which the external power supply voltage is supplied and the second output terminal of the reference voltage generating circuit and a gate supplied with constant voltage and having negative threshold voltage.
A semiconductor device according to a third aspect of the invention comprises a reference voltage generating circuit which generates reference voltage based on external power supply voltage, the reference voltage generating circuit outputting the generated reference voltage from an output terminal thereof; a voltage generating circuit whose input terminal is connected to the output terminal of the reference voltage generating circuit, the voltage generating circuit lowering the external power supply voltage according to the reference voltage supplied from the reference voltage generating circuit to output internal power supply voltage from an output terminal thereof; and a transistor having a current path which is connected at one end to a terminal to which the external power supply voltage is supplied and connected at the other end to at least one of the output terminal of the voltage generating circuit and the output terminal of the reference voltage generating circuit, the transistor being supplied with constant voltage at a gate thereof and having negative threshold voltage.
A semiconductor device according to a fourth aspect of the invention comprises a reference voltage generating circuit having first and second output terminals, the reference voltage generating circuit generating reference voltage based on external voltage, outputting the generated reference voltage from the first output terminal, generating a control signal used to control a current source and outputting the thus generated control signal from the second output terminal; a voltage generating circuit whose input terminal is connected to the first output terminal of the reference voltage generating circuit, the voltage generating circuit lowering external power supply voltage according to the reference voltage supplied from the first output terminal of the reference voltage generating circuit to output internal power supply voltage from an output terminal thereof; a first transistor having a current path connected between a terminal to which the external power supply voltage is supplied and the output terminal of the voltage generating circuit and a gate supplied with first voltage and having negative threshold voltage; and a second transistor having a current path connected between a terminal to which the external power supply voltage is supplied and the second output terminal of the reference voltage generating circuit and having negative threshold voltage, a gate of the second transistor being grounded.
There will now be described embodiments of this invention with reference to the accompanying drawings. In the respective embodiments, the same portions are denoted by the same reference symbols.
(First Embodiment)
In
In
In
The operation of the voltage lowering circuit is explained with reference to FIG. 5. In this case, it is assumed that the voltage level of the signal NA is VNA, the voltage level of the signal NB is VNB, the voltage level of the reference signal REF is VREF, and the voltage level of the signal CMN is VCMN.
First, a case wherein the voltage of VEXT lies within a range (B) shown in
VNA=i2×DR1
where DR1 denotes the resistance of the diode D1.
Further, the voltage VNB of the output signal NB is determined by the following equation.
VNB=i3×(DR2+R1)
where DR2 denotes the resistance of the diode D2.
Also, the voltage VREF of the reference signal REF is determined by the following equation.
VREF=i4×(DR3+R2)
where DR3 denotes the resistance of the diode D3.
Further, the voltage VCMN of the signal CMN is determined by the following equation.
VCMN=i5×NR1
where NR1 denotes the channel resistance of the NMOS transistor N1.
Since the currents i2 to i5 become constant as described before, the voltages of the signals NA, NB, REF, CMN also become constant. In addition, as shown in
VINT=(VREF×(R11+R12)/R12) (1)
Alternatively, it can be expressed by the following equation.
VINT=i6×(R11+R12)
The current i6 flows through the PMOS transistor P10 having a gate to which a signal GP output from the OP amplifier of the voltage generating circuit 13 is supplied. Since the reference signal is set at a constant value as described before, the voltage of VINT becomes constant as is expressed in the equation (1). When the voltage VINT derived from the equation (1) is higher than the voltage VEXT, VINT becomes equal to VEXT.
At this time, the operation of the D type NMOS transistor DN10 is performed as follows.
As described before, the threshold voltage VTHN of the MOS transistor DN10 is set at −1.4V. The MOS transistor DN10 is set into the ON state in a condition of Vgs (gate-source voltage)≧VTHN and set into the OFF state in a condition of Vgs<VTH=−1.4V. Therefore, the NMOS transistor DN10 is set into the OFF state in a range (VINT=1.4V) higher than the level (b) shown in
Next, a case wherein the voltage of VEXT lies in a range (A) shown in
The NMOS transistor DN10 maintains the ON state when the source voltage is set in the range of VINT=0V to 1.4V. Therefore, as shown in
The approximate values of the voltages of VINT, VREF, VCMN with respect to VEXT in the voltage lowering circuit shown in
VINT=(1.3)×(1k+6k)/6k)=1.517V
According to the first embodiment, the D type NMOS transistor DN10 is provided between the output terminal of the voltage generating circuit 13 and the VEXT terminal. Therefore, VINT is set to a higher one of the voltage caused by the D type NMOS transistor DN10 and the voltage caused by the BGR circuit 11. Thus, the voltage of VINT is obtained as shown in FIG. 5 and VINT which is equal to VEXT is output from the state where the voltage of VEXT is low in the range (A). As a result, when VEXT is 1V as shown by (a) of
Further, the gate of the D type NMOS transistor DN10 is grounded and the NMOS transistor DN10 is controlled by VEXT and VINT. Therefore, since a control signal is not additionally required in order to control the operation of the NMOS transistor DN10, it is not necessary to provide a circuit which generates the above control signal.
Further, a control signal is not additionally required in order to control the operation of the NMOS transistor DN10. Therefore, the internal power supply voltage can be maintained at the same level as the external power supply voltage when the external power supply voltage is lower than in the steady-state time in a case wherein the semiconductor device is set in any operation state. For example, the above operation can be attained not only in a case wherein the semiconductor device is set in the standby mode, but also in a period from the time the power supply is changed from the turn-OFF state into the turn-ON state until the external power supply voltage reaches a preset value.
When the semiconductor device is released from the standby state and set into the active mode, the NMOS transistor DN10 is turned OFF in response to VINT output from the voltage generating circuit 13 without performing any control operation. Therefore, stable VINT output from the voltage generating circuit 13 can be instantaneously output.
(Second Embodiment)
According to the second embodiment, the D type NMOS transistor DN11 is provided at the output terminal of the BGR circuit 11. Therefore, VREF is set to a higher one of the voltage output from the transistor DN11 and the output voltage of the BGR circuit 11. Thus, VREF and VINT are set to voltages as shown in FIG. 8 and the voltages of VINT and VEXT can be set equal to each other in a state in which VEXT is set low as shown in the range (A). As a result, at a time point of VEXT=1V, VINT=1V can be output. Therefore, in the second embodiment, the same effect as that of the first embodiment can be attained.
(Third Embodiment)
Like the first and second embodiments, in the range (A) of
According to the third embodiment, the same effect as that of the first and second embodiments can be attained.
(Fourth Embodiment)
The substrate voltage (VB) of the NMOS transistor DN12 is set at ground potential. Therefore, the threshold voltage VTHN of the NMOS transistor DN12 becomes higher because of the back-gate bias effect as the source voltage VCMN of the NMOS transistor DN12 rises. That is, the threshold voltage VTHN becomes higher as the voltage VBS between the substrate and the source of the NMOS transistor DN12 becomes more negative. For example, in a case where VTHN obtained when VBS of the NMOS transistor DN10 is set at 0V is set at −0.7V, VBS of the NMOS transistor DN12 is set at −0.5V when the source voltage VCMN of the NMOS transistor DN12 is set equal to 0.5V. As a result, VTHN is set to approximately −0.5V. That is, VTHN of the NMOS transistor DN12 becomes higher than VTHN of the NMOS transistor DN10 by 0.2V.
The NMOS transistor DN12 is set into the ON state in a condition of Vgs>VTHN. Therefore, the NMOS transistor DN12 maintains the ON state while the source voltage VCMN thereof is kept in the range of 0V to 0.5V. Thus, as shown in
Further, the gate of the NMOS transistor DN10 is supplied with the signal CMN and VTHN is set at −0.7V. The NMOS transistor DN10 is set in the ON state in a condition of Vgs≧VTHN. Therefore, the NMOS transistor DN10 maintains the ON state when voltage VINT supplied to the source of the NMOS transistor DN10 is set in the range of 0V to 1.2V in a state in which VCMN is set at 0.5V. Thus, as shown in
Further, in (a) shown in
As described above, since the NMOS transistor DN10 is connected to the output terminal of the voltage generating circuit 13, VINT is set to a higher one of the voltage obtained by the NMOS transistor DN10 and the voltage obtained by the BGR circuit 11. Therefore, VINT is set to voltage as shown in FIG. 12 and VINT of voltage equal to VEXT in a state in which the voltage of VEXT is low is output in the range (A). That is, when VEXT is set at 1V, a voltage of 1V is output as VINT.
The operation characteristic diagram of
Further, as shown in
With the above configuration, the characteristic substantially equivalent to the operation characteristic shown in
(Fifth Embodiment)
With the above configuration, when VEXT is equal to or higher than 0V, VTHN of the NMOS transistor DN12 rises by the back-gate effect. Since VBS of each of the NMOS transistors DN11, DN10 is set at 0V, no back-gate effect occurs. Therefore, the relation of the voltages VTHN of the NMOS transistors DN11, DN10, DN12 when VEXT is equal to or higher than 0V is so set that the relation of VTHN(DN10)=VTHN(DN11)<VTHN(DN12) can be attained.
Further, the relation of the gate voltages Vg of the NMOS transistors DN11, DN10, DN12 is so set that the relation of Vg(DN11)=Vg(DN12)<Vg(DN10) can be attained. Therefore, the NMOS transistors DN12, DN11, DN10 are turned OFF in this order when VEXT rises. As a result, a characteristic in which VINT=1V is output at the time of VEXT=1V can be attained without independently setting the voltages VTHN of the NMOS transistors DN11, DN10, DN12.
In
In each of the above embodiments, the voltages supplies to the drains of the NMOS transistors DN10, DN11, DN12 are set at VEXT. However, this is not limitative. For example, power supply voltage which varies with voltage equivalent to VEXT in a period from turn-ON of the power supply until it reaches 1V or signal voltage in the semiconductor device output at voltage equivalent to VEXT in a period from turn-ON of the power supply until it reaches 1V can be supplied to the drains of the NMOS transistors DN10, DN11, DN12.
Further, in each of the above embodiments, the reference signal REF is generated by use of the BGR circuit 11 and OP amplifier 12. However, this is not limitative.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Number | Date | Country | Kind |
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2003-198470 | Jul 2003 | JP | national |
Number | Name | Date | Kind |
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5563546 | Tsukada | Oct 1996 | A |
5783935 | Kyung | Jul 1998 | A |
Number | Date | Country |
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2001-210076 | Aug 2001 | JP |
2002-334577 | Nov 2002 | JP |
2002-373490 | Dec 2002 | JP |
Number | Date | Country | |
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20050012494 A1 | Jan 2005 | US |