Patent Application
20080290851
The present invention relates to a power supply to which a DC voltage is input from a DC power supply, such as a battery, and from which a controlled DC voltage is output, more particularly, to a soft-start technology in the power supply.
Power conversion systems, such as a series regulator system comprising a voltage control device connected in series with a load and a switching regulator system comprising switching devices, are used for power supplies. In order that a power supply supplies a stable output DC voltage to a load, both the systems are common in that its output DC voltage is detected and fed back. In a power supply, its supply power increases when its output DC voltage is lower than a target value and decreases when the output DC voltage is higher than the target value. For this reason, at the start-up of the power supply, during which the output DC voltage is going to reach the target value, the supply power is increased to the limit of the capacity. As a result, there is a problem that inrush current is generated from the input DC power supply of the power supply. Furthermore, since the power supply is configured such that the supply power is decreased after the output DC voltage exceeds the target value, there is a problem of generating overshoot that supplies excessive power exceeding the target value to the load.
The soft-start technology for limiting the supply power at the start-up is used to suppress inrush current generated at the start-up.
Referring to
A PWM circuit 210 generates and outputs a drive pulse signal having a pulse width based on the error signal Ve input thereto. The switching transistor 202 repeats ON/OFF operation according to the drive pulse signal output from the PWM circuit 210. Since the switching transistor 202 repeats ON/OFF operation, the input DC voltage Vi is chopped and rectified using the diode 203, and smoothed using the inductor 204 and the output capacitor 205, whereby the output DC voltage Vo is supplied to the load 206. The output DC voltage Vo becomes high when the ratio (hereinafter referred to as the “duty ratio”) of the ON time in the switching cycle of the switching transistor 202 is large. The output of the comparator circuit 209 is input to a clamp circuit 211. During a period in which the output DC voltage Vo does not reach the predetermined value, the clamp circuit 211 suppresses the error signal Ve from rising, thereby limiting the error signal Ve to a predetermined value.
In addition, referring to
On the other hand, at the start-up, since the output DC voltage Vo does not reach the predetermined value (95% of the reference voltage), the clamp circuit 211 operates to limit the voltage of the error signal Ve input to the PWM circuit 210 to a clamp voltage. In reality, since the clamp voltage being lower than the voltage of the error signal Ve having a high potential is input to the PWM circuit 210, the duty ratio of the switching transistor 202 becomes small, and the supply power is limited. As a result, the generation of inrush current is prevented in the conventional power supply. When the output DC voltage Vo reaches the predetermined value (95% of the reference voltage) in the power supply, the limitation of the supply power is released, and the operation shifts to the normal operation in which the output DC voltage Vo is adjusted to the reference voltage.
However, although inrush current can be limited in the power supply having the conventional soft-start function and configured as described above, when the limitation of the supply power is released after the output DC voltage Vo reaches the preset voltage, overshoot is generated in the output DC voltage Vo in the case that the load 206 is light. To solve this problem, there is a method in which the limitation of the supply power to limit inrush current is continued after the start-up. However, in the case that the limitation level of the supply power for suppressing overshoot is lower than the limitation level of the supply power for limiting inrush current, this method has a problem of being unable to sufficiently suppress overshoot.
An object of the present invention is to provide a power supply capable of securely carrying out soft-start operation, more particularly, to provide a power supply having a soft-start function capable of raising the output DC voltage without generating overshoot even when the load is set light at the start-up.
To attain the above-mentioned object, a power supply according to a first aspect of the present invention, for converting an input DC voltage into an output DC voltage and supplying power to a load, comprises:
an error amplifier for outputting an error signal corresponding to the error between the output DC voltage and the target value thereof,
a control section for adjusting power to be supplied to the load on the basis of the error signal, and
a limiting circuit for limiting the voltage of the error signal to a predetermined level for a predetermined time after the output DC voltage at the start-up exceeds a predetermined value being set less than the target value.
With the power supply configured as described above, when the load condition is set light at the start-up, the output DC voltage can rise without generating overshoot.
The power supply according to a second aspect of the present invention may be configured such that the limiting circuit according to the first aspect limits the voltage of the error signal to a first predetermined level until the output DC voltage at the start-up reaches the predetermined value being set less than the target value, and limits the voltage of the error signal to a second predetermined level for a predetermined time after the output DC voltage at the start-up exceeds the predetermined value being set less than the target value.
The power supply according to a third aspect of the present invention may be configured such that the limiting circuit according to the second aspect comprises a comparator circuit for comparing the output DC voltage with the predetermined value being set less than the target value; a first clamp circuit for limiting the voltage of the error signal to a first predetermined level on the basis of the output of the comparator circuit until the output DC voltage at the start-up reaches the predetermined value being set less than the target value; and a second clamp circuit for limiting the voltage of the error signal to a second predetermined level for a predetermined time on the basis of the output of the comparator circuit after the output DC voltage at the start-up exceeds the predetermined value being set less than the target value.
The power supply according to a fourth aspect of the present invention may be configured such that the second clamp circuit according to the third aspect limits the voltage of the error signal to a second predetermined level on the basis of the output of the comparator circuit for a predetermined time after the output DC voltage at the start-up exceeds the predetermined value being set less than the target value, and releases the limitation to the second predetermined level when the error between the output DC voltage at the start-up and the target value becomes a reference voltage or less.
The power supply according to a fifth aspect of the present invention may be configured such that the limiting circuit according to the second aspect comprises a first comparator circuit for comparing the output DC voltage with a first value being set less than the target value; a second comparator circuit for comparing the output DC voltage with a second value that is set less than the target value and higher than the first value; a first clamp circuit for limiting the voltage of the error signal to a first predetermined level on the basis of the output of the first comparator circuit until the output DC voltage at the start-up reaches the first value being set less than the target value; and a second clamp circuit for limiting the voltage of the error signal to a second predetermined level for a predetermined time on the basis of the output of the first comparator circuit after the output DC voltage at the start-up exceeds the first value being set less than the target value, the limitation to the second predetermined level being released on the basis of the output of the second comparator circuit.
The power supply according to a sixth aspect of the present invention may be configured such that the predetermined time according to the first and second aspects is set at a period elapsed after the output DC voltage exceeds the predetermined value being set less than the target value and until the output DC voltage reaches the target value.
The power supply according to a seventh aspect of the present invention may be configured such that the control section according to the first to fifth aspects comprises a voltage conversion section having a switch, a rectifier and an inductor, and a PWM circuit for ON/OFF controlling the switch according to the error signal.
The power supply according to an eighth aspect of the present invention may be configured such that the PWM circuit according to the seventh aspect comprises a current detector for detecting the current flowing through the voltage conversion section, and a timing setting circuit for setting the ON/OFF timing of the switch on the basis of the output of the current detector and the error signal.
Since the present invention is configured so as to limit supply power immediately before the output DC voltage reaches the target value, it is possible to provide a power supply capable of securely suppressing output overshoot even at the start-up under light load.
While the novel features of the invention are set forth particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings.
It will be recognized that some or all of the Figures are schematic representations for purposes of illustration and do not necessarily depict the actual relative sizes or locations of the elements shown.
Preferred embodiments of a power supply according to the present invention will be described below referring to the accompanying drawings.
A power supply according to a first embodiment of the present invention will be described below referring to
Referring to
A first clamp circuit 11 serving as a limiting circuit comprises a transistor 110 that is driven using the output signal of the comparator circuit 9, a resistor 111, a constant current supply 112 for supplying a constant current to this resistor 111 and a transistor 113 that is driven using the voltage generated at the connection point of the resistor 111 and the constant current supply 112. When the transistor 110 is ON, the addition voltage (Vt+Vr) of the source-gate voltage Vt of the transistor 110 and the constant voltage Vr generated across the resistor 111 is applied to the gate of the transistor 113, and the transistor 113 is turned ON. On the other hand, when the transistor 110 is OFF, the input voltage Vi is applied to the gate of the transistor 113, and the transistor 113 is turned OFF.
A second clamp circuit 12 serving as a limiting circuit comprises an integrating circuit comprising a resistor 120 and a capacitor 121 for integrating the output signal of the comparator circuit 9, an inverter 122 for inverting the output of the capacitor 121, a NAND circuit 123 for outputting the NAND of the output signal of the inverter 122 and the output signal of the comparator circuit 9, and a transistor 124 that is driven using the output of the NAND circuit 123.
Next, the operation of the power supply according to the first embodiment configured as described above will be described below. First, the operation of the power supply according to the first embodiment during the normal operation time will be described below.
Referring to
Conversely, when the output DC voltage Vo is higher than the reference voltage, the voltage of the error signal Ve lowers, the duty ratio of the switching transistor 2 becomes smaller, and the output DC voltage Vo becomes lower. By virtue of this feedback operation, the output DC voltage Vo is controlled so as to become equal to the reference voltage. In the first clamp circuit 11, the transistor 110 is turned OFF using the H-level (high-level) output signal of the comparator circuit 9 that is input thereto, whereby the transistor 13 is also turned OFF. Furthermore, in the second clamp circuit 12, the capacitor 121 is charged using the H-level output signal of the comparator circuit 9 that is input thereto, and the inverter 122 outputs an L-level (low-level) signal. As a result, the NAND circuit 123 outputs an H-level signal, and the transistor 124 is turned OFF.
Next, the operation of the power supply at the start-up will be described below referring to
First, at the start-up in which the output DC voltage Vo does not reach the predetermined value (95% of the reference voltage) that is less than the target value, the output signal V9 of the comparator circuit 9 is L level, the voltage of the error signal Ve input to the PWM circuit 10 is limited to the addition voltage (2Vt+Vr) of the source-gate voltage Vt of the transistor 110, the voltage Vr across the resistor 111 and the source-gate voltage Vt of the transistor 113 of the first clamp circuit 11. In reality, since the voltage of the error signal Ve rising to a high potential is limited to the first clamp voltage (2Vt+Vr) and input to the PWM circuit 10, the duty ratio of the switching transistor 2 becomes small, and the supply power is limited. As a result, the generation of inrush current can be prevented in the power supply according to the first embodiment. During this period, in the second clamp circuit 12, the NAND circuit 123 outputs an H-level signal by virtue of the L-level output signal of the comparator circuit 9 that is input thereto, and the transistor 124 is turned OFF. Since the capacitor 121 is discharged to L level, the output signal V122 of the inverter 122 is H level.
When the output DC voltage Vo reaches the predetermined value (95% of the reference voltage) at time t1 in
As described above, in the power supply according to the first embodiment, at the light-load start-up in which the output DC voltage Vo does not reach the predetermined value that is less than the target value, the voltage of the error signal Ve is limited to the first clamp voltage (2Vt+Vr), and the supply power is limited, whereby inrush current is prevented. Furthermore, for a predetermined period after the output DC voltage Vo has reached the predetermined value, the voltage of the error signal Ve is limited to the second clamp voltage (Vt), and the rising speed of the output DC voltage Vo is further suppressed. As a result, the generation of overshoot is prevented securely.
A power supply according to a second embodiment of the present invention will be described below referring to the accompanying
As shown in
Since the operation of the power supply according to the second embodiment configured as described above during the normal operation time is similar to that of the power supply according to the above-mentioned first embodiment, the description thereof is omitted herein.
Next, the operation of the power supply according to the second embodiment at the start-up will be described below referring to
First, at the start-up in which the output DC voltage Vo does not reach the predetermined value (95% of the reference voltage), the first error signal Ve generated by the error amplifier 8 has a high potential. However, the output signal V9 of the comparator circuit 9 is L level, and the voltage of the second error signal Ve2 that is input to the PWM circuit 10 is limited to the addition voltage (2Vt+Vr) of the source-gate voltage Vt of the transistor 110, the voltage Vr across the resistor 111 and the source-gate voltage Vt of the transistor 113 of the first clamp circuit 11. Hence, the duty ratio of the switching transistor 2 becomes small, and the supply power is limited. As a result, the generation of inrush current can be prevented in the power supply according to the second embodiment. During this period, in the second clamp circuit 12a, since the voltage of the first error signal Ve is higher than the voltage V125 of the voltage supply 125, the output signal V126 of the comparator 126 is H level. Furthermore, since the output signal V9 of the comparator circuit 9 is L level, the NAND circuit 123 outputs an H-level signal and the transistor 124 is turned OFF.
When the output DC voltage Vo reaches the predetermined value (95% of the reference voltage) at time t1 in
As described above, in the power supply according to the second embodiment, the resistor 80 is provided so that the output level (Ve) from the error amplifier 8 is separated from the input level (Ve2) to the PWM circuit 10. Furthermore, a judgment as to whether the output DC voltage Vo has reached the target value is made depending on the output level from the error amplifier 8, whereby it becomes possible to set the limitation period using the second clamp voltage. Since the first clamp circuit 11 and the second clamp circuit 12 do not carry out clamp operation during the normal operation time, the output level from the error amplifier 8 is equal to the input level to the PWM circuit 10.
As described above, in the power supply according to the second embodiment, at the light-load start-up in which the output DC voltage Vo does not reach the predetermined value that is less than the target value, the voltage of the second error signal Ve2 is limited to the first clamp voltage (2Vt+Vr), and the supply power is limited, whereby the generation of inrush current is prevented. Furthermore, for a predetermined period after the output DC voltage Vo has reached the predetermined value, the voltage of the second error signal Ve2 is limited to the second clamp voltage (Vt), and the rising speed of the output DC voltage Vo is further suppressed. As a result, the generation of overshoot is prevented securely.
A power supply according to a third embodiment of the present invention will be described below referring to the accompanying
The power supply according to the third embodiment is provided with a first comparator circuit 9, the output signal of which is input to the first clamp circuit 11 and the second clamp circuit 12a, and the second comparator circuit 9a, the output signal of which is input to the second clamp circuit 12a. The configuration of the first comparator circuit 9 according to the third embodiment is substantially the same as that of the comparator circuit 9 according to the first embodiment. The first comparator circuit 9 is provided with a comparator 90 and two resistors 91 and 92, and the comparator 90 compares the output DC voltage Vo with a first predetermined value. The first predetermined value that is compared by the comparator 90 is formed by dividing the reference voltage using the resistors 91 and 92. The first predetermined value is formed so as to be 95% of the reference voltage, for example. The second comparator circuit 9a in the power supply according to the third embodiment is provided with a comparator 90a and two resistors 91a and 92a, and the comparator 90a compares the output DC voltage Vo with a second predetermined value. The second predetermined value that is compared by the comparator 90a is formed by dividing the reference voltage using the resistors 91a and 92a. The second predetermined value is formed so as to be 99% of the reference voltage, for example.
Since the operation of the power supply according to the third embodiment configured as described above during the normal operation time is similar to that of the power supply according to the above-mentioned first embodiment, the description thereof is omitted herein.
Next, the operation of the power supply according to the third embodiment at the start-up will be described below referring to
First, at the start-up in which the output DC voltage Vo does not reach the first predetermined value (95% of the reference voltage), the first error signal Ve generated by the error amplifier 8 has a high potential, and the output signal V9 of the first comparator circuit 9 is L level. Hence, the voltage of the second error signal Ve2 that is input to the PWM circuit 10 is limited to the addition voltage (2Vt+Vr) of the source-gate voltage Vt of the transistor 110, the voltage Vr across the resistor 111 and the source-gate voltage Vt of the transistor 113 of the first clamp circuit 11. Hence, the duty ratio of the switching transistor 2 becomes small, and the supply power is limited. As a result, the generation of inrush current can be prevented in the power supply according to the third embodiment. During this period, in the second clamp circuit 12a, since the output DC voltage Vo is lower than the second predetermined value (99% of the reference voltage), the output signal V9a of the second comparator circuit 9a is H level, the output signal V126 of the comparator 126 is H level, and the output signal V9 of the first comparator circuit 9 is L level, the NAND circuit 123 outputs an H-level signal. Hence, the transistor 124 is turned OFF.
When the output DC voltage Vo reaches the first predetermined value (95% of the reference voltage) that is less than the target value at time t1 in
As described above, in the power supply according to the third embodiment, the second comparator circuit 9a is provided, and a judgment as to whether the output DC voltage Vo has reached the target value is made, whereby it becomes possible to set the limitation period using the second clamp voltage. Since the first clamp circuit 11 and the second clamp circuit 12 do not carry out clamp operation during the normal operation time, the output level (Ve) from the error amplifier 8 is equal to the input level (Ve2) to the PWM circuit 10.
A power supply according to a fourth embodiment of the present invention will be described below referring to the accompanying
The power supplies according to the first to third embodiments according to the present invention employ voltage mode control in which the duty ratio of the switching transistor 2 is changed using the error signal Ve obtained by comparing the output DC voltage Vo with the reference voltage so that the output DC voltage Vo is controlled so as to become equal to the reference voltage. On the other hand, the power supply according to the fourth embodiment employs current mode control in which the error signal Ve obtained by comparing the output DC voltage Vo with the reference voltage is compared with a voltage V13 being proportional to the current flowing through the inductor 4, and the current flowing through the inductor 4 is adjusted so that the output DC voltage Vo is controlled so as to become equal to the reference voltage. In the fourth embodiment, the current flowing through the diode 3 is used instead of the current flowing through the inductor 4.
In the power supply according to the fourth embodiment, the voltage of the first error signal Ve generated by the error amplifier 8 rises when the output DC voltage Vo is lower than the reference voltage, and lowers when the output DC voltage Vo is higher than the reference voltage. During the normal operation time, the first clamp circuit 11 and the second clamp circuit 12 do not operate, and the first error signal Ve generated by the error amplifier 8 is input to the comparator 14 via the resistor 80.
As shown in
As shown in
When the H-level signal is input from the pulse-forming circuit 15 to the set (S) terminal of the RS latch circuit 16, the RS latch circuit 16 outputs an H-level signal. When this H-level signal is input to the timer circuit 17, the timer circuit 17 outputs an H-level signal after the elapse of a predetermined time that is determined by the capacity of the capacitor 175, the constant current from the constant current supply 174 and the voltage of the voltage supply 176.
When the H-level signal of the timer circuit 17 is input to the reset (R) terminal of the RS latch circuit 16, the RS latch circuit 16 outputs an L-level signal. In other words, the ON period of the switching transistor 2 is set at a predetermined time using the pulse-forming circuit 15, the RS latch circuit 16 and the timer circuit 17.
Next, the operation of the power supply according to the fourth embodiment configured as described above will be described below.
First, the operation of the power supply according to the fourth embodiment during the normal operation time will be described below.
In the power supply according to the fourth embodiment, the voltage of the first error signal Ve generated by the error amplifier 8 rises when the output DC voltage Vo is lower than the reference voltage, and lowers when the output DC voltage Vo is higher than the reference voltage. Furthermore, the output of the current detection circuit 13 rises and lowers in proportion to the current flowing through the inductor 4. Hence, when the second error signal Ve2 derived from the first error signal Ve via the resistor 80 has a high potential, the comparator 14 outputs an H-level signal while a large amount of current flows through the inductor 4. On the other hand, when the second error signal Ve2 has a low potential, the comparator 14 outputs an H-level signal while a small amount of current flows through the inductor 4. When the comparator 14 outputs the H-level signal, the switching transistor 2 is turned ON, thereby increasing the current flowing through the inductor 4. As a result, the amount of the current flowing through the inductor 4 is proportional to the potential of the first error signal Ve. In other words, when the output DC voltage Vo is lower than the reference voltage, the voltage of the first error signal Ve rises, the current flowing through the inductor 4 becomes larger, and the output DC voltage Vo becomes higher. Conversely, when the output DC voltage Vo is higher than the reference voltage, the voltage of the first error signal Ve lowers, the current flowing through the inductor 4 becomes smaller, and the output DC voltage Vo becomes lower. This feedback operation controls the output DC voltage Vo so as to become equal to the reference voltage.
During the normal operation time, in the first clamp circuit 11, the transistor 110 of the first clamp circuit 11 is turned OFF using the H-level signal of the comparator circuit 9 that is input thereto. In addition, in the second clamp circuit 12a, since the voltage of the first error signal Ve is lower than the voltage V125 of the voltage supply 125, the output signal of the comparator 126 is L level. Furthermore, since the output of the comparator circuit 9 is H level, the NAND circuit 123 outputs an H-level signal, and the transistor 124 is turned OFF.
Next, the operation of the power supply at the start-up will be described below referring to
At the start-up in which the output DC voltage Vo does not reach the predetermined value (95% of the reference voltage), the first error signal Ve generated by the error amplifier 8 has a high potential, and the output signal V9 of the comparator circuit 9 is L level. Hence, the voltage of the second error signal Ve2 that is input to the comparator 14 is limited to the addition voltage (2Vt+Vr) of the source-gate voltage Vt of the transistor 110, the voltage Vr across the resistor 111 and the source-gate voltage Vt of the transistor 113 of the first clamp circuit 11. Hence, the current of the inductor 4 is limited. As a result, the generation of inrush current can be prevented in the power supply according to the fourth embodiment. During this period, in the second clamp circuit 12a, since the voltage of the second error signal Ve is higher than the voltage V125 of the voltage supply 125, the output signal V126 of the comparator 126 is H level, and the output signal V9 of the comparator circuit 9 is L level. Hence, the NAND circuit 123 outputs an H-level signal, and the transistor 124 is turned OFF.
When the output DC voltage Vo reaches the predetermined value (95% of the reference voltage) at time t1 in
As described above, even in the power supply according to the fourth embodiment employing the current mode control, the supply power is limited immediately before the output DC voltage reaches the target value, whereby the output overshoot under light load at the start-up can be suppressed. In the case of the current mode control, since the error signal to be limited directly corresponds to the current flowing through the inductor 4, that is, the current supplied to the output, the power supply has excellent characteristics capable of setting the suppression level of inrush current and capable of speedily responding to transient phenomena, such as output overshoot.
Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art to which the present invention pertains, after having read the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
The present invention is thus useful for a power supply to which a DC voltage is input from a DC power supply, such as a battery, and from which a controlled DC voltage is output.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-136616 | May 2007 | JP | national |
