Power surface mount light emitting die package

Information

  • Patent Grant
  • 8622582
  • Patent Number
    8,622,582
  • Date Filed
    Tuesday, February 8, 2011
    15 years ago
  • Date Issued
    Tuesday, January 7, 2014
    12 years ago
  • Inventors
  • Original Assignees
  • Examiners
    • Alavi; Ali
    Agents
    • Jenkins, Wilson, Taylor & Hunt, P.A.
Abstract
A light emitting die package includes a substrate, a reflector plate, and a lens. The substrate has traces for connecting an external electrical power source to a light emitting diode (LED) at a mounting pad. The reflector plate is coupled to the substrate and substantially surrounds the mounting pad, and includes a reflective surface to direct light from the LED in a desired direction. The lens is free to move relative to the reflector plate and is capable of being raised or lowered by the encapsulant that wets and adheres to it and is placed at an optimal distance from the LED chip(s). Heat generated by the LED during operation is drawn away from the LED by both the substrate (acting as a bottom heat sink) and the reflector plate (acting as a top heat sink).
Description
BACKGROUND

Example embodiments in general relate to packaging semiconductor devices which include light emitting diodes.


Light emitting diodes (LEDS) are often packaged within leadframe packages. A leadframe package typically includes a molded or cast plastic body that encapsulates an LED, a lens portion, and thin metal leads connected to the LED and extending outside the body. The metal leads of the leadframe package serve as the conduit to supply the LED with electrical power and, at the same time, may act to draw heat away from the LED. Heat is generated by the LED when power is applied to the LED to produce light. A portion of the leads extends out from the package body for connection to circuits external to the leadframe package.


Some of the heat generated by the LED is dissipated by the plastic package body; however, most of the heat is drawn away from the LED via the metal components of the package. The metal leads are typically very thin and has a small cross section. For this reason, capacity of the metal leads to remove heat from the LED is limited. This limits the amount of power that can be sent to the LED thereby limiting the amount of light that can be generated by the LED.


To increase the capacity of an LED package to dissipate heat, in one LED package design, a heat sink slug is introduced into the package. The heat sink slug draws heat from the LED chip. Hence, it increases the capacity of the LED package to dissipate heat. However, this design introduces empty spaces within the package that is be filled with an encapsulant to protect the LED chip. Furthermore, due to significant differences in CTE (coefficient of thermal expansion) between various components inside the LED package, bubbles tend to form inside the encapsulant or the encapsulant tends to delaminate from various portions within the package. This adversely affects the light output and reliability of the product. In addition, this design includes a pair of flimsy leads which are typically soldered by a hot-iron. This manufacturing process is incompatible with convenient surface mounting technology (SMT) that is popular in the art of electronic board assembly.


In another LED package design, the leads of the leadframe package have differing thicknesses extended (in various shapes and configurations) beyond the immediate edge of the LED package body. A thicker lead is utilized as a heat-spreader and the LED chip is mounted on it. This arrangement allows heat generated by the LED chip to dissipate through the thicker lead which is often connected to an external heat sink. This design is inherently unreliable due to significant difference in coefficient of thermal expansion (CTE) between the plastic body and the leadframe material. When subjected to temperature cycles, its rigid plastic body that adheres to the metal leads experiences high degree of thermal stresses in many directions. This potentially leads to various undesirable results such as cracking of the plastic body, separation of the plastic body from the LED chip, breaking of the bond wires, delaminating of the plastic body at the interfaces where it bonds to various parts, or resulting in a combination of these outcomes. In addition, the extended leads increase the package size and its footprint. For this reason, it is difficult to populate these LED packages in a dense cluster on a printed circuit board (PCB) to generate brighter light.


Another disadvantage of conventional leadframe design is that the thick lead cannot be made or stamped into a fine circuit for flip-chip mounting of a LED—which is commonly used by some manufacturers for cost-effective manufacturing and device performance.


SUMMARY

An example embodiment of the present invention is directed to a semiconductor die package including a substrate having conductive traces on a top surface thereof, and a light emitting diode (LED) mounted to the top surface of the substrate via a mounting pad. The mounting pad is electrically connected to the conductive traces on the substrate top surface. The package includes a reflector plate mechanically coupled to the substrate and substantially surrounding the mounting pad and LED, the reflector plate defining a reflection surface, and a lens substantially covering the mounting pad and LED.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1A is a perspective view of a semiconductor die package according to one embodiment of the present invention;



FIG. 1B is an exploded perspective view of the semiconductor package of FIG. 1A;



FIG. 2A is a top view of a portion of the semiconductor package of FIG. 1A;



FIG. 2B is a side view of a portion of the semiconductor package of FIG. 1A;



FIG. 2C is a front view of a portion of the semiconductor package of FIG. 1A;



FIG. 2D is a bottom view of a portion of the semiconductor package of FIG. 1A;



FIG. 3 is a cut-away side view of portions of the semiconductor package of FIG. 1A;



FIG. 4 is a side view of the semiconductor package of FIG. 1A with additional elements;



FIG. 5 an exploded perspective view of a semiconductor die package according to another embodiment of the present invention;



FIG. 6A is a top view of a portion of the semiconductor package of FIG. 5;



FIG. 6B is a side view of a portion of the semiconductor package of FIG. 5;



FIG. 6C is a front view of a portion of the semiconductor package of FIG. 5; and



FIG. 6D is a bottom view of a portion of the semiconductor package of FIG. 5.





DETAILED DESCRIPTION

Example embodiments will now be described with reference to the FIGS. 1 through 6D. As illustrated in the Figures, the sizes of layers or regions are exaggerated for illustrative purposes and, thus, are provided to illustrate the general structures of the present invention. Furthermore, various aspects in the example embodiments are described with reference to a layer or structure being formed on a substrate or other layer or structure. As will be appreciated by those of skill in the art, references to a layer being formed “on” another layer or substrate contemplates that additional layers may intervene. References to a layer being formed on another layer or substrate without an intervening layer are described herein as being formed “directly on” the layer or substrate.


Furthermore, relative terms such as beneath may be used herein to describe one layer or regions relationship to another layer or region as illustrated in the Figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, layers or regions described as “beneath” other layers or regions would now be oriented “above” these other layers or regions. The term “beneath” is intended to encompass both above and beneath in this situation. Like numbers refer to like elements throughout.


As shown in the figures for the purposes of illustration, example embodiments of the present invention are exemplified by a light emitting die package including a bottom heat sink (substrate) having traces for connecting to a light emitting diode at a mounting pad and a top heat sink (reflector plate) substantially surrounding the mounting pad. A lens covers the mounting pad. In effect, an example die package comprises a two part heat sink with the bottom heat sink utilized (in addition to its utility for drawing and dissipating heat) as the substrate on which the LED is mounted and connected, and with the top heat sink utilized (in addition to its utility for drawing and dissipating heat) as a reflector plate to direct light produced by the LED. Because both the bottom and the top heat sinks draw heat away from the LED, more power can be delivered to the LED, and the LED can thereby produce more light.


Further, the body of the die package itself may act as the heat sink removing heat from the LED and dissipating it. For this reason, the example LED die package may not require separate heat sink slugs or leads that extend away from the package. Accordingly, the LED die package may be more compact, more reliable, and less costly to manufacture than die packages of the prior art.



FIG. 1A is a perspective view of a semiconductor die package 10 according to one embodiment of the present invention and FIG. 1B is an exploded perspective view of the semiconductor package of FIG. 1A. Referring to FIGS. 1A and 1B, the light emitting die package 10 of the present invention includes a bottom heat sink 20, a top heat sink 40, and a lens 50.


The bottom heat sink 20 is illustrated in more detail in FIGS. 2A through 2D. FIGS. 2A, 2B, 2C, and 2D provide, respectively, a top view, a side view, a front view, and a bottom view of the bottom heat sink 20 of FIG. 1A. Further, FIG. 2C also shows an LED assembly 60 in addition to the front view of the bottom heat sink 20. The LED assembly 60 is also illustrated in FIG. 1B. Referring to FIGS. 1A through 2D, the bottom heat sink 20 provides support for electrical traces 22 and 24; for solder pads 26, 32, and 34; and for the LED assembly 60. For this reason, the bottom heat sink 20 is also referred to as a substrate 20. In the Figures, to avoid clutter, only representative solder pads 26, 32, and 34 are indicated with reference numbers. The traces 22 and 24 and the solder pads 32, 34, and 36 can be fabricated using conductive material. Further, additional traces and connections can be fabricated on the top, side, or bottom of the substrate 20, or layered within the substrate 20. The traces 22 and 24, the solder pads 32, 34, and 36, and any other connections can be interconnected to each other in any combination using known methods, for example via holes.


The substrate 20 is made of material having high thermal conductivity but is electrically insulating, for example, aluminum nitride (AlN) or alumina (Al2O3). Dimensions of the substrate 20 can vary widely depending on application and processes used to manufacture the die package 10. For example, in the illustrated embodiment, the substrate 20 may have dimensions ranging from fractions of millimeters (mm) to tens of millimeters. Although the present invention is not limited to particular dimensions, one specific embodiment of the die package 10 of the present invention is illustrated in Figures with the dimensions denoted therein. All dimensions shown in the Figures are in millimeters (for lengths, widths, heights, and radii) and degrees (for angles) except as otherwise designated in the Figures, in the Specification herein, or both.


The substrate 20 has a top surface 21, the top surface 21 including the electrical traces 22 and 24. The traces 22 and 24 provide electrical connections from the solder pads (for example top solder pads 26) to a mounting pad 28. The top solder pads 26 are portions of the traces 22 and 24 generally proximal to sides of the substrate 20. The top solder pads 26 are electrically connected to side solder pads 32. The mounting pad 28 is a portion of the top surface (including portions of the trace 22, the trace 24, or both) where the LED assembly 60 is mounted. Typically the mounting pad 28 is generally located proximal to center of the top surface 21. In alternative embodiments of the present invention, the LED assembly 60 can be replaced by other semiconductor circuits or chips.


The traces 22 and 24 provide electrical routes to allow the LED assembly 60 to electrically connect to the solder pads 26, 32, or 34. Accordingly, some of the traces are referred to as first traces 22 while other traces are referred to as second traces 24. In the illustrated embodiment, the mounting pad 28 includes portions of both the first traces 22 and the second traces 24. In the illustrated example, the LED assembly 60 is placed on the first trace 22 portion of the mounting pad 28, thereby making contact with the first trace 22. In the illustrated embodiment, a top of the LED assembly 60 and the second traces 24 are connected to each other via a bond wire 62. Depending on the construction and orientation of LED assembly 60, first traces 22 may provide anode (positive) connections and second traces 24 may comprise cathode (negative) connections for the LED assembly 60 (or vice versa).


The LED assembly 60 can include additional elements. For example, in FIGS. 1B and 2C, the LED assembly 60 is illustrated including an LED bond wire 62, an LED subassembly 64, and a light emitting diode (LED) 66. Such an LED subassembly 64 is known in the art and is illustrated for the purposes of discussing the invention and is not meant to be a limitation of the present invention. In the Figures, the LED assembly 60 is shown die-attached to the substrate 20. In alternative embodiments, the mounting pad 28 can be configured to allow flip-chip attachment of the LED assembly 60. Additionally, multiple LED assemblies can be mounted on the mounting pad 28. In alternative embodiments, the LED assembly 60 can be mounted over multiple traces. This is especially true if flip-chip technology is used.


The topology of the traces 22 and 24 can vary widely from the topology illustrated in the Figures while still remaining within the scope of the example embodiments of the present invention. In the Figures, three separate cathode (negative) traces 24 are shown to illustrate that three LED assemblies can be placed on the mounting pad 28, each connected to a different cathode (negative) trace; thus, the three LED assemblies may be separately electrically controllable. The traces 22 and 24 are made of conductive material such as gold, silver, tin, or other metals. The traces 22 and 24 can have dimensions as illustrated in the Figures and are of a thickness on the order of microns or tens of microns, depending on application. In an example, the traces 22 and 24 can be 15 microns thick. FIGS. 1A and 2A illustrate an orientation marking 27. Such markings can be used to identify the proper orientation of the die package 10 even after assembling the die package 10. The traces 22 and 24, as illustrated, can extend from the mounting pad 28 to sides of the substrate 20.


Continuing to refer to FIGS. 1A through 2D, the substrate 20 defines semi-cylindrical spaces 23 and quarter-cylindrical spaces 25 proximal to its sides. In the Figures, to avoid clutter, only representative spaces 23 and 25 are indicated with reference numbers. The semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25 provide spaces for solder to flow-through and solidify-in when the die package 10 is attached to a printed circuit board (PCB) or another apparatus (not shown) to which the die package 10 is a component thereof. Moreover, the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25 provide convenient delineation and break points during the manufacturing process.


The substrate 20 can be manufactured as one individual section of a strip or a plate having a plurality of adjacent sections, each section being a substrate 20. Alternatively, the substrate 20 can be manufactured as one individual section of an array of sections, the array having multiple rows and columns of adjacent sections. In this configuration, the semi-cylindrical spaces 23 and quarter-cylindrical spaces 25 can be utilized as tooling holes for the strip, the plate, or the array during the manufacturing process.


Furthermore, the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25, combined with scribed grooves or other etchings between the sections, assist in separating each individual substrate from the strip, the plate, or the wafer. The separation can be accomplished by introducing physical stress to the perforation (semi through holes at a close pitch) or scribe lines made by laser, or premolded, or etched lines (crossing the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25) by bending the strip, the plate, or the wafer. These features simplify the manufacturing process and thus reduce costs by eliminating the need for special carrier fixtures to handle individual unit of the substrate 20 during the manufacturing process. Furthermore, the semi-cylindrical spaces 23 and the quarter-cylindrical spaces 25 serve as via holes connecting the top solder pads 26, the side solder pads 32, and the bottom solder pads 34.


The substrate 20 has a bottom surface 29 including a thermal contact pad 36. The thermal contact pad 36 can be fabricated using a material having a high thermally and electrically conductive properties such as gold, silver, tin, or another material including but not limited to precious metals.



FIG. 3 illustrates a cut-away side view of portions of the semiconductor package of FIGS. 1A and 1B. In particular, the FIG. 3 illustrates a cut-away side view of the top heat sink 40 and the lens 50. Referring to FIGS. 1A, 1B, and 3, the top heat sink 40 is made from a material having high thermal conductivity such as aluminum, copper, ceramics, plastics, composites, or a combination of these materials. A high temperature, mechanically tough, dielectric material can be used to overcoat the traces 22 and 24 (with the exception of the central die-attach area) to seal the traces 22 and 24 and provide protection from physical and environmental harm such as scratches and oxidation. The overcoating process can be a part of the substrate manufacturing process. The overcoat, when used, may insulate the substrate 20 from the top heat sink 40. The overcoat may then be covered with a high temperature adhesive such as thermal interface material manufactured by THERMOSET that bonds the substrate 20 to the top heat sink 40.


The top heat sink 40 may include a reflective surface 42 substantially surrounding the LED assembly 60 mounted on the mounting pad 28 (of FIGS. 2A and 2C). When the top heat sink 40 is used to dissipate heat generated by the LED in the die package 10, it can be “top-mounted” directly onto an external heat sink by an adhesive or solder joint to dissipate heat efficiently. In another embodiment, if heat has to be dissipated by either a compressible or non-compressible medium such as air or cooling fluid, the top heat sink 40 may be equipped with cooling fins or any feature that will enhance heat transfer between the top heat sink 40 and the cooling medium. In both of these embodiments, the electrical terminals and the bottom heat sink 20 of the die package 10 can still be connected to its application printed circuit board (PCB) using, for example, the normal surface-mount-technology (SMT) method.


The reflective surface 42 reflects portions of light from the LED assembly 60 as illustrated by sample light rays 63. Other portions of the light are not reflected by the reflective surface 42 as illustrated by sample light ray 61. Illustrative light rays 61 and 63 are not meant to represent light traces often use in the optical arts. For efficient reflection of the light, the top heat sink 40 is preferably made from material that can be polished, coined, molded, or any combination of these. Alternatively, to achieve high reflectivity, the optical reflective surface 42 or the entire heat sink 40 can be plated or deposited with high reflective material such as silver, aluminum, or any substance that serves the purpose. For this reason, the top heat sink 40 is also referred to as a reflector plate 40. The reflector plate 40 is made of material having high thermal conductivity if and when required by the thermal performance of the package 10. In the illustrated embodiment, the reflective surface 42 is illustrated as a flat surface at an angle, for example 45 degrees, relative to the reflective plate's horizontal plane. The example embodiments are not limited to the illustrated embodiment. For example, the reflective surface 42 can be at a different angle relative to the reflective plate's horizontal plane. Alternatively, the reflective plate can have a parabolic, toroid or any other shape that helps to meet the desired spectral luminous performance of the package.


The reflective plate 40 includes a ledge 44 for supporting and coupling with the lens 50. The LED assembly 60 is encapsulated within the die package 10 (of FIGS. 1A and 1B) using encapsulation material 46 such as, for example only, soft and elastic silicones or polymers. The encapsulation material 46 can be a high temperature polymer with high light transmissivity and refractive index that matches or closely matches refractive index of the lens 50, for example. The encapsulant 46 is not affected by most wavelengths that alter its light transmissivity or clarity.


The lens 50 is made from material having high light transmissivity such as, for example only, glass, quartz, high temperature and transparent plastic, or a combination of these materials. The lens 50 is placed on top of and adheres to the encapsulation material 46. The lens 50 is not rigidly bonded to the reflector 40. This “floating lens” design enables the encapsulant 46 to expand and contract under high and low temperature conditions without difficulty. For instance, when the die package 10 is operating or being subjected to a high temperature environment, the encapsulant 46 experiences greater volumetric expansion than the cavity space that contains it. By allowing the lens 50 to float up somewhat freely on top of the encapsulant 46, no encapsulant will be squeezed out of its cavity space. Likewise, when the die package 10 is subjected to a cold temperature, the encapsulant 46 will contract more than the other components that make up the cavity space for the encapsulant 46; the lens will float freely on top of the encapsulant 46 as the latter shrinks and its level drops. Hence, the reliability of the die package 10 is maintained over relatively large temperature ranges as the thermal stresses induced on the encapsulant 46 is reduced by the floating lens design.


In some embodiments, the lens 50 defines a recess 52 (See FIG. 3) having a curved, hemispherical, or other geometry, which can be filled with optical materials intended to influence or change the nature of the light emitted by the LED chip(s) before it leaves the die package 10. Examples of one type of optical materials include luminescence converting phosphors, dyes, fluorescent polymers or other materials which absorb some of the light emitted by the chip(s) and re-emit light of different wavelengths. Examples of another type of optical materials include light diffusants such as calcium carbonate, scattering particles (such as Titanium oxides) or voids which disperse or scatter light. Any one or a combination of the above materials can be applied on the lens 50 to obtain certain spectral luminous performance.



FIG. 4 illustrates the die package 10 coupled to an external heat sink 70. Referring to FIG. 4, the thermal contact pad 36 can be attached to the external heat sink 70 using epoxy, solder, or any other thermally conductive adhesive, electrically conductive adhesive, or thermally and electrically conductive adhesive 74. The external heat sink 70 can be a printed circuit board (PCB) or other structure that draws heat from the die package 10. The external heat sink can include circuit elements (not shown) or heat dissipation fins 72 in various configurations.


An example embodiment having an alternate configuration is shown in FIGS. 5 through 6D. Portions of this second embodiment are similar to corresponding portions of the first embodiment illustrated in FIGS. 1A through 4. For convenience, portions of the second embodiment as illustrated in FIGS. 5 through 6D that are similar to portions of the first embodiment are assigned the same reference numerals, analogous but changed portions are assigned the same reference numerals accompanied by letter “a,” and different portions are assigned different reference numerals.



FIG. 5 is an exploded perspective view of an LED die package 10a in accordance with other embodiments of the present invention. Referring to FIG. 5, the light emitting die package 10a of the present invention includes a bottom heat sink (substrate) 20a, a top heat sink (reflector plate) 40a, and a lens 50.



FIGS. 6A, 6B, 6C, and 6D, provide, respectively, a top view, a side view, a front view, and a bottom view of the substrate 20a of FIG. 5. Referring to FIGS. 5 through 6D, the substrate 20a includes one first trace 22a and four second traces 24a. Traces 22a and 24a are configured differently than traces 22 and 24 of FIG. 2A. The substrate 20a includes flanges 31 that define latch spaces 33 for reception of legs 35 of the reflector plate 40a, thereby mechanically engaging the reflector plate 40a with the substrate 20a.


The example embodiments of the present invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the exemplary embodiments of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims
  • 1. A light emitting die package, comprising: an electrically insulating substrate comprising a substantially planar top surface and a substantially planar bottom surface;a plurality of traces disposed on the top surface of the substrate;a light emitting diode (LED) mounted on the top surface of the substrate and proximate a center of the substrate, and the LED being connected to one or more traces of the plurality of traces; anda thermal contact pad disposed on the bottom surface of the substrate.
  • 2. The package of claim 1, wherein the plurality of traces extend to at least one side of the substrate.
  • 3. The package of claim 2, wherein the substrate and the portion of the plurality of traces extending around the side to an end portion of the bottom surface have spaces formed therein.
  • 4. The package of claim 1, wherein the electrically insulating substrate has a high thermal conductivity.
  • 5. The package of claim 1, wherein the electrically insulating substrate comprises aluminum nitride.
  • 6. The package of claim 1, further comprising a plurality of connection pads disposed on the bottom surface of the substrate, the plurality of connection pads being electrically connected to the plurality of traces.
  • 7. The package of claim 6, wherein the plurality of connection pads are positioned at edges of the bottom surface.
  • 8. The package of claim 1, wherein the thermal pad is isolated from the plurality of connection pads on the bottom surface.
  • 9. The package of claim 1, wherein an encapsulant covering the LED.
  • 10. The package of claim 9, wherein the encapsulant is composed of an optically clear polymer material.
  • 11. The package of claim 9, further comprising a lens covering the LED.
  • 12. The package of claim 11, wherein the lens is formed by the encapsulant.
  • 13. The package of claim 9, wherein the encapsulant comprises silicon.
  • 14. A light emitting die package comprising: an electrically insulating substrate comprising a top surface, a bottom surface, and a substantially uniform thickness;a plurality of traces disposed on the top surface of the substrate;a light emitting diode (LED) mounted on the top surface of the substrate, proximate a center of the substrate, and the LED being connected to at least one trace of the plurality of traces;a thermal contact pad disposed on the bottom surface of the substrate; anda reflector coupled to the substrate and substantially surrounding the LED, the reflector defining a reflection surface.
  • 15. The package of claim 14, wherein the reflector comprises a material having high thermal conductivity.
  • 16. The package of claim 14, wherein the reflector plate and the substrate serve as heat sinks for dissipating heat generated by the LED.
  • 17. The package of claim 14, further comprising a lens covering the LED.
  • 18. A light emitting die package, comprising: an electrically insulating substrate comprising a top surface and a bottom surface;a plurality of traces disposed on the top surface of the substrate;a light emitting diode (LED) mounted on the top surface of the substrate and connected to the plurality of traces;a thermal contact pad disposed on the bottom surface of the substrate; anda lens over the LED, the lens sitting on and adhering adheres to the encapsulant, the lens free to move as the encapsulant expands and contracts.
  • 19. A light emitting die package, comprising: an electrically insulating substrate comprising a top surface and a bottom surface;a plurality of traces disposed on the top surface of the substrate;a light emitting diode (LED) mounted on the top surface of the substrate and connected to the plurality of traces;a thermal contact pad disposed on the bottom surface of the substrate; anda lens over the LED, the lens sitting on and adhering adheres to the encapsulant and the lens being, free to move relative to the substrate.
CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of and claims priority to U.S. patent application Ser. No. 12/856,320, filed Aug. 13, 2010 now U.S. Pat. No. 7,976,186, which is a divisional of U.S. patent application Ser. No. 11/703,721, filed Feb. 8, 2007, now U.S. Pat. No. 7,775,685, which is a divisional of U.S. patent application Ser. No. 10/446,532, filed May 27, 2003, now U.S. Pat. No. 7,264,378, which claims the benefit of U.S. Provisional Application Ser. No. 60/408,254 filed Sep. 4, 2002. The entire contents of the above applications and patents are hereby incorporated by reference herein.

US Referenced Citations (138)
Number Name Date Kind
3443140 Jensen May 1969 A
3760237 Jaffe Sep 1973 A
4152618 Abe et al. May 1979 A
4168102 Chida Sep 1979 A
4267559 Johnson et al. May 1981 A
4603496 Latz et al. Aug 1986 A
5119174 Chen Jun 1992 A
5173839 Metz, Jr. Dec 1992 A
5285352 Pastore et al. Feb 1994 A
5433295 Murphy Jul 1995 A
5633963 Rickenbach et al. May 1997 A
5649757 Aleman Jul 1997 A
5785418 Hochstein Jul 1998 A
5789772 Jiang Aug 1998 A
5835661 Tai Nov 1998 A
5841177 Komoto et al. Nov 1998 A
5847507 Butterworth Dec 1998 A
5849396 Ali et al. Dec 1998 A
5851847 Yamanaka Dec 1998 A
5857767 Hochstein Jan 1999 A
5869883 Mehringer et al. Feb 1999 A
5903052 Chen et al. May 1999 A
5907151 Gramann et al. May 1999 A
5959316 Lowery Sep 1999 A
5982090 Kalmanash et al. Nov 1999 A
5998925 Shimizu et al. Dec 1999 A
6060729 Suzuki et al. May 2000 A
6124635 Kuwabara Sep 2000 A
6155699 Miller et al. Dec 2000 A
6159033 Oka Dec 2000 A
6180962 Ishinaga Jan 2001 B1
6238599 Gelorme et al. May 2001 B1
6274924 Carey et al. Aug 2001 B1
6281435 Maekawa Aug 2001 B1
6307272 Takahashi et al. Oct 2001 B1
6318886 Stopa et al. Nov 2001 B1
6329706 Nam Dec 2001 B1
6331063 Kamada et al. Dec 2001 B1
6335548 Roberts et al. Jan 2002 B1
6362964 Dubhashi et al. Mar 2002 B1
RE37707 Bozzini et al. May 2002 E
6429513 Shermer, IV et al. Aug 2002 B1
6444498 Huang et al. Sep 2002 B1
6456766 Shaw et al. Sep 2002 B1
6457645 Gardner, Jr. Oct 2002 B1
6468821 Maeda et al. Oct 2002 B2
6469322 Srivastava et al. Oct 2002 B1
D465207 Williams et al. Nov 2002 S
6480389 Shie et al. Nov 2002 B1
6489637 Sakamoto et al. Dec 2002 B1
6490104 Gleckman et al. Dec 2002 B1
6492725 Loh et al. Dec 2002 B1
6501103 Jory et al. Dec 2002 B1
6525386 Mills Feb 2003 B1
6531328 Chen Mar 2003 B1
6541800 Barnett et al. Apr 2003 B2
6559525 Huang May 2003 B2
6582103 Popovich et al. Jun 2003 B1
6610563 Waitl et al. Aug 2003 B1
6614103 Durocher et al. Sep 2003 B1
6670648 Isokawa et al. Dec 2003 B2
6672734 Lammers Jan 2004 B2
6680491 Nakanishi et al. Jan 2004 B2
6680568 Fujiwara et al. Jan 2004 B2
6707069 Song et al. Mar 2004 B2
6710544 Schliep Mar 2004 B2
6759803 Sorg Jul 2004 B2
6768525 Paolini et al. Jul 2004 B2
6789921 Deloy et al. Sep 2004 B1
6791259 Stokes et al. Sep 2004 B1
6809347 Tasch et al. Oct 2004 B2
6844903 Mueller-Mach et al. Jan 2005 B2
6849867 Roberts et al. Feb 2005 B2
6850001 Takekuma Feb 2005 B2
6864567 Yu Mar 2005 B2
6874910 Sugimoto et al. Apr 2005 B2
6897486 Loh May 2005 B2
6903380 Barnett et al. Jun 2005 B2
6930332 Hashimoto et al. Aug 2005 B2
6943380 Ota et al. Sep 2005 B2
6943433 Kamada Sep 2005 B2
6949772 Shimizu Sep 2005 B2
6960878 Sakano et al. Nov 2005 B2
7002727 Huibers Feb 2006 B2
7044620 Van Duyn May 2006 B2
7078254 Loh Jul 2006 B2
7078728 Ishii et al. Jul 2006 B2
7084435 Sugimoto et al. Aug 2006 B2
7102177 Goh et al. Sep 2006 B2
7118262 Negley Oct 2006 B2
7122884 Cabahug et al. Oct 2006 B2
7192163 Park Mar 2007 B2
7204631 Weber et al. Apr 2007 B2
7244965 Andrews et al. Jul 2007 B2
7264378 Loh Sep 2007 B2
7279719 Suehiro et al. Oct 2007 B2
7280288 Loh Oct 2007 B2
7322732 Negley Jan 2008 B2
7329399 Camaro et al. Feb 2008 B2
7456499 Loh et al. Nov 2008 B2
7659551 Loh Feb 2010 B2
7692206 Loh Apr 2010 B2
7705465 Kimura et al. Apr 2010 B2
7775685 Loh Aug 2010 B2
7976186 Loh Jul 2011 B2
7980743 Loh Jul 2011 B2
8167463 Loh May 2012 B2
8188488 Andrews May 2012 B2
8308331 Loh Nov 2012 B2
20020084462 Tamai et al. Jul 2002 A1
20020093206 Furlong Jul 2002 A1
20030057573 Sekine et al. Mar 2003 A1
20030058650 Shih Mar 2003 A1
20030189830 Sugimoto et al. Oct 2003 A1
20030193083 Isoda Oct 2003 A1
20030201451 Suehiro Oct 2003 A1
20040004435 Hsu Jan 2004 A1
20040023552 Chen Feb 2004 A1
20040222433 Mazzochette Nov 2004 A1
20050001433 Seelin Jan 2005 A1
20050043627 Angelsen et al. Feb 2005 A1
20050093430 Ibbetson et al. May 2005 A1
20050152146 Owen et al. Jul 2005 A1
20050265029 Epstein et al. Dec 2005 A1
20060083017 Wang Apr 2006 A1
20060097385 Negley May 2006 A1
20060098441 Chou May 2006 A1
20060215075 Huang et al. Sep 2006 A1
20060263545 Coenjarts Nov 2006 A1
20060292747 Loh Dec 2006 A1
20070054149 Cheng Mar 2007 A1
20070085194 Mao et al. Apr 2007 A1
20070200127 Andrews Aug 2007 A1
20080231170 Masato et al. Sep 2008 A1
20110121345 Andrews et al. May 2011 A1
20110186896 Loh Aug 2011 A1
20110186897 Loh Aug 2011 A1
20110261554 Loh Oct 2011 A1
Foreign Referenced Citations (64)
Number Date Country
03820849 Aug 2008 CN
200480030943.3 Mar 2011 CN
19945919 Mar 2000 DE
11 2006 001 634 Jul 2013 DE
0965493 Dec 1999 EP
1059678 Dec 2000 EP
1087447 Mar 2001 EP
1179858 Feb 2002 EP
1416219 May 2004 EP
1418628 May 2004 EP
1537603 Jul 2008 EP
1953825 Aug 2008 EP
1680816 Sep 2009 EP
1 953 825 Jul 2013 EP
07-202271 Aug 1995 JP
H09-083018 Mar 1997 JP
09274454 Oct 1997 JP
H10-098215 Apr 1998 JP
10-151804 Jun 1998 JP
H10-321909 Dec 1998 JP
11-163409 Jun 1999 JP
H11-177136 Jul 1999 JP
2000-013962 Jan 2000 JP
2000-277807 Apr 2000 JP
2000-236116 Aug 2000 JP
2000-277807 Oct 2000 JP
2001-036148 Feb 2001 JP
2001-044452 Feb 2001 JP
2001-052513 Feb 2001 JP
2001-111116 Apr 2001 JP
2001-111117 Apr 2001 JP
2001-144333 May 2001 JP
2001-326390 Nov 2001 JP
2002-093206 Mar 2002 JP
2002-185046 Jun 2002 JP
2002-270903 Sep 2002 JP
2002-319711 Oct 2002 JP
2002-368278 Dec 2002 JP
2003-110146 Apr 2003 JP
2003-124525 Apr 2003 JP
2003-197974 Jul 2003 JP
2002103977 Oct 2003 JP
2003298117 Oct 2003 JP
2003-318448 Nov 2003 JP
2003-124528 May 2004 JP
4731906 Jul 2011 JP
10-1991-0007381 May 1991 KR
10-2001-0006914 Jan 2001 KR
10-1082145 Nov 2011 KR
10-1082169 Nov 2011 KR
10-1082235 Nov 2011 KR
10-1082304 Nov 2011 KR
10-1088928 Nov 2011 KR
10-1160037 Jun 2012 KR
10-1244075 Mar 2013 KR
556364 Nov 2001 TW
497758 Aug 2002 TW
517402 Jan 2003 TW
518775 Jan 2003 TW
533604 May 2003 TW
I392105 Apr 2013 TW
WO 9931737 Jun 1999 WO
WO 2004023552 Mar 2004 WO
WO 2005043627 May 2005 WO
Non-Patent Literature Citations (142)
Entry
Japanese Notice of Allowance for JP Appl. 2004-534428 dated Mar. 29, 2011.
Notice of Allowance corresponding to U.S. Appl. No. 11/153,724 dated Apr. 14, 2011.
Taiwanese Office Action/Rejection (English Translation) corresponding to TW Patent Appl. No. 093131884 dated Apr. 15, 2011.
Korean Office Action corresponding to Korean Patent Application No. 10-2011-7002566 dated Apr. 19, 2011.
Korean Office Action corresponding to Korean Patent Application No. 10-2011-7002567 dated Apr. 20, 2011.
Korean Office Action corresponding to Korean Patent Application No. 10-2011-7002568 dated Apr. 20, 2011.
Korean Office Action corresponding to Korean Patent Application No. 10-2011-7002573 dated Apr. 22, 2011.
Non-Final Office Action for U.S. Appl. No. 11/168,018 dated May 9, 2011.
Korean Office Action corresponding to Korean Patent Application No. 10-2006-7007929 dated May 23, 2011.
Japanese Office Action for JP 2008-519523 dated Jun. 14, 2011.
Korean Office Action for Korean Application No. 10-2011-7002575 dated Jun. 2, 2011.
Non-Final Office Action for U.S. Appl. No. 13/022,365 dated Jul. 14, 2011.
Non-Final Office Action for U.S. Appl. No. 13/175,600 dated Jul. 28, 2011.
Non-Final Office Action for U.S. Appl. No. 11/689,868 dated Aug. 30, 2011.
Korean Notice of Allowance for KR Appl. No. 10-2011-7002567 dated Sep. 26, 2011.
Korean Notice of Allowance for KR Appl. No. 10-2011-7002568 dated Sep. 26, 2011.
Korean Notice of Allowance for KR Application No. 10-2011-7002573 dated Oct. 5, 2011.
Final Office Action for U.S. Appl. No. 11/168,018 dated Oct. 13, 2011.
Official Action with Restriction/Election Requirement corresponding to U.S. Appl. No. 10/446,532 dated Feb. 24, 2005.
Non-Final Official Action corresponding to U.S. Appl. No. 10/446,532 dated Jul. 26, 2005.
Non-Final Official Action corresponding to U.S. Appl. No. 10/446,532 dated May 2, 2006.
Official Action with Restriction/Election Requirement corresponding to U.S. Appl. No. 10/692,351 dated Oct. 5, 2004.
Non-Final Official Action corresponding to U.S. Appl. No. 10/692,351 dated Feb. 24, 2005.
Final Official Action corresponding to U.S. Appl. No. 10/692,351 dated Nov. 16, 2005.
Official Action with Advisory Action corresponding to U.S. Appl. No. 10/692,351 dated Apr. 4, 2006.
International Search Report corresponding to PCT International Application No. PCT/US03/27421 dated Nov. 10, 2004.
International Search Report corresponding to PCT International Application No. PCT/US04/34768 dated Apr. 21, 2005.
Supplemental European Search Report corresponding to EP Appl. No. 03794564.9 dated Aug. 22, 2006.
Official Action corresponding to U.S. Appl. No. 11/153,724 dated Nov. 2, 2006.
Notification of International Preliminary Report on Patentability and Written Opinion corresponding to PCT International Application No. PCT/US06/025193 dated Jan. 23, 2007. (mail date).
Supplemental European Search Report corresponding to European Patent Application No. 04795871 dated Mar. 7, 2007.
Official Action corresponding to U.S. Appl. No. 11/153,724 dated May 3, 2007.
Chinese Office Action for Appl. No. 03820849 with English translation dated Jul. 6, 2007.
Official Action corresponding to U.S. Appl. No. 11/153,724 dated Oct. 16, 2007.
Official Action corresponding to U.S. Appl. No. 11/694,046 dated Oct. 25, 2007.
International Search Report and Written Opinion for PCT/US06/025193 dated Oct. 29, 2007.
European Examination Report corresponding to European Patent Application No. 04795871.5 dated Nov. 12, 2007.
Official Action/Restriction Requirement corresponding to U.S. Appl. No. 11/168,018 dated Dec. 11, 2007.
Notification of International Preliminary Report on Patentability and Written Opinion for PCT International Application No. PCT/US06/023195 dated Jan. 3, 2008.
Notification of International Preliminary Report on Patentability and Written Opinion corresponding to PCT International Application No. PCT/US06/025193 dated Jan. 17, 2008.
Official Action corresponding to U.S. Appl. No. 11/168,018 dated Mar. 27, 2008.
Official Action corresponding to U.S. Appl. No. 11/694,046 dated May 7, 2008.
Official Action corresponding to U.S. Appl. No. 11/168,018 dated May 28, 2008.
EPO Notice of Patent Grant for EP 03794564.9 dated Jun. 12, 2008.
Final Office Action for U.S. Appl. No. 11/153,724 dated Jul. 1, 2008.
European Notice of Publication for EP 08157294 dated Jul. 9, 2008 (dated “received” on Jul. 14, 2008).
Chinese Office Action for CN 2004-80030943.3 (with English Translation) dated Jul. 4, 2008 but received Aug. 7, 2008 (incorrectly dated on some docs as “Aug. 4, 2008”).
European Search Report and Written Opinion for EP 08157294.3 dated Aug. 20, 2008.
Office Action for U.S. Appl. No. 11/153,724 dated Oct. 17, 2008.
Office Action with Restriction/Election Requirement dated Oct. 20, 2008 for U.S. Appl. No. 11/689,868.
Non-final Office Action for U.S. Appl. No. 11/694,046 dated Dec. 1, 2008.
Final Office Action corresponding to U.S. Appl. No. 11/168,018 dated Dec. 10, 2008.
Chinese Office Action for CN 2004-80030943.3 with English translation dated Dec. 12, 2008.
Non-final Office Action for U.S. Appl No. 11/689,868 dated Jan. 26, 2009.
Office Action with Restriction/Election Requirement for U.S. Appl. No. 11/703,721 dated Feb. 26, 2009.
European Office Action for EP Appl. No. 08157294.3 dated Mar. 16, 2009.
Final Office Action for U.S. Appl. No. 11/153,724 dated Mar. 23, 2009.
Communication Under Rule 71(3) EPC (with enclosures) regarding intent to grant European patent for Application No. 04795871.5-222 dated Apr. 24, 2009.
Office Action (with English Summary) dated Apr. 28, 2009 regarding Japanese Patent Application No. 2004-534428.
Communication dated May 13, 2009 regarding no Opposition for European Application No. 03794564.9-2222 / Patent No. 1537603.
Official Action corresponding to Japanese Patent Application No. 2006-536764 (with English Translation) dated Jun. 9, 2009.
Official Action corresponding to U.S. Appl. No. 11/168,018 dated Jul. 7, 2009.
Official Action corresponding to U.S. Appl. No. 11/689,868 dated Jul. 17, 2009.
Notice of Allowance dated Jul. 24, 2009 regarding U.S. Appl. No. 11/694,046.
Official Action corresponding to U.S. Appl. No. 11/703,721 dated Aug. 6, 2009.
Decision to Grant from European Patent Office corresponding to European Patent Application No. 1,680,816 dated Sep. 3, 2009.
Official Action and Search Report corresponding to Taiwan Patent Application No. 092123988 dated Sep. 11, 2009 (with English Translation).
Official Action corresponding to Chinese Patent Application No. 2004800309433 (with English Translation) dated Sep. 25, 2009.
Official Action corresponding to U.S. Appl. No. 11/153,724 dated Nov. 9, 2009.
European Search Report corresponding to European Patent Application No, 09171045.9 dated Nov. 23, 2009.
Japanese Office Action (English Translation) corresponding to Japanese Patent Application No. 2006-536764 dated Feb. 2, 2010.
Japanese Office Action (English Translation) corresponding to Japanese Patent Application No. 2004-534428 dated Feb. 23, 2010.
Official Action corresponding to U.S. Appl. No. 11/168,018 dated Mar. 2, 2010.
Notice of Allowance corresponding to U.S. Appl. No. 11/703,721 dated Apr. 16, 2010.
Final Office Action corresponding to U.S. Appl. No. 11/153,724 dated Apr. 27, 2010.
Advisory Action corresponding to U.S. Appl. No. 11/168,018 dated May 13, 2010.
IPO (TW) Notice of Allowance corresponding to TW Patent Application No. 092123988 dated Jun. 8, 2010.
European Office Action corresponding to European Patent Application No. 09171045.9 dated Jun. 18, 2010.
Korean Patent Office Action corresponding to KR 10-2005-7003428 dated Jul. 29, 2010.
Non-Final Office Action for U.S. Appl. No. 12/856,320 dated Sep. 14, 2010.
Non-Final Office Action for U.S. Appl. No. 11/153,724 dated Sep. 15, 2010.
Chinese Patent Certificate dated Oct. 1, 2010 for TW Patent No. I 331380.
Japanese Notice of Issuance for JP 4602345 dated Oct. 8, 2010.
Japanese Office Action/Rejection (English Translation) corresponding to Japanese Patent Appl. No. 2004-534428 dated Oct. 19, 2010.
Chinese Notice of Patent Grant for CN Appl No. 200480030943.3 dated Oct. 29, 2010.
Notice of Allowance corresponding to U.S. Appl. No. 12/856,320 dated Mar. 3, 2011.
Korean Notice of Allowance for KR Appl. No. 10-2011-7002566 dated Sep. 26, 2011.
German Office Action for Application DE 11 2006 001 634.2 dated Nov. 15, 2011.
Non-Final Office Action for U.S. Appl. No. 13/175,600 dated Jan. 4, 2012.
Notice of Allowance for U.S. Appl. No. 13/023,268 dated Jan. 6, 2012.
Non-Final Office Action for U.S. Appl. No. 13/023,263 dated Jan. 26, 2012.
Supplemental Notice of Allowance for U.S. Appl. No. 13/023,268 dated Feb. 1, 2012.
Notice of Allowance for U.S. Appl. No. 13/022,365 dated Feb. 16, 2012.
Notice of Allowance for U.S. Appl. No. 11/689,868 dated Feb. 8, 2012.
Corrected Notice of Allowance for U.S. Appl. No. 11/689,868 dated Mar. 5, 2012.
Notice of Allowance for U.S. Appl. No. 13/023,263 dated May 11, 2012.
Chineese Office Action for Chineese Application No. 201110021562.0 dated Feb. 16, 2012.
Korean Notice of Allowance for KR Appl. No. 10-2006-7007929 dated Mar. 27, 2011.
Japanese Office Action for Application Serial No. JP 2008-519523dated Jun. 19, 2012.
Japanese Office Action for Application Serial No. JP 2008-519523 dated Jun. 21, 2011.
Japanese Office Action for JP 2008-519523 dated Jun. 19, 2012.
Taiwanese Office Action for Application Serial No. TW 093131884 dated Jun. 28, 2012.
Notice of Allowance for U.S. Appl. No. 13/175,600 dated Jul. 9, 2012.
Notification Regarding Oral Hearing for Application No. DE 11 2006 001 634.2 dated Sep. 20, 2012.
Chinese Office Action for Application No. 201110021562.0 dated Sep. 28, 2012.
Japanese Office Action for Application Serial No. JP 2011-032604 dated Oct. 16, 2012.
Japanese Office Action for Application Serial No. JP 2011-032598 dated Oct. 16, 2012.
Non-Final Office Action for U.S. Appl. No. 13/023,263 dated Oct. 17, 2012.
Japanese Office Action for Application Serial No. 2011-032599 dated Oct. 17, 2012.
Japanese Office Action for Application Serial No. 2011-032600 dated Oct. 17, 2012.
Japanese Office Action for Application Serial No. 2011-032601 dated Oct. 17, 2012.
Japanese Office Action for Application Serial No. 2011-032602 dated Oct. 17, 2012.
Japanese Office Action for Application Serial No. 2011-032603 dated Oct. 17, 2012.
German Oral Hearing Summary for Application Serial No. DE 11 2006 001 634.2 dated Nov. 15, 2012.
Non-Final Office Action for U.S. Appl. No. 13/481,334 dated Dec. 20, 2012.
Notice of Allowance for U.S. Appl. No. 13/022,365 dated Dec. 21, 2012.
Non-Final Office Action for U.S. Appl. No. 13/023,263 dated Jan. 10, 2013.
Taiwanese Notice of Allowance for Application No. 093131884 dated Jan. 16, 2013.
Korean Notice of Allowance for Application No. 10-2006-7007929 dated Feb. 6, 2013.
European Intent to Grant for Application No. 08 157 294.3-2222 dated Feb. 6, 2013.
Korean Office Action for Application No. 10-2012-7027757 dated Feb. 14, 2013.
Non-Final Office Action for U.S. Appl. No. 13/023,263 dated Feb. 27, 2013.
Korean Notice of Allowance for KR Appl. No. 10-2006-7007929 dated Jul. 23, 2011.
German Notice of Allowance for Application No. 11 2006 001 634.2 dated Feb. 14, 2013.
Final Japanese Office Action for Application No. 2008-519523 dated Apr. 18, 2013.
Notice of Allowance for U.S. Appl. No. 13/022,365 dated May 10, 2013.
Final Office Action for U.S. Appl. No. 13/023,263 dated May 23, 2013.
Applicant-Initiated Interview Summary for U.S. Appl. No. 13/023,263 dated Jun. 5, 2013.
Korean Notice of Allowance for Application No. 10-2011-7002575 dated Mar. 27, 2012.
Korean Office Action for Application No. 10-2006-7007929 dated Apr. 24, 2012.
Chinese Office Action for Application No. 201110021562.0 dated May 27, 2013.
Final Office Action for U.S. Appl. No. 13/481,334 dated Jun. 27, 2013.
European Decision to Grant for Application No. 08157294.3 dated Jun. 27, 2013.
Korean Notice of Allowance for Application No. 10-2012-7027757 dated Jun. 28, 2013.
Korean Office Action for Application No. 10-2013-7009561 dated Jul. 10, 2013.
Japanese Office Action for Application No. 2011-032598 dated Jul. 25, 2013.
Japanese Office Action for Application No. 2011-032599 dated Jul. 25, 2013.
Japanese Office Action for Application No. 2011-032600 dated Jul. 25, 2013.
Japanese Office Action for Application No. 2011-032601 dated Jul. 25, 2013.
Japanese Office Action for Application No. 2011-032602 dated Jul. 25, 2013.
Japanese Office Action for Application No. 2011-032603 dated Jul. 25, 2013.
Japanese Office Action for Application No. 2011-032604 dated Jul. 25, 2013.
Related Publications (1)
Number Date Country
20110186897 A1 Aug 2011 US
Provisional Applications (1)
Number Date Country
60408254 Sep 2002 US
Divisions (3)
Number Date Country
Parent 12856320 Aug 2010 US
Child 13023273 US
Parent 11703721 Feb 2007 US
Child 12856320 US
Parent 10446532 May 2003 US
Child 11703721 US