BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power switch for a power source of low voltage, and more particularly, to a power switch for transmitting a power source of low voltage between regular mode and deep-power-down mode.
2. Description of the Prior Art
In electronic devices applied with power sources of low voltage, generally a main power source VDD (providing a voltage VDD) and an internal chip power source VCC (providing a voltage VCC) are provided. Under the condition that the power consumption is not critical, normally the main power source VDD is directly connected to the internal chip power source VCC. That is, the voltage VDD equals the voltage VCC, thereby keeping the internal chips having the maximum operating voltage and operating at the fastest speed.
However, for portable electronic devices such as cellular phones, the power consumption is critical, and therefore the internal components such as memories and control chips have to be able to function under low power condition. Consequently deep-power-down mode is utilized for reducing power consumption of the portable electronic devices. The deep-power-down mode means that under the condition that the portable electronic device is not turned off, the internal chip power source is turned off. More particularly, in deep-power-down mode, the main power source VDD is still turned on and keeps providing the voltage VDD and the internal chip power source VCC is turned off to stop providing the voltage VCC. In this way, the power consumption of the internal chips of the portable electronic device can be reduced when the portable electronic device is in the sleep mode.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a diagram illustrating a conventional power switch QP1 for achieving the deep-power-down mode. FIG. 2 is a timing diagram illustrating the control signal for the conventional power switch QP1. As shown in FIG. 1, the power switch QP1 is a P channel Metal Oxide Semiconductor (PMOS) transistor. The first end (source) of the power switch QP1 is coupled to the main power source VDD, the control end (gate) of the power switch QP1 receives a gate control signal SGP, and the second end (drain) of the power switch QP1 outputs the power source VCC according to the gate control signal SGP. The power source VDD can be the main power source of the portable electronic device, and the power source VCC can be the internal chip power source for providing voltage VCC to the internal chips of the portable electronic device. As shown in FIG. 2, the voltage of the gate control signal SGP falls between the voltages VDD and VSS (ground). Generally, when the power switch QP1 is to be turned on (the first end of the power switch QP1 is coupled to the second of the power switch QP1 for outputting the voltage VCC), the voltage of the gate control signal SGP has to fall to the voltage VSS; on the other hand, when the power switch QP1 is to be turned off (the first end of the power switch QP1 is not coupled to the second of the power switch QP1 and consequently the voltage VCC is not outputted), the voltage of the gate control signal SGP has to rise to the voltage VDD. In this way, the internal chip power source can be switched between the regular mode and the deep-power-down mode of the portable electronic device for meeting the requirement of the high speed in the regular mode and the power saving in the deep-power-down mode.
Generally, when the main power source VDD is high enough, the voltage drop between the voltages VDD and VCC is ignorable. However, when the main power source VDD provides a lower voltage (such as 1.8 volts or lower than that), the voltage drop between the voltages VDD and VCC cannot be ignorable. Since the gate control signal SGP cannot have the power switch QP1 turn on completely, causing considerable resistance on the power switch QP1, the voltage VCC would be much lower than the voltage VDD and it possibly effects the normal operations of the chips.
SUMMARY OF THE INVENTION
The present invention provides a power switch for transmitting a power source providing a low voltage between regular mode and deep-power-down mode. The power switch comprises a first gate control circuit and a first switch. The first gate control circuit is disposed for generating a first gate control signal according to a control signal. Voltage of the first gate control signal is lower than ground. The first switch comprises a first end, coupled to the power source, a control end coupled to the first gate control circuit for receiving the first gate control signal, and a second end for outputting the power source. The first end of the first switch is coupled to the second end of the first switch when the first switch receives the first gate control signal.
The present invention further provides a power switch for transmitting a power source providing a low voltage between regular mode and deep-power-down mode. The power switch comprises a first gate control circuit and a first switch. The first gate control circuit is disposed for generating a first gate control signal according to a control signal. Voltage of the first gate control signal is higher than the low voltage. The first switch comprises a second end coupled to the power source, a control end coupled to the first gate control circuit for receiving the first gate control signal, and a first end for outputting the power source. The first end of the first switch is coupled to the second end of the first switch when the first switch receives the first gate control signal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a conventional power switch for achieving the deep-power-down mode.
FIG. 2 is a timing diagram illustrating the control signal for the conventional power switch.
FIG. 3 is a diagram illustrating a power switch according to a first embodiment of the present invention.
FIG. 4 is a timing diagram illustrating the control signal for the power switch according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating a power switch according to a second embodiment of the present invention.
FIG. 6 is a timing diagram illustrating the control signal for the power switch according to the second embodiment of the present invention.
FIG. 7 is a diagram illustrating a power switch according to a third embodiment of the present invention.
FIG. 8 is a timing diagram illustrating the control signal for the power switch according to the third embodiment of the present invention.
DETAILED DESCRIPTION
Please refer to FIG. 3 and FIG. 4. FIG. 3 is a diagram illustrating a power switch SW1 according to a first embodiment of the present invention. FIG. 4 is a timing diagram illustrating the control signal for the power switch SW1 according to the first embodiment of the present invention. As shown in FIG. 3, the power switch SW1 comprises a switch QP2 and a gate control circuit GC1. The switch QP2 is a PMOS transistor. The first end (source) of the switch QP2 is coupled to a main power source VDD, the control end (gate) of the switch QP2 receives a gate control signal SGP, and the second end (drain) of the switch QP2 outputs the power source VCC according to the gate control signal SGP. The gate control circuit GC1 is coupled to the control end of the switch QP2 for outputting the gate control signal SGP according to a control signal S1. As shown in FIG. 4, the voltage of the gate control signal SGP falls between the voltage VDD and a voltage VA which is lower than the voltage VSS. When the switch QP2 is to be turned on (the first end of the switch QP2 is coupled to the second of the switch QP2 for outputting the voltage VCC), the control signal S1 is outputted to the gate control circuit GC1 so that the voltage of the gate control signal SGP falls to the voltage VA which is below the voltage VSS for completely turning on the switch QP2; on the other hand, when the switch QP2 is to be turned off (the first end of the switch QP2 is not coupled to the second of the switch QP2 and consequently the voltage VCC is not outputted), the control signal S1 is not outputted to the gate control circuit GC1 so that the voltage of the gate control signal SGP rises to the voltage VDD. Since when the switch QP2 is turned on by the gate control signal SGP whose voltage is lower than the voltage VSS, the switch QP2 is turned on completely and the resistance of the switch QP2 is reduced. Consequently the voltage drop on the switch QP2 is reduced and the difference between the voltages VDD and VCC is reduced as well. Therefore, the problem generated by the conventional power switch is solved and the internal chips can still function well. Furthermore, in order to reduce the body effect of the MOS transistor, the body (the third end) of the switch QP2 is coupled to the first end of the switch QP2. Additionally, the gate control circuit GC1 can be realized with a charge pump.
Please refer to FIG. 5 and FIG. 6. FIG. 5 is a diagram illustrating a power switch SW2 according to a second embodiment of the present invention. FIG. 6 is a timing diagram illustrating the control signal for the power switch SW2 according to the second embodiment of the present invention. As shown in FIG. 5, the power switch SW2 comprises a switch QN2 and a gate control circuit GC2. The switch QN2 is an N channel Metal Oxide Semiconductor (NMOS) transistor. The second end (drain) of the switch QN2 is coupled to a main power source VDD, the control end (gate) of the switch QN2 receives a gate control signal SGN, and the first end (source) of the switch QN2 outputs the power source VCC according to the gate control signal SGN. The gate control circuit GC2 is coupled to the control end of the switch QN2 for outputting the gate control signal SGN according to a control signal S1. As shown in FIG. 6, the voltage of the gate control signal SGN falls between the Voltage VSS and a voltage VB which is higher than the voltage VDD. When the switch QN2 is to be turned on (the first end of the switch QN2 is coupled to the second of the switch QN2 for outputting the voltage VCC), the control signal S1 is outputted to the gate control circuit GC2 so that the voltage of the gate control signal SGN rises to the voltage VB which is above the voltage VDD for completely turning on the switch QN2; on the other hand, when the switch QN2 is to be turned off (the first end of the switch QN2 is not coupled to the second of the switch QN2 and consequently the voltage VCC is not outputted), the control signal S1 is not outputted to the gate control circuit GC2 so that the voltage of the gate control signal SGN falls to the voltage VSS. Since when the switch QN2 is turned on by the gate control signal SGN whose voltage is higher than the voltage VDD, the switch QN2 is turned on completely and the resistance of the switch QN2 is reduced. Consequently the voltage drop on the switch QN2 is reduced and the difference between the voltages VDD and VCC is reduced as well. Therefore, the problem generated by the conventional power switch is solved and the internal chips can still function well. Furthermore, in order to reduce the body effect of the MOS transistor, the body (the third end) of the switch QN2 is coupled to the first end of the switch QN2. Additionally, the gate control circuit GC2 can be realized with a charge pump.
Please refer to FIG. 7 and FIG. 8. FIG. 7 is a diagram illustrating a power switch SW3 according to a third embodiment of the present invention. FIG. 8 is a timing diagram illustrating the control signal for the power switch SW3 according to the third embodiment of the present invention. As shown in FIG. 7, the power switch SW3 comprises two switches QP2 and QN2, and two gate control circuits GC1 and GC2. The switch QP2 is a PMOS transistor, and the switch QN2 is an NMOS transistor. The first end (source) of the switch QP2 is coupled to a main power source VDD, the control end (gate) of the switch QP2 receives a gate control signal SGP, and the second end (drain) of the switch QP2 outputs the power source VCC according to the gate control signal SGP. The second end (drain) of the switch QN2 is coupled to the main power source VDD, the control end (gate) of the switch QN2 receives a gate control signal SGN, and the first end (source) of the switch QN2 outputs the power source VCC according to the gate control signal SGN. The gate control circuits GC1 and GC2 are respectively coupled to the control end of the switch QP2 and the control end of the switch QN2 for outputting the gate control signals SGP and SGN according to a control signal S1. As shown in FIG. 8, the voltage of the gate control signal SGP falls between the voltage VDD and a voltage VA which is lower than the voltage VSS, and the voltage of the gate control signal SGN falls between the voltage VSS and a voltage VB which is higher than the voltage VDD. When the switch QP2 is to be turned on (the first end of the switch QP2 is coupled to the second of the switch QP2 for outputting the voltage VCC) and the switch QN2 is to be turned on (the first end of the switch QN2 is coupled to the second of the switch QN2 for outputting the voltage VCC), the control signal S1 is outputted to the gate control circuits GC1 and GC2 SO that the voltage of the gate control signal SGP falls to the voltage VA which is below the voltage VSS for completely turning on the switch QP2 and the voltage of the gate control signal SGN rises to the voltage VB which is above the voltage VDD for completely turning on the switch QN2; on the other hand, when the switch QP2 is to be turned off (the first end of the switch QP2 is not coupled to the second of the switch QP2 and consequently the voltage VCC is not outputted) and the switch QN2 is to be turned off (the first end of the switch QN2 is not coupled to the second of the switch QN2 and consequently the voltage VCC is not outputted), the control signal S1 is not outputted to the gate control circuits GC1 and GC2 so that the voltage of the gate control signal SGP rises to the voltage VDD and the voltage of the gate control signal SGN falls to the voltage VSS. Since when the switch QP2 is turned on by the gate control signal SGP whose voltage is lower than the voltage VSS, and the switch QN2 is turned on by the gate control signal SGN whose voltage is higher than the voltage VDD, the switch QP2 is turned on completely and the resistance of the switch QP2 is reduced, and the switch QN2 is turned on completely and the resistance of the switch QN2 is reduced. Consequently the voltage drop on the switches QP2 and QN2 are reduced and the difference between the voltages VDD and VCC is reduced as well. Therefore, the problem generated by the conventional power switch is solved and the internal chips can still function well. Furthermore, in order to reduce the body effect of the MOS transistor, the body (the third end) of the switch QP2 is coupled to the first end of the switch QP2, and the body (the third end) of the switch QN2 is coupled to the first end of the switch QN2. The advantage of the power switch SW3 is that the outputted power source VCC is still stable when the main power source VDD varies since the switches QP2 and QN2 are complementary to each other.
To sum up, the power switch of the present invention for transmitting power sources of low voltage utilizes gate control circuits to reduce the voltage drop on the power switch. Therefore, when the main power source provides a low voltage, in regular mode, the internal chip power source still provides almost same voltage as the voltage provided from the main power source to the internal chips so as to allow the internal chips to operate normally, and in deep-power-down mode, the internal chip power source can be effectively turned off, providing great convenience.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Patent Application
20100026372
