Patent Grant
8654483
1. Field of the Invention
The present invention relates in general to the field of electronics, and more specifically to a power control system and method with voltage-based monitoring for over current protection.
2. Description of the Related Art
Power control systems often utilize one or more power conversion stages to convert alternating current (AC) voltages to direct current (DC) voltages or perform DC-to-DC conversions. For example, power control systems often contain a power factor correction (PFC) stage to provide power factor correction and regulate a link voltage, an output stage to provide output power to a load, and an isolation stage to isolate the PFC stage from the output stage.
The PFC stage and the output stage of a power control system have a one hundred percent (100%) rated power and a maximum power. The rated power refers to power available from the power control system under nominal operation conditions. The maximum power refers to a percentage of the rated power that can be supplied by the power control system for at least a limited period of time while maintaining a regulated output voltage and without damaging the power control systems and/or the load. Once the load begins demanding more power than the maximum power of the power control system, an output current of the output stage will increase, and an output voltage of the output stage will decrease. A controller that controls the power control system monitors the output current. When the output current exceeds a predetermined threshold, the controller will enter an over-current protection mode. However, circuitry used to sense the current can cause overall power losses and, thus, lower the efficiency of the power control system.
The power control system 100 includes a controller 114 to regulate a link voltage VLINK of PFC stage 102 and control isolation stage 106. Controller 114 generates a pulse-width modulated control signal CS0 to control power factor correction and regulate the link voltage VLINK of PFC stage 102. In one embodiment, PFC stage 102 is a boost-type, switching power converter, and control signal CS0 is a switch control signal that controls conversion of input voltage VX to link voltage VLINK. Controller 114 monitors voltages VX and VLINK to generate switch control signal CS0.
Isolation stage 106 isolates the PFC stage 102 from the output stage 104. Depending upon the type of PFC stage 102, the link voltage VLINK is either a multiple or a fraction of the input voltage VX. In either situation, the load 116 may not be compatible with the value of the link voltage VLINK or compatible with a DC voltage in general. Isolation stage 106 includes a transformer 118 to convert the link voltage VLINK into the output voltage VOUT. Transformer 118 is a flyback type transformer that includes switch 124. Control signal CSF controls the conductivity of switch 124 to convert link voltage VLINK into a time-varying, primary-side voltage VP to allow the primary-side windings 120 of transformer 118 to alternately store energy and then transfer energy to the secondary-side windings 122. In one embodiment, switch 124 is a field effect transistor (FET). Transformer 118 converts the primary side voltage VP into a secondary voltage VS. A variety of other topologies are well-known for isolation stage 106, such as half-bridge and full-bridge topologies as discussed in chapter 6 of Fundamentals of Power Electronics—Second Edition by Erickson and Maksimović, publisher Springer Science+Business Media, LLC, copyright 2001 (“Fundamentals of Power Electronics”).
The output stage 104 converts the secondary voltage VS into the output voltage VOUT. The topology of output stage 104 is a matter of design choice. Exemplary topologies are a half-bridge buck converter and a full-bridge buck converter. Examples of output stage 104 are also discussed in chapter 6 of Fundamentals of Power Electronics.
Power control system 100 supplies load 116 with output voltage VOUT and output current iOUT. The load 116 is any device that can utilize the power provided by output stage 104. Controller 114 regulates the link voltage VLINK and the primary-side voltage VP to establish a particular value for the secondary-side load current iOUT. Controller 114 regulates the primary-side voltage VP by controlling the duty cycles of control signal CSF. Controller 114 obtains a value of the output current iOUT by sensing a feedback voltage VR
PFC stage 102 has a rated power of PRATED and a maximum power of PMAX. If load 116 demands more power than the maximum power PMAX, the output current iOUT increases and the output voltage VOUT decreases. If the output current iOUT exceeds a predetermined threshold value, the power control system 100 enters an over current protection mode. The particular over current protection mode involves, for example, turning the power control system 100 OFF to protect components of the power control system 100 from damage.
Power efficiency is generally a concern when designing and utilizing power control system 100. However, the voltage drop corresponding to the feedback voltage VR
In one embodiment of the present invention, an apparatus includes a controller to control a power supply and provide over current protection. The controller is configured to provide over current protection for the power supply using power utilization information and an output voltage of an output stage of the power supply. The power utilization information represents power utilization of the power supply.
In another embodiment of the present invention, a method includes controlling a power supply. Controlling the power supply includes using power utilization information and an output voltage of an output stage of the power supply to provide over current protection for the power supply. The power utilization information represents power utilization of the power supply.
In a further embodiment of the invention, an apparatus includes a controller to control a switching power supply and provide over current protection. The controller is configured to monitor a link voltage of the switching power converter and to determine a power utilization factor. The controller is further configured to monitor an output voltage of the switching power converter and to determine if the power utilization factor is greater than a power utilization factor threshold value. The controller is further configured to determine if an output voltage of the switching power converter is greater than an output voltage threshold value. If the power utilization factor is greater than a power utilization factor threshold value and the output voltage is less than the output voltage threshold value, then enter an over current protection mode. The power utilization factor represents power utilization of the power supply.
The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.
A power control system reduces power losses while monitoring for an over current event by utilizing an over current protection method that detects the over current event based on an output voltage of an output stage of the power control system and power utilization information. The power utilization information represents power utilization of a power supply of the power control system. In at least one embodiment, the power utilization of the power supply is represented as a normalized, power utilization factor. In at least one embodiment, the power control system detects the over current event by sensing only voltages and, in at least one embodiment, without sensing an output current in an output stage of the power control system. Since the output current is not sensed, the power control system avoids power losses otherwise associated with sensing the output current.
In at least one embodiment, addition to the output stage, the power control system includes the power factor correction (PFC) stage to provide power factor correction and, in at least one embodiment, to regulate an output voltage of the PFC stage. The power control system also includes an isolation stage to isolate the PFC stage from the output stage while allowing the PFC stage to transfer energy to the output stage. In at least one embodiment, the power control system also includes a controller to control the PFC stage and the isolation stage. The controller includes an over current protection module (“OCP module”). In at least one embodiment, the OCP module determines the power utilization factor PUTIL using voltages sensed from the PFC stage and/or the isolation stage. In at least one embodiment, the OCP module responds to the over current event by entering an over current protection mode.
In at least one embodiment, the OCP module 204 determines the power utilization factor PUTIL using the link voltage VLINK and a reference voltage VREF. The OCP module 204 utilizes the output voltage VOUT of output stage 210 of power supply 201 and the power utilization factor PUTIL to determine when to enter an over current protection mode to, for example, protect power control system 200 from an over current event. In at least one embodiment, an over current event refers to an increase in the output current iOUT above a predetermined output current threshold iOUT
As subsequently described in more detail, the rated power PRATED of power control system 200 represents an amount of power that power supply 201 can nominally supply to load 212. For example, a rated power PRATED of 100 W indicates that the power supply 201 can nominally supply load 212 with up to 100 W of power. Power supply 201 also has a maximum power PMAX. The maximum power PMAX is generally a percentage increase of, for example 25%, over the rated power PRATED. Thus, in at least one embodiment, for a rated power PRATED of 100 W and a 25% increase, a maximum power PMAX is 125% of the rated power PRATED, which equals 125 W. The maximum power PMAX represents an amount of power that power supply 201 can supply to load 212 while maintaining an approximately constant output voltage VOUT. Equation [1] represents an exemplary relationship between the output power P of power supply 201, the output current iOUT, and the output voltage VOUT:
P=VOUT·iOUT [1],
where P represents the power supplied by power supply 201, VOUT represents the output voltage of output stage 210, and iOUT represents the output current of output stage 210.
Power control system 200 maintains an approximately constant output voltage VOUT if the power demand of load 212 is less than or equal to the maximum power PMAX of power supply 201. If load 212 begins to demand more power from power supply 201 than the maximum power PMAX, then P equals PMAX in Equation [1], output current iOUT will increase in proportion to the power demand increase, and the output voltage VOUT will decrease in accordance with Equation [1]. In at least one embodiment, when power utilization factor PUTIL equals 1 (indicating that the power control system is generating 100% of rated power) and the output voltage VOUT decreases to a predetermined threshold voltage VOUT
For the power control system 200 to convert the input voltage VX into the output voltage VOUT, the PFC stage 206 receives the input voltage VX. In at least one embodiment, the input voltage VX is a rectified alternating current (AC) voltage, such as a rectified 60 Hz/110 V line voltage in the United States of America or a rectified 50 Hz/220 V line voltage in Europe. The particular topology of the PFC stage 206 is a matter of design choice. For example, PFC stage 206 can be a switching type boost, buck, buck-boost, or Cúk converter. The PFC stage 206 generates a link voltage VLINK. In at least one embodiment, the link voltage VLINK is a regulated, approximately DC voltage.
The power supply 201 also includes an isolation stage 208 that isolates the PFC stage 206 from an output stage 210 and converts the link voltage VLINK into a secondary voltage VS. The particular topology of the isolation stage 208 is a matter of design choice. For example, the isolation stage 208 can be a transformer based isolation stage such as a flyback, full bridge, or half bridge transformer.
The output stage 210 receives the secondary voltage VS and provides an output voltage VOUT and an output current iOUT to load 212. The particular topology of the output stage 210 is also a matter of design choice. For example, output stage 210 can have a flyback topology. The load 212 can be any load for which power control system 200 can provide power. Examples of load 212 include lamps, such as light emitting diode and gas discharge type lamps, cellular telephones, personal computer (PCs) computing devices including personal digital assistants, and other electronic devices. Additionally, in at least one embodiment, isolation stage 208 and output stage 210 are separate and distinct as shown in
In addition to providing over current protection, controller 202 generates a control signal CS1 for PFC stage 206 to control power factor correction of PFC stage 206 and, in at least one embodiment, to also regulate the link voltage VLINK to a particular value. U.S. patent application Ser. No. 11/967,269, entitled “POWER CONTROL SYSTEM USING A NONLINEAR DELTA-SIGMA MODULATOR WITH NONLINEAR POWER CONVERSION PROCESS MODELING”, filed Dec. 31, 2007, inventor John L. Melanson, and assignee Cirrus Logic, Inc. (referred to herein as “Melanson I”) describes exemplary generation of control signal, such as control signal CS1, and control of PFC stage implemented as a switching power converter. Controller 202 also generates control signals CS2 through CSN to control isolation stage 208, and N is an integer index and is greater than or equal to 2. Melanson I describes exemplary generation of control signals CS2 through CSN. In at least one embodiment, controller 202 can be implemented as one or more physically distinct circuits. For example, in at least one embodiment, controller 202 is a single integrated circuit. In at least one embodiment, controller 202 is implemented as two embodiments with one embodiment controlling PFC stage 206 and one embodiment controlling isolation stage 208. Melanson I is hereby incorporated by reference in its entirety.
The power control system 300 includes a controller 314 to regulate a link voltage VLINK of PFC stage 302 and control isolation stage 306. Controller 314 also protects power control system 300 when load 332 is demanding more than the rated power PRATED of power supply 301 and the output voltage decreases below a predetermined threshold value VOUT
The PFC stage 302 includes an inductor 318 that conducts a current iL. When switch 316 is ON, diode 320 is reverse biased, and inductor current iL energizes inductor 318. When switch 316 is OFF, diode 320 is forward biased, and inductor current iL charges link capacitor 322. The link voltage VLINK across link capacitor 322 remains approximately constant during operation of PFC stage 302. Controller 314 operates PFC stage 302 in discontinuous conduction mode (DCM). In DCM, the inductor current iL decreases to zero while switch 316 is OFF and remains at zero for a finite time before switch 316 turns ON.
Isolation stage 306 isolates the PFC stage 302 from the output stage 304 and converts the DC link voltage VLINK into an AC voltage so that transformer 328 can transfer energy from link capacitor 322 via the primary side windings 324 to the secondary-side windings 326 of transformer 328. Isolation stage 306 also includes a primary-side transformer interface 330. The primary-side transformer interface 330 can be any type of interface. In at least one embodiment, primary-side transformer interface 330 is a half-bridge interface as described in U.S. patent application Ser. No. 12/415,830, entitled “PRIMARY-SIDE BASED CONTROL OF SECONDARY-SIDE CURRENT FOR A TRANSFORMER,” inventor John L. Melanson, Attorney Docket No. 1812-IPD, and filed on Mar. 31, 2009 describes exemplary methods and systems and is incorporated by reference in its entirety and referred to herein as Melanson II. Control signals CS2 through CSN control isolation stage 306, and N is an integer index that is greater than or equal to 2. A variety of other topologies are well-known for isolation stage 306, such as full-bridge topologies as discussed in chapter 6 of Fundamentals of Power Electronics.
The output stage 304 converts the secondary voltage VS into the output voltage VOUT. The topology of output stage 304 is a matter of design choice. In at least one embodiment, the output stage 304 is a half-bridge, buck converter as described in Melanson II. Other exemplary topologies, such as a full-bridge buck converter, are also discussed in chapter 6 of Fundamentals of Power Electronics.
Power supply 301 supplies load 332 with output voltage VOUT and output current iOUT. Controller 314 regulates the link voltage VLINK and the primary-side voltage VP to establish a particular value for the secondary-side load current iOUT. Controller 314 includes a power utilization module (“PUTIL, module”) 333 which represents one embodiment of power utilization module 203. The PUTIL module 333 generates the power utilization factor PUTIL. The power utilization factor PUTIL varies as the difference between the reference voltage VREF and the link voltage VLINK, as represented by error signal ev from error generator 336 varies. The link voltage VLINK varies in proportion to the power demand by load 332. Accordingly, the power utilization factor PUTIL also varies in proportion to power demand by load 332. As previously described, the power utilization factor PUTIL is a normalized representation of the power demand of load 332. In at least one embodiment, the reference voltage VREF is set to a desired value of the link voltage VLINK. For example, in at least one embodiment, the desired value of link voltage VLINK is 100V, so the reference voltage VREF is set to 100 V. The PUTIL module 333 includes an integral signal path 338 and a proportional signal path 340.
The integral signal path 338 includes an integrator 342 to integrate the error signal ev and also includes a gain module 344 to multiply the integral of error signal ev by a gain factor g2 and generate the integrated output signal IPW. The proportional path 340 includes a gain module 346 to multiply the error signal ev by a gain factor g1 and generate the proportional output signal PPW. Adder 348 adds the integrated output signal IPW and the proportional output signal PPW to generate the power utilization factor PUTIL. The values of gain factors g1 and g2 are a matter of design choice. The gain factors g1 and g2 affect the responsiveness of OCP module 314 in tracking changes in power demand by load 332. Exemplary values of gain factors g1 and g2 are set forth in the emulation code of FIGS. 8-31 in Melanson I. Additionally, in at least one embodiment, the link voltage VLINK, the reference voltage VREF, and the output voltage VOUT monitored by the PUTIL module 333 are scaled versions of the actual voltages.
Controller 314 also includes OCP module 334 to detect an over current event in power supply 301. The OCP module 334 also provides an over current protection signal OCP that causes power control system 300 to enter an over current protection mode. In at least one embodiment, over current protection signal OCP causes power control system 300 to enter an over current protection mode when power supply 301 is operating above 100% rated power PRATED.
In operation 406, OCP mode module 334 monitors the output voltage VOUT. The OCP module 334 stores a power utilization factor threshold PUTIL
In operation 408, the OCP mode module 334 determines whether the power utilization factor PUTIL is greater than the power utilization factor threshold PUTIL
To protect power control system 300 from an output current iOUT exceeding the maximum allowable output current iOUT
Thus, in at least one embodiment, a power control system can provide overcurrent protection using sensed voltages without incurring current sensing power losses.
Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.
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