Patent Application
20240137018
This disclosure relates generally to power transmission gates, and more particularly to power transmission gates using a charge pump.
Conventional transmission gates include an n-channel metal oxide semiconductor field effect transistor (MOSFET) and a p-channel MOSFET in which a substrate terminal is not connected internally to a source terminal. The pair of transistors are connected in parallel with the drain and source terminals of the two transistors connected together. The gate terminals are connected to each other by an inverter to form a control terminal. A parasitic substrate diode exists between source/drain and substrate. The substrate terminals are connected to respective supply potentials to ensure the parasitic substrate diode is always reversely biased and so does not affect signal flow. The substrate terminal of the p-channel MOSFET is thus connected to the positive supply potential, and the substrate terminal of the n-channel MOSFET connected to the negative supply potential. For the p-channel MOSFET to achieve the same resistivity as the n-channel MOSFET, the area of the p-channel MOSFET must be approximately twice the area of n-channel MOSFET.
The manner and process of making and using the disclosed embodiments may be appreciated by reference to the figures of the accompanying drawings. It should be appreciated that the components and structures illustrated in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principals of the concepts described herein Like reference numerals designate corresponding parts throughout the different views. Furthermore, embodiments are illustrated by way of example and not limitation in the figures, in which:
Described is a power transmission gate which includes a charge pump, an NMOS transistor, and a gate driver circuit configured to power (or bias or “drive”) a gate of the NMOS transistor. With this arrangement, a power transmission gate capable of achieving substantially the same resistance provided by prior art power transmission gates while having a footprint of approximately just over one NMOS size unit is provided. Moreover, transmission gates provided in accordance with the concepts described herein may have a lower resistance per unit area and/or a lower overall parasitic capacitance compared with conventional transmission gates
In embodiments a power transmission gate includes a switch having an input terminal, an output terminal, a control terminal, and a body terminal, the switch configured to receive an input voltage at the input terminal thereof and, in response to a control signal having a first value being provided to the control terminal, pass the input voltage to the output terminal of the switch; and a first capacitance between the input and control terminals of the switch and configured to maintain a substantially constant voltage across the input and control terminals of the switch; and a charge pump coupled to the control terminal of the switch, wherein in response to the charge pump receiving an input voltage, the charge pump applies a drive voltage to the control terminal of the switch, wherein a voltage level of the drive voltage is larger than a voltage level of the input voltage.
The power transmission gate may include one or more of the following features independently or in combination with one or more other features to include: a voltage source selectively coupled to the control terminal of the switch; the charge pump includes a capacitor configured to charge a gate of the switch to about twice the input voltage; the charge pump comprises a switch network that is connected to a capacitor configured to charge a gate of the switch to about twice the input voltage; a switch network configured to operate at a variable clock frequency; a switch network configured to operate at a variable clock frequency having a relatively high value during an initial turn-on of the switch, and configured to reduce in value after a particular period of time; the switch is an NMOS transistor; the charge pump has a Disckson or Pelliconi topology; the power transmission gate satisfies one or more safe operating area conditions of an NMOS transistor; the power transmission gate is configured to carry currents in the order of amperes; the power transmission gate is configured to respond to changes in the input voltage that occur in the order of nanoseconds.
In embodiments, the switch may be provided as n-channel metal oxide semiconductor field effect transistor (n-channel MOSFET) the input terminal of the switch is a source terminal of the n-channel MOSFET, the output terminal of the switch is a drain terminal of the n-channel MOSFET, the control terminal of the switch is a gate terminal of the n-channel MOSFET.
In embodiments, a voltage source is configured to apply a voltage to the control terminal of the switch having a value equal to about a maximum possible voltage for the input voltage; and the voltage at the control terminal of the switch changes proportionally with respect to the input voltage changing between zero volts and the maximum possible voltage for the input voltage.
In embodiments, the power transmission gate may include a switch network is configured to protect a gate-source breakdown voltage of a diode of the charge pump.
In embodiments, the power transmission gate may include a second capacitor with first capacitor having a larger capacitance value than the second capacitor.
In embodiments, the power transmission gate may further include a shutdown circuit having a terminal coupled to the control terminal of the switch and configured to discharge the voltage at the control terminal of the switch when the switch is disabled.
In embodiments, the power transmission gate is a pulse shaping network switch.
In embodiments, the power transmission gate includes a body control circuit that is configured to control a body of the switch.
In embodiments, the power transmission gate includes a body control circuit which includes a first NMOS transistor that is configured to drive the body of the switch to the input voltage when the switch is enabled; and a second NMOS transistor that is configured to drive the body of the switch to a negative supply voltage when the switch is disabled.
In accordance with a further aspect of the concepts described herein, a system includes the power transmission gate and a supply modulator configured to provide, from a set of possible input voltage levels, the input voltage to the power transmission gate.
In embodiments, the supply modulator is configured to provide, from the set of possible input voltage levels, the input voltage to at least one additional power transmission gate.
In embodiments, the power transmission gate is electrically isolated from the at least one additional power transmission gate.
It should be appreciated that individual elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable or reasonable sub-combination. It should also be appreciated that other embodiments not specifically described herein are also within the scope of the following claims. It should thus be appreciated that the concepts, circuits, systems and techniques described herein could be used in any application where the following conditions are met: a voltage is passed from input to output; and/or a higher voltage rail exists that is equal to or greater than the maximum input voltage. The concepts, circuits, systems and techniques described herein can be applied in a wide variety of different technology areas (i.e., different nodes) and/or at different voltages.
In power transmission and/or envelope tracking applications, a plurality of power transmission gates (which can include “pulse shaping network switches” that are used in RF applications with a filtering network) can be used to provide electrical isolation between a plurality of outputs (e.g., one or more signal paths leading from one or more supply modulator outputs to one or more supply terminals of a power amplifier, for example). Exemplary pulse shaping networks and their associated switches/switch elements are described in U.S. patent application Ser. No. 16/369,667 entitled “MULTI-STAGE PULSE SHAPING NETWORK”, filed Mar. 29, 2019, now U.S. Pat. No. 10,992,265, issued Apr. 27, 2021, the entire contents of which are hereby incorporated by reference herein.
These power transmission gates may be coupled to one or more outputs of a supply modulator (i.e., power transmission gates can follow a supply modulator). A supply modulator may be configured to provide, from a set of possible input voltage levels, one or more selected output voltage levels at one or more outputs thereof. Each of the power transmission gates can pass the selected output voltage level to a respective output thereof. The power transmission gate outputs may, for example, be coupled to a supply terminal of a power amplifier (PA).
Referring now to
The power transmission gates 104a-n may be configured to satisfy one or more criteria for the particular application. For example, the power transmission gates 104a-n can be configured to respond relatively quickly (e.g., in the order of nanoseconds) to changes in the input voltages because the output of the supply modulator 102 can change in nanoseconds. Further, the power transmission gates 104a-n can be configured to provide electrical isolation between their respective outputs. The power transmission gates 104a-n can also be configured to have relatively low resistances and carry relatively large currents (e.g., in the order of amperes). In some implementations, the power transmission gates 104a-n can be configured to carry currents having values of about 2 amperes at a voltage of about 4.6 volts, although other applications having larger voltages and/or currents are possible as well. In some implementations, the power transmission gates 104a-n can be configured to operate at a maximum power of about 10 watts, although other applications having larger power limits are possible as well. In some implementations, the power transmission gates 104a-n can each have a relatively low resistance (e.g., of about 30 milliohms).
Traditionally, to achieve one or more of these criteria, the power transmission gates 104a-n would be required to have a particular size (i.e., an area (or “footprint”) occupied on an IC or a die by the power transmission gate) determined by the types of components required to achieve the criteria.
The power transmission gate 200 includes a first amplifier 204a that is configured to power a gate of the NMOS transistor 202a and a second amplifier 204b that is configured to power a gate of the PMOS transistor 202b. The amplifiers 204a, 204b operate according to a control signal 206. Each of the amplifiers 204a, 204b is configured to receive a negative power supply Vss and a positive power supply Vdd. The input voltage received by the complementary switch pair 202 can be between the voltages provided by the negative power supply Vss and the positive power supply Vdd.
To achieve the same resistance as the NMOS transistor 202a, the PMOS transistor 202b typically must be about twice the size (i.e., occupy twice the area on a die or an IC) of the NMOS transistor 202a. Thus, the power transmission gate 200 can be said to have a size of about “three NMOS size units” (e.g., one NMOS transistor 202a that counts as one NMOS size unit, and one PMOS transistor 202b that counts as two NMOS size units). In many applications, it would be desirable to reduce the overall size (or footprint) of power transmission gates while satisfying the criteria described above.
The gate driver circuit 304 includes a fast start circuit 319 that is configured to receive a maximum possible input voltage Vin(max) 320 from an external voltage source and selectively apply the maximum possible input voltage Vin(max) 320 to the control terminal of the switch 316. The fast start circuit 319 can include one or more components and/or configurations for selectively applying the maximum possible input voltage Vin(max) 320 to the gate of the switch 316. Details of an exemplary fast start circuit 419 are described herein with respect to
The gate driver circuit 304 includes a shutdown circuit 326 that is coupled to the control terminal of the switch 316. The shutdown circuit 326 can include a switch that is responsive to a shutdown signal. The switch can have a drain coupled to the gate of the switch 316 and can be configured to discharge the voltage at the gate of the switch 316 when the switch 316 is disabled. Details of exemplary shutdown circuits 426, 526 are described herein with respect to
The power transmission gate 300 includes a body control circuit 321 that is configured to control a body of the switch 316. When the switch 316 is enabled, the body can be tied to the input voltage Vin 301, and when the switch 316 is disabled, the body can be tied to a negative supply voltage (e.g., Vss, or ground). The body control circuit 321 can include a first power NMOS transistor 323 and a second power NMOS transistor 325. In some implementations, the first power NMOS transistor 323 is configured to drive the body to the input voltage Vin 301 when the switch 316 is enabled, and the second power NMOS transistor 325 is configured to drive the body to the negative supply voltage Vss when the switch 316 is disabled.
While a single power transmission gate 300 is shown, it should be understood that multiple power transmission gates may be provided such that each power transmission gate receives one of a plurality of input voltage or in some instances the same input voltage Vin, and provides a respective output voltage.
The power transmission gate 300 can be configured to concurrently satisfy one or more criteria, including, but not limited to satisfying one or more safe operating area conditions of the NMOS transistor 302 (e.g., max Vgs, Vds, Vdb, Vds, etc.) such as: being configured to respond relatively quickly (e.g., in the order of nanoseconds) to changes in the input voltages; being configured to provide electrical isolation between the various outputs; being configured to carry relatively large currents (e.g., in the order of amperes), etc.
The supply modulation system 400 includes a supply modulator 402 configured to provide, from a set of possible input voltage levels, an input voltage Vin to one or more power transmission gates 404a-404n. Taking power transmission gate 404a as representative of power transmission gates 404a-404n, power transmission gate 404a includes a charge pump 406 configured to receive the input voltage Vin from the supply modulator 402. The input voltage Vin is received at a first terminal (e.g., an input) of a diode 408 of the charge pump 406, and a second terminal (e.g., an output) of the diode 408 is coupled to a first terminal (a “top end”) of a flying capacitor Cfly 410 via a switch 412a. The switch 412a is configured to protect a breakdown of the diode D1408 from a source-to-gate voltage (Vgs). The input voltage Vin (e.g., from the supply modulator 402) is selectively applied through a switch 412b to a first terminal (or “bottom end”) of the flying capacitor Cfly 410. The switches 412a, 412b can generally belong to a switch network 412. A second terminal (or “top end”) of flying capacitor Cfly 410 is coupled to an input of a diode 414. Voltage signals passing through diode 414 may correspond to a drive (or control) voltage provided to a control terminal of a switch 416. In this example, switch 416 is provided as an NMOS transistor and the control terminal corresponds to a gate terminal of the NMOS transistor which receives a voltage VNgate.
The diodes 408, 414, flying capacitor Cfly 410, and the switches 412a, 412b operate in a manner such that the flying capacitor Cfly 410 is configured to charge the gate of the switch 416 to the drive voltage VNgate having a value greater than the input voltage Vin, which, in this example, is about two times the input voltage Vin. The switch 412b is configured to switch between the input voltage Vin and a reference potential (illustrated as ground in this example embodiment) such that the input voltage and the reference potential are alternately applied to the bottom end of the flying capacitor Cfly 410. The switch 412a is configured to switch between applying and disconnecting the output of the diode 408 from the top end of the flying capacitor Cfly 410.
The power transmission gate 404a includes a diode D3418 that receives at a first (or input) terminal thereof a voltage provided by an external voltage source 420. In embodiments, the external voltage source 420 may, for example, be an external rail of the system 400. The voltage provided by external voltage source 420 may have a value corresponding to about a maximum possible input voltage Vin(max) that the input voltage Vin can be. A second (or output) terminal of diode D3418 is selectively coupled to the control terminal (here the gate terminal) of the switch 416 via a switch 422. The diode D3418 is configured to ensure that the drive voltage VNgate applied to the gate of the switch 416 is always above Vin(max) when enabled. While a diode D3418 is shown, it should be understood that other components and/or configurations are also possible for selectively applying the external voltage source 420 to the gate of the switch 416. The external voltage source 420 and the other components for allowing it to be selectively applied are sometimes collectively referred to herein as belonging to a “fast start circuit.”
The switch 416 is configured to receive the input voltage from the supply modulator 402 at a source of the switch and pass the input voltage to a drain of the switch. A capacitance Cg 424 is coupled between the gate and the source of the switch 416 and configured to maintain a substantially constant voltage across the gate and the source. The capacitance Cg 424 can have a larger (e.g., significantly larger, in some implementations, 10-100 times larger) capacitance value than the flying capacitor Cfly 410. In some implementations, the ratio of the values between the capacitance Cg 424 and the flying capacitor Cfly 410 can be chosen to ensure that the capacitance Cg 424 can allow the gate of the switch 416 to track the source of the switch 416 as the input voltage Vin is modulated.
The capacitance Cg 424 represents one or more internal parameters of the switch 416. For example, the capacitance Cg 424 can represent several physical capacitances/capacitors within the switch 416, including but not limited to a gate-to-source capacitance Cgs and a gate-to-drain capacitance Cgd, In some implementations, the capacitance Cg 424 may be augmented by one or more physical capacitors/capacitances implemented in the power transmission gates 404a-n.
In a first startup case, the switch 416 turns from off to on with the input voltage Vin at its maximum voltage Vin(max). The drive voltage VNgate is quickly (or rapidly) charged to the maximum input voltage Vin(max) through the diode D3418. In some implementations, the drive voltage VNgate is charged at a rate of about 1 volt per nanosecond, although other rates (e.g., in some cases faster rates) are also possible. Over a relatively short period of time, flying capacitor Cfly 410 is charged such that drive voltage VNgate corresponds to about two times the input voltage Vin. In some implementations, the flying capacitor Cfly 410 is charged at a rate of about 200 kHz, although other rates are also possible, including programmable/configurable rates. The voltage across the gate and the source (i.e., the gate-source voltage Vgs) of NMOS transistor 416 is equal to the input voltage Vin, which is equal to the maximum input voltage Vin(max). At this point, the switch 416 is fully enhanced and can conduct. If the input voltage Vin suddenly drops, the drive voltage VNgate follows that same drop proportionally because it is coupled through the capacitance Cg 424. Due to this coupling, the voltage Vgs across the gate and the source of switch 416 is maintained at a substantially consistent value as the input voltage Vin changes. This can ensure that safe operating conditions of the switch 416 (e.g., max Vgs, Vds, Vdb, Vds, etc.) are not violated.
In a second startup case, with the input voltage Vin at zero, the charge pump 406 has no input voltage, so it is essentially doing nothing. In this situation, the external voltage source 420 via the diode D3418 is configured to charge the gate of the switch 416 to Vin(max), which enhances the switch 416. At this point, the voltage Vgs across the gate and the source of the switch 416 has a value of Vin(max) If the input voltage Vin suddenly increases, the capacitance Cg 424 keeps the drive voltage VNgate coupled to the input voltage Vin such that the voltage Vgs across the gate and the source of the switch 416 remains substantially constant at a value of about Vin(max).
In both use cases, the voltage Vgs across the gate and the source of the switch 416 is kept close to Vin(max) regardless of how the input voltage Vin changes. There is a phase when the gate of the switch 416 is initially charged, and then from there the coupling of the capacitance Cg 424 keeps the gate moving with the source.
In some implementations, the charge pump 406 is a Dickson charge pump. The charge pump 406 can be configured to operate at a variable clock speed. For example, during an initial turn-on of the switch 416, the clock frequency for the charge pump can be run at a relatively high rate. After a fixed period of time, the clock frequency can be reduced, in some cases significantly. In some implementations, the fixed period of time may be determined at least in part by the charging rate of the flying capacitor Cfly 410 into the capacitance Cg 424 coupled to the switch 416.
The power transmission gate 404a also includes a shutdown circuit 426. The shutdown circuit 426 includes a switch 428 (e.g., an NMOS transistor) that is responsive to a shutdown signal. The switch 428 has a drain coupled to the gate of the switch 416 and is configured to discharge the voltage at the gate of the switch 416 when the switch 416 is disabled. The shutdown circuit 426 may include additional components than those shown in
The supply modulation system 400 can include additional power transmission gates 404a-n, with each of the power transmission gates 404a-n being configured to receive the input voltage Vin from the supply modulator 402 and provide a respective output Vouta-n. Each of the outputs Vouta-n can be electrically isolated for each other.
While the charge pump 406 has been illustrated and described as having a Dickson topology, other topologies can also be used without departing from the scope of the inventive concepts described herein. In some implementations, a charge pump having a Pelliconi topology could be used.
The power transmission gate 500 includes a diode 518 that is configured to initially charge VNgate to Vin(max) and ensure that VNgate never drops below Vin(max). The diode 518 may be an example of the diode 418 of
The power transmission gate 500 includes a protection switch 506 and a discharge switch 508. Each of the protection switch 506 and the discharge switch 508 may be NMOS transistors. The protection switch 506 is configured to provide protection to the discharge switch 508 from the relatively high voltage seen at VNgate. The power transmission gate 500 also includes a level translator 510 that is configured to receive a shutdown signal and up convert a logic level signal to the Vin(max) domain. The power transmission gate 500 also includes a plurality of buffers and inverters that are generally configured to drive the gates and bodies of the various components of the power transmission gate 500.
The charge pump 606 is configured to provide charge from the input voltage Vin to the driver voltage VNgate. Level translation is performed by the charge pump 606 to convert low level signals (e.g., 1.8 volt signals) to the input voltage Vin level. The charge pump 606 includes an OR gate 601 that is configured to receive a clock signal 603 and a shutdown signal 605 as inputs and provide an output to a first level translator 607, and an AND gate 609 that is configured to receive the clock signal 603 and an enable signal 611 (e.g., which is the inverse of the shutdown signal 605) as inputs and provide an output to a second level translator 613. The first and second level translators 607, 613 are each configured to receive a shutdown signal, which may be the same as the shutdown signal 605 received by the OR gate 601.
The body control circuit 700 can be configured to avoid the body effect of the resistance of the switch increasing as the source and drain voltages increase above the body voltage. For example, the particular voltage that the body is at changes the threshold/degree at which the gate voltage will enable/enhance the switch. As such, for a given gate voltage, as the body voltage increases, the resistance of the switch increases. To avoid the body effect, the body control circuit 700 can include a first NMOS transistor 702 that is configured to drive the body to the input voltage Vin when the switch is enabled, and a second NMOS transistor 704 that is configured to drive the body to the negative supply voltage Vss (e.g., ground) when the switch is disabled. Such a configuration can prevent back conducting through the body diode (e.g., keeping the output at a relatively high resistance).
Although reference is sometimes made herein to particular structures, circuit elements and materials, it is appreciated that other structures, circuit elements and materials having similar functional and/or structural properties may be substituted where appropriate, and that a person having ordinary skill in the art would understand how to select such materials and incorporate them into embodiments of the concepts, techniques, and structures set forth herein without deviating from the scope of those teachings.
Various embodiments of the concepts, systems, devices, structures and techniques sought to be protected are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the concepts, systems, devices, structures and techniques described herein. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the described concepts, systems, devices, structures and techniques are not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship.
As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s). The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising, “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance, or illustration. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “one or more” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.”
References in the specification to “one embodiment, “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal, “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, where intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary elements.
Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.
The terms “approximately” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, and yet within ±2% of a target value in some embodiments. The terms “approximately” and “about” may include the target value. The term “substantially equal” may be used to refer to values that are within ±20% of one another in some embodiments, within ±10% of one another in some embodiments, within ±5% of one another in some embodiments, and yet within ±2% of one another in some embodiments.
The term “substantially” may be used to refer to values that are within ±20% of a comparative measure in some embodiments, within ±10% in some embodiments, within ±5% in some embodiments, and yet within ±2% in some embodiments. For example, a first direction that is “substantially” perpendicular to a second direction may refer to a first direction that is within ±20% of making a 90° angle with the second direction in some embodiments, within ±10% of making a 90° angle with the second direction in some embodiments, within ±5% of making a 90° angle with the second direction in some embodiments, and yet within ±2% of making a 90° angle with the second direction in some embodiments.
It is to be understood that the disclosed subject matter is not limited in its application to the details of construction and to the arrangements of the components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other structures, methods, and systems for carrying out the several purposes of the disclosed subject matter. Therefore, the claims should be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.
Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the details of implementation of the disclosed subject matter may be made without departing from the spirit and scope of the disclosed subject matter.
This application claims the benefits of U.S. Provisional Application No. 63/380,612, filed on Oct. 24, 2022. The entire contents of this application is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63380612 | Oct 2022 | US |
