Pre-Charge Systems and Methods for ADC Input Sampling

Information

  • Patent Application
  • 20080024351
  • Publication Number
    20080024351
  • Date Filed
    July 31, 2006
    18 years ago
  • Date Published
    January 31, 2008
    16 years ago
Abstract
The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are implemented using an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge. The system is so configured for a coarse sampling phase and a fine sampling phase the to ensure that the sampling capacitor settles quickly to provides an output.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from consideration of the following description and drawings in which:



FIG. 1 is a simplified schematic circuit diagram illustrating an example of an ADC driver system embodying the methods of the invention;



FIG. 2 is a timing diagram illustrating an example of the operation of preferred embodiments of the methods and systems of the invention; and



FIG. 3 is a simplified schematic circuit diagram illustrating an example of an alternative embodiment of an ADC driver system embodying the methods of the invention.





References in the description correspond to like references in the various drawings unless otherwise noted. Descriptive, polarity, and directional terms used in the written description such as top, bottom, upper, side, etc., refer to the drawings themselves as laid out on the paper and not to physical limitations of the invention unless specifically noted. The drawings are not to scale, and some features of embodiments shown and discussed are simplified or amplified for illustrating the principles, features, and advantages of the invention.


DESCRIPTION OF REPRESENTATIVE EMBODIMENTS

In general, the invention provides novel pre-charge methods and systems embodied in high performance analog to digital converter input drivers. An exemplary embodiment of the invention is portrayed in the schematic diagram of FIG. 1. An ADC driver system 10 is shown with an op amp A1 for sampling the inputs, 12, 14. For using the system 10 with a high performance ADC, an amplifier A1 that is sufficiently fast and accurate for the application is selected. It may enhance appreciation of the principles of the invention to consider the underlying, but perhaps easily overlooked fact that speed and accuracy are only required of the op amp A1 during the intervals when the ADC system is actually sampling the input. It follows that during the other phase of the operative clock cycle, the amplifier A1 may be used as described. Examining FIG. 1, it may be seen that the system 10 is configured so that during the non-sampling phase of the clock cycle, the amplifier A1 may be operated as a slow amplifier charging a large pre-charge capacitor Cp. Preferably, for effective pre-charging, the pre-charge capacitor Cp may be on the order of about ten times the capacitance of the sampling capacitor Cs, e.g.; Cp≈k*Cs, for k=10. In some applications, for example where saving area is at a premium, a pre-charge capacitor of about the same value as Cs may be used. Of course, any pre-charge capacitor value between about Cs and 10*Cs may be used without departure from the invention, depending upon considerations such as available area and amount of pre-charging desired. The sampling capacitor Cs is used during the sampling phase of the clock cycle as further described.


Thus, in operation of the system 10, sampling takes place according to two phases as follows. During a coarse pre-charge phase, preferably of a duration of approximately one-tenth to one-sixth of the total sampling time, the amplifier A1 is operated as slow amplifier, the charge to the sampling capacitor Cs is provided by the larger pre-charge capacitor Cp at the output by charge sharing. Preferably, with Cp≈10*Cs, the output reaches a value approaching to within about 85-95% of its final value during this phase. With a smaller Cp, a lesser pre-charge level may be used, for example 50% for Cp≈Cs. Subsequently, during a fine sampling phase, the high-speed capabilities of the amplifier A1 are used to sample the charge on the sampling capacitor Cs, and the pre-charge capacitor Cp is disconnected from the output. The amplifier A1 then operates such that output quickly settles to the desired accuracy for use by the ADC system. Of course, additional feedback networks may be used as represented by resistors Rf and capacitors Cf. Also, it should be understood by those conversant in the arts that circuits shown herein are representative of preferred embodiments and that equivalent circuits may be used without departure from the principles of the invention.



FIG. 2 is a timing diagram further illustrating an example of the operation of preferred embodiments of the methods and systems of the invention. The pre-charge phase, during which the pre-charge capacitor Cp is charged, is indicated by trace P. The sampling phase, during which the sampling capacitor Cs is sampled, is shown by trace S. It may be seen that the time corresponding to the coarse sampling phase, during which the pre-charge capacitor and sampling capacitor are coupled for charge sharing, is indicated by t1. The fine sampling phase is indicated by t2.


In an example of an alternative embodiment of a system of the invention, as shown in FIG. 3, in order to reduce the area penalty which may be encountered by including large pre-charge capacitors Cp as shown in FIG. 1, a pre-charge capacitor Cpd may be placed in a differential configuration 20. This configuration 20 permits the reduction of the area used for the pre-charge capacitor(s) by a factor of two, for example, with k=10, Cpd≈k/2*Cs. This alternative embodiment of the invention occupies less chip area while the functioning of the system remains essentially unchanged from that described herein with reference to FIG. 2. That is, the differential pre-charge capacitor Cpd is charged during the pre-charge phase, and the sampling capacitor Cs is substantially charged by charge sharing with the pre-charge capacitor Cpd. The pre-charge capacitor Cpd is decoupled from the output, and the sampling capacitor Cs rapidly settles for an accurate sample.


Based on the disclosed examples, those skilled in the arts should appreciate that there are numerous possibilities for systems and methods using the principles of the invention. The principles of the invention may be implemented using various types of operational amplifiers in input stages for circuits, such as many types of ADC, either on-chip or on-board. The methods and systems of the invention provide one or more advantages which may include: improved SNR; improved SFDR; reduced power consumption; integration of ADCs and input drivers using CMOS manufacturing processes. While the invention has been described with reference to certain illustrative embodiments, those described herein are not intended to be construed in a limiting sense. For example, variations or combinations of steps in the embodiments shown and described may be used in particular cases without departure from the invention. For example, the principles of the invention may be applied in systems including but not limited to differential input to single-ended output, single-ended input to single-ended output, single-ended input to differential output, differential input to differential output. Modifications and combinations of the illustrative embodiments as well as other advantages and embodiments of the invention will be apparent to persons skilled in the arts upon reference to the drawings, description, and claims.

Claims
  • 1. A system for sampling a switched capacitive load comprising: an operational amplifier operably coupled to an input;a pre-charge capacitor operably coupled to an output of the operational amplifier for storing an input charge;a sampling capacitor operably coupled to the output of the operational amplifier and in parallel with the pre-charge capacitor for receiving and holding an input charge; andswitching circuitry connected to the pre-charge and sampling capacitors, configured and adapted for switching between a coarse sampling phase for at least partially charging the pre-charge capacitor and sampling capacitor, and a fine sampling phase for decoupling the pre-charge capacitor and outputting the charge from the sampling capacitor.
  • 2. (canceled)
  • 3. A system for sampling a switched capacitive load comprising: an operational amplifier operably coupled to receive a differential input signal at respective inverting and non-inverting inputs;a pre-charge capacitor operably coupled between inverting and non-inverting outputs of the operational amplifier for storing a differential input charge from the inverting and non-inverting outputs;a first sampling capacitor operably coupled to the inverting output of the operational amplifier for receiving and holding an input charge from the inverting output;a second sampling capacitor operably coupled to the non-inverting output of the operational amplifier for receiving and holding an input charge from the non-inverting output;switching circuitry connected to the pre-charge and sampling capacitors, configured and adapted for switching between a coarse sampling phase for at least partially charging the pre-charge capacitor and sampling capacitors, and a fine sampling phase for decoupling the pre-charge capacitor and outputting the charge from the sampling capacitors.
  • 4. A system according to claim 1 wherein the capacitance of the pre-charge capacitor is approximately ten times the capacitance of the sampling capacitor.
  • 5. A system according to claim 1 wherein the system is implemented using CMOS manufacturing processes.
  • 6. A system according to claim 1 further comprising an integrated system residing in a single chip.
  • 7. A system for driving a switched capacitive input load for an analog to digital converter, comprising: an operational amplifier operably coupled to a sampling network, the sampling network including switching circuitry connected and configured for sampling an input and for holding the sampled input for the analog to digital converter; the sampling network further comprising,a pre-charging capacitor and a sampling capacitor coupled to an output of the operational amplifier and arranged in a parallel configurations the switching circuitry being configured and adapted so that the pre-charging capacitor at least partially charges the sampling capacitor.
  • 8. A system according to claim 7 wherein the pre-charge capacitor is coupled to the operational amplifier in a differential configuration.
  • 9. A system according to claim 7 wherein the capacitance of the pre-charge capacitor is about ten times the capacitance of the sampling capacitor.
  • 10. A system according to claim 7 further comprising a feedback network operably coupled to the operational amplifier.
  • 11. A system according to claim 7 wherein the system is implemented using CMOS manufacturing processes.
  • 12. A system according to claim 7 further comprising an integrated system residing in a single chip.
  • 13. A method for regulating the input to an analog to digital converter system comprising the steps of: during a non-sampling phase of a system clock cycle, using an operational amplifier in a slow pre-charging mode for charging a large pre-charge capacitor;during a course sampling phase of the clock cycle, using the pre-charge capacitor to charge a sampling capacitor and thereafter decoupling the pre-charge capacitor from the sampling capacitor;during a fine sampling phase of the clock cycle, using the operational amplifier in a fast sampling mode to sample the charge on the sampling capacitor; andinputting the sample to the analog to digital converter system.
  • 14. A method according to claim 13 wherein the capacitance of the pre-charge capacitor Cp is about ten times the capacitance of the sampling capacitor.
  • 15. A method according to claim 13 wherein the duration of the pre-charge phase is within a range of approximately one-tenth to one-fifth of the total sampling time.
  • 16. A method according to claim 13 wherein during the pre-charge phase, the sampling capacitor Cs is charged to a range of within about 85-95% of its final value.
  • 17. A method according to claim 13 wherein the capacitance of the pre-charge capacitor Cp is within a range of within one to about ten times the capacitance of the sampling capacitor.
  • 18. A method according to claim 13 wherein the duration of the pre-charge phase is approximately one-seventh of the total sampling time.
  • 19. A method according to claim 13 wherein during the pre-charge phase, the sampling capacitor Cs is charged to a range of within about 50-85% of its final value.