Patent Application
20070165698
Typical DC free line encoding schemes, such as 8b/10b, 5b/6b, and 3b/4b, are used to guarantee that a given data signal has a certain number of transitions per baud rate (line signaling rate). This is important for many signaling systems, such as fiber optic and media using transformers, which need a certain number of transitions per baud rate for optimal performance. A high number of transitions helps to prevent transformer saturation and assists in clock acquisition. In addition, for data communication systems employing a clock encoded into data stream, the receiver relies on transitions embedded into the data stream to acquire the data-sampling clock. The number of transitions per baud rate drives a data recovery algorithm at the receiving end of the signaling system. The data recovery algorithm is, therefore, highly dependent on the number of transitions. However, this dependency causes possible slips in the data recovery algorithm.
Typical DC free line encoding schemes output a signal whose power spectrum is dependent on the spectral shape of the input data signal. As the input data sequence could contain extended sequences of zeros or ones, this opens a potential for energy concentrated in an area or frequency that the data recovery algorithm may not be looking at for clock acquisition. For example, typical data recovery algorithms operate in a limited bandwidth since the requirements for creating a data recovery algorithm that can operate over the whole bandwidth would stress the data recovery algorithm. However, by operating over a limited bandwidth, there is a chance that a power spectrum output, which is dependent on the spectral shape of the input signal, will have transition frequencies at the edge or outside of the data recovery algorithm processing bandwidth. If this occurs, the data recovery algorithm will not see the transition and slips in the data recovery algorithm can occur, inserting error into the data signal.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an encoding system which removes the dependency of an encoded output power spectrum on the spectral shape of the input data signal.
The above-mentioned problems and other problems are resolved by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a pre-whitened DC free line coding system is provided. The pre-whitened DC free line coding system comprises a scrambler adapted to whiten an input signal and an encoder adapted to convert the whitened input signal to a DC balanced signal.
In another embodiment, a method of removing dependency of an encoded output spectrum on the spectral shape of the input data sequence is provided. The method comprises scrambling a data signal such that the power spectrum is substantially evenly spread over a known bandwidth; and encoding the scrambled data signal to output a DC balanced signal.
In another embodiment, a data scrambler is provided. The data scrambler comprises a shift register; and at least one exclusive-OR operator (XOR), an input of the at least one XOR being coupled to one or more bits of the shift register, the register size and selection of the one or more bits coupled to the at least one XOR being based on the coding scheme of an encoder coupled to the data scrambler.
In another embodiment, a pre-whitened DC free line coding system is provided. The pre-whitened DC free line coding system comprises means for whitening a data signal; and means for encoding the whitened data signal coupled to the means for whitening the data signal, wherein the means for encoding the whitened data signal encodes the whitened data signal such that the whitened data signal is DC balanced.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific illustrative embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the scope of the present invention. It should also be understood that the exemplary methods illustrated may include additional or fewer steps or may be performed in the context of a larger processing scheme. Furthermore, the methods presented in the drawing figures or the specification are not to be construed as limiting the order in which the individual steps may be performed. The following detailed description is, therefore, not to be taken in a limiting sense.
Embodiments of the present invention remove the dependency of an encoding scheme output signal on the spectral shape of an input signal. Hence, embodiments of the present invention enable data recovery algorithms to be designed to operate over a limited bandwidth without risking missing needed transitions. Additionally, data recovery algorithms are not stressed by the requirements of designing the data recovery algorithms to operate over the whole frequency bandwidth.
At 106, the encoded signal is decoded by a data recovery algorithm to extract the scrambled signal. If the data signal were not scrambled, the data recovery algorithm would either risk missing necessary transitions or be stressed by the requirements of having to operate over the whole bandwidth. However, relatively little stress is placed on the recovery algorithm, in embodiments of the present invention, because the scrambled signal encoded at 104 is spread substantially evenly over a known bandwidth. Therefore, the encoded output power spectrum is substantially always spread over the same frequency bandwidth. Hence, embodiments of the present invention enable a data recovery algorithm to be designed to operate over a limited bandwidth without running the risk of missing necessary transitions due to transitions being at frequencies at the edge or outside of the processing bandwidth. At 108, the scrambled data signal is descrambled to extract the original data signal. In some embodiments, the scrambling and descrambling algorithms are synchronized by sending a synchronization bit using techniques known to one of skill in the art. In other embodiments, the scrambling and descrambling algorithms are self-synchronized based on the algorithm chosen as described in more detail below. In other embodiments, other means known to one of skill in the art are used for synchronizing the scrambling and descrambling algorithms.
Scrambler 202 is coupled to encoder 204. Encoder 204 receives the whitened data signal and converts the whitened data signal to a DC balanced signal. In some embodiments, the encoding scheme is used one of 8b/10b, 5b/6b, and 3b/4b. In other embodiments, other DC free line encoding schemes are used. Additionally, in some embodiments, scrambler 202 and encoder 204 are incorporated in the same physical component. Decoder 208 is coupled to encoder 204 across the transmission line. Decoder 208 receives the DC balanced signal and extracts the whitened signal. As described above, the data recovery algorithm of decoder 208 is relatively less stressed since the signal encoded by encoder 204 is a whitened signal. This enables the data recovery algorithm of decoder 208 to operate over a limited bandwidth without the risk of missing necessary transitions outside that limited bandwidth.
Descrambler 208 is coupled to decoder 206. Descrambler 208 is adapted to extract the original input signal from the whitened data signal. Descrambler 208 uses the same algorithm and characteristic polynomial as scrambler 202. In some embodiments, scrambler 202 and descrambler 208 are synchronized using N frame alignment bits. The frame alignment bits are not scrambled so that a receiving terminal can extract the frame boundary. In such embodiments, shift registers are reset to a specified state of shift register at the start of each frame in both scrambler 202 and descrambler 208. In other embodiments, scrambler 202 and descrambler 208 are self-synchronized. For example, in some embodiments, an input signal is scrambled as it passes through an “excited” shift register gate. The shift register gate is excited by an external input. The scrambled signal is then automatically de-scrambled as it passes through a reversed replica of the scrambler shift register gates. By self-synchronizing the scrambler and descrambler, no framing or processing is needed to synchronize the descrambler. In other embodiments, other means are used to synchronize scrambler 202 and descrambler 208.
In operation, shift register 302 starts with a seed value which is the initial value of shift register 302. Taps 304 output the value of bits 4 and 7 to XOR 306-1. Based on the values of bits 4 and 7, XOR 306-1 outputs a 1 or a 0 to an input of shift register 302. This input value will shift through the bits of shift register 302 changing the value of bits 4 and 7. This cycle continues with XOR 306-1 outputting a 1 or 0 to an input of shift register 302. This process generates a pseudo-random signal sequence which eventually repeats. The pseudo-random signal is characterized by the characteristic polynomial of scrambler 300. The number of taps 304, selection of bits for taps 304, and the size of shift register 302 determine the characteristic polynomial of scrambler 300. Therefore, the length of the pseudo-random signal sequence is affected by varying the number of bits, selection of taps, and number of taps.
In
XOR 306-2, in
The original data signal is extracted from the whitened signal by a descrambler with a similar shift-register/XOR configuration as scrambler 300. The descrambler also uses the same characteristic polynomial to descramble the whitened signal. In some embodiments, the descrambler and scrambler 300 are self-synchronized based on the seed value and characteristic polynomial chosen. In other embodiments, other means are used for synchronizing the descrambler and scrambler, such as by sending a synchronization bit.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
