PRECISE DELAY ALIGNMENT BETWEEN AMPLITUDE AND PHASE/FREQUENCY MODULATION PATHS IN A DIGITAL POLAR TRANSMITTER

Abstract

A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

FIG. 1 is a block diagram illustrating a prior art complex polar modulator with direct phase and amplitude modulation;

FIG. 2 is a block diagram illustrating a single chip polar transceiver radio incorporating an all-digital local oscillator based transmitter and receiver;

FIG. 3 is a block diagram illustrating a single chip polar transmitter based on a DCO and digitally controlled power amplifier (DPA) circuits;

FIG. 4 is a diagram illustrating spectral replicas of a modulating signal and associated filtering through a zero-order hold;

FIG. 5 is a block diagram illustrating the amplitude and phase modulation paths of the polar transmitter;

FIG. 6 is a graph illustrating the effect of misalignment between amplitude and phase on several points of the EDGE spectrum;

FIG. 7 is a graph illustrating the effect of misalignment between amplitude and phase on the EDGE spectrum for several different time mismatch delays;

FIG. 8 is a graph illustrating the degradation in EVM for WCDMA as a function of time mismatch between amplitude and phase modulation paths;

FIG. 9 is a graph illustrating the degradation in ACLR for WCDMA as a function of time mismatch between amplitude and phase modulation paths;

FIG. 10 is a graph illustrating the degradation in ACLR for WCDMA as a function of time mismatch between amplitude integer and fractional bits;

FIG. 11 is a graph illustrating the degradation in EVM for WCDMA as a function of time mismatch between amplitude integer and fractional bits;

FIG. 12 is a graph illustrating the degradation in EVM for WCDMA as a function of time mismatch between phase integer and fractional bits;

FIG. 13 is a graph illustrating the degradation in ACLR for WCDMA as a function of time mismatch between phase integer and fractional bits;

FIG. 14 is a graph illustrating TX spectral noise contribution degradation in the corresponding RX band for WCDMA as a function of time mismatch between phase integer and fractional bits;

FIG. 15 is a block diagram illustrating a digital delay adjustment block in accordance with the present invention for a signal propagating from a slow clock domain to a fast clock domain;

FIG. 16 is a block diagram illustrating a digital delay adjustment block in accordance with the present invention for a signal propagating from a fast clock domain to a slow clock domain;

FIG. 17 is a block diagram illustrating a first embodiment of a WCDMA transmitter having precise delay alignment between amplitude and frequency modulation paths;

FIG. 18 is a block diagram illustrating a tapped delay line in accordance with the present invention;

FIG. 19 is a block diagram illustrating a second embodiment of a WCDMA transmitter having precise delay alignment between frequency and amplitude modulation;

FIG. 20 is a block diagram illustrating a first generation ADPLL based DRP transmitter;

FIG. 21 is a block diagram illustrating the phase modulation path in a first generation ADPLL based DRP transmitter;

FIG. 22 is a block diagram illustrating the phase modulation path in a second generation ADPLL based DRP transmitter;

FIG. 23 is a block diagram illustrating the phase modulation path in a third generation ADPLL based DRP transmitter;

FIG. 24 is a block diagram illustrating an ADPLL with direct point injection and reference point injection rates of different clock domains;

FIG. 25A is a graph illustrating the use of multi-rate correlation determined using analytic clock alignment for the alignment of direct and reference point injections; and

FIG. 25B is a graph illustrating the use of multi-rate correlation determined using correlative measures to tune multiple clock domain delays for the alignment of direct and reference point injections.

Claims

1. A method of time alignment of a signal split into a plurality of independent paths, said method comprising the steps of: determining processing delays within one or more modules adapted to process said independent signal paths;generating a plurality of clock domains;using programmable delay elements between said plurality of clock domains to delay one or more clock domains; anddistributing said plurality of clock domains and the output of said programmable delay elements so as to compensate for said processing delays.

2. The method according to claim 1, wherein said programmable delay elements comprise a plurality of digitally controlled buffer delays.

3. A method of time alignment of a signal split into a plurality of independent paths, said method comprising the steps of: determining processing delays within one or more modules adapted to process said independent signal paths;generating a plurality of clock domains;using programmable delay elements between said plurality of clock domains to delay one or more clock domains;distributing said plurality of clock domains and the output of said programmable delay elements so as to compensate for said processing delays; andcalibrating the time alignment between said independent paths.

4. The method according to claim 3, wherein said step of calibrating comprises the steps of: interpolating data from each said independent signal path to be matched;correlating interpolated data to generate a delay associated with each independent signal path; andmatching each delay to available time resolution among said plurality of clock domains.

5. The method according to claim 3, wherein said programmable delay elements comprise a plurality of digitally controlled buffer delays.

6. A method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter, said method comprising the steps of: dividing a local oscillator clock output into a plurality of clock domains;delaying one or more of said clock domains in time by an amount adapted to compensate for analog propagation and settling times in said amplitude and phase/frequency modulation paths; andapplying said plurality of clock domains and said one or more delayed clock domains to circuit modules within said amplitude and phase/frequency modulation paths so as to provide time alignment between said amplitude and phase/frequency modulation paths.

7. The method according to claim 6, further comprising the step of calibrating time alignment between said amplitude and phase/frequency modulation paths.

8. The method according to claim 7, wherein said step of calibrating comprises the steps of: interpolating data from each said independent signal path to be matched;correlating interpolated data to generate a delay associated with each independent signal path; andmatching each delay to available time resolution among said plurality of clock domains.

9. The method according to claim 6, wherein said step of delaying comprises the step of using programmable delay elements comprising a plurality of digitally controlled buffer delays.

10. The method according to claim 6, further comprising the step of delaying a quadrature switch signal by an amount adapted to compensate for time alignment mismatches within said transmitter.

11. An apparatus for providing delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter, comprising: a clock module for dividing a local oscillator clock output into a plurality of clock domains;a tapped delay line operative to delay one or more of said clock domains by a programmable amount adapted to compensate for analog propagation and settling times in said amplitude and phase/frequency modulation paths; andmeans for applying said plurality of clock domains and said one or more delayed clock domains to circuit modules within said amplitude and phase/frequency modulation paths so as to provide time alignment between said amplitude and phase/frequency modulation paths.

12. The apparatus according to claim 11, further comprising a delay adjustment module operative to delay a quadrature switch signal by an amount adapted to compensate for time alignment mismatches within said transmitter.

13. The apparatus according to claim 12, wherein said delay adjustment module comprises: a first plurality of flip flops adapted to receive an input signal clocked by a first clock domain;an interpolator operative to interpolate the output of said first plurality of flip flops by a predetermined ratio; anda second plurality of flip flops adapted to receive the output of said interpolator and clocked by a second clock domain.

14. The apparatus according to claim 13, wherein said ratio comprises the ratio of said second clock domain to a third clock domain.

15. The apparatus according to claim 11, wherein final digital stages of both said amplitude and phase/frequency modulation paths share a common clock domain.

16. An apparatus for providing delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter, comprising: a programmable tapped delay line operative to delay a local oscillator clock in accordance with a delay control signal;a clock module for dividing either the delayed or non delayed local oscillator clock output of said programmable tapped delay line into a plurality of clock domains; andmeans for applying said plurality of clock domains to circuit modules within said amplitude and phase/frequency modulation paths so as to provide time alignment between said amplitude and phase/frequency modulation paths.

17. An apparatus for providing delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter, comprising: a clock divider module operative to generate a plurality of clock domains derived from the clock output of a digital controlled oscillator (DCO);means for assigning said plurality of clock domains to signal processing blocks within said amplitude and phase/frequency modulation paths;one or more digital delay adjustment modules operative to convert data within said amplitude and phase/frequency modulation paths from one clock domain to another; anda tapped delay operative comprising a plurality of buffer delays operative to adjust the phase relationship between high speed clock domains within said amplitude and phase/frequency modulation paths.

18. The apparatus according to claim 17, wherein each of said one or more digital delay adjustment module blocks comprises sample rate conversion means capable of being tuned to achieve desired delay alignment between said amplitude and phase/frequency modulation paths by accounting for the digital group delay of each said signal processing blocks within said amplitude and phase/frequency modulation paths.

19. The apparatus according to claim 17, wherein said tapped delay line is located between said DCO and a digital power amplifier (DPA).

20. The apparatus according to claim 17, wherein said tapped delay line is coupled to one or more clock domains output of said clock divider module.

21. The apparatus according to claim 17, wherein said tapped delay line is configured to compensate for analog propagation delays in one or more signal processing blocks within said amplitude and phase/frequency modulation paths.

22. The apparatus according to claim 17, wherein said digital delay adjustment module comprises: a first plurality of delay elements clocked at a first clock domain;a second plurality of delay elements clocked at a second clock domain; anda sample rate converter operative to convert between said first clock domain and said second clock domain.

23. The apparatus according to claim 22, wherein said sample rate converter is operative to perform interpolation when said first clock domain is slower than said second clock domain.

24. The apparatus according to claim 22, wherein said sample rate converter is operative to perform decimation when said first clock domain is faster than said second clock domain.

25. A polar transmitter comprising: an amplitude modulation path;a phase/frequency modulation path;said phase/frequency modulation path comprising a frequency synthesizer for performing a frequency modulation; said frequency synthesizer comprising a digitally controlled oscillator (DCO);delay alignment means said for providing delay alignment between said amplitude modulation path and said phase/frequency modulation path, said delay alignment means comprising: a clock module for dividing a DCO output signal into a plurality of clock domains;a tapped delay line operative to delay one or more of said clock domains by a programmable amount adapted to compensate for analog propagation and settling times in said amplitude and phase/frequency modulation paths; andmeans for applying said plurality of clock domains and said one or more delayed clock domains to circuit modules within said amplitude and phase/frequency modulation paths so as to provide time alignment between said amplitude and phase/frequency modulation paths.