Claims
- 1. An integrated circuit memory system comprising:a control block controlling operations of said integrated circuit memory system; a plurality of memory cells, each memory cell comprising: a source, drain, control gate and floating gate, said floating gate capable of storing electric charge, said memory cells programmable by hot carrier injection of electric charge to said floating gate corresponding to input signals to said integrated circuit memory system; and circuit means, responsive to said control block, for applying preselected voltages to said source, drain and control gate of selected memory cell in a set of timed relationships and for providing a constant current independently of said input signals, said current flowing between said source and drain of said selected memory cell to determine an amount of charge stored in said floating gate of said selected memory cell to read signals corresponding to said stored amount of charge.
- 2. The new integrated circuit memory system of claim 1 wherein said set of timed relationships are dependent upon characteristics of said memory cells.
- 3. The integrated circuit memory system of claim 1 wherein said set of timed relationships are controlled by said control block.
- 4. The integrated circuit memory system of claim 3 wherein said set of timed relationships are dependent upon characteristics of said memory cells.
- 5. In an integrated circuit memory system having a plurality of memory cells, each memory cell comprising a source, drain, control gate and floating gate, said floating gate capable of storing electric charge, said memory cells programmable by hot carrier injection corresponding to input signals to said integrated circuit memory system, a method for reading said memory cells comprising:applying voltages to said source, drain and control gate of a selected memory cell in a set of timed relationships and providing a constant current independently of said input signals, said constant current flowing between said source and drain of said selected memory cell to determine an amount of electric charge stored on said floating gate of said selected memory cell to read signals corresponding to said amount of charge.
- 6. The reading method of claim 5 further comprising setting said set of timed relationships from characteristics of said memory cells.
- 7. The reading method of claim 5 further comprising setting said set of timed relationships by a control block in said integrated circuit memory system.
- 8. The reading method of claim 7 further comprising setting said set of timed relationships from characteristics of said memory cells.
Parent Case Info
This application is a divisional of and claims the benefit of U.S. patent application Ser. No. 09/523,828, filed Mar. 13, 2000, U.S. Pat. No. 6,285,598, which is a continuation of U.S. patent application Ser. No. 09/197,479, filed on Nov. 20, 1998, U.S. Pat. No. 6,038,174, which is a continuation of U.S. patent application Ser. No. 08/812,868, filed Mar. 6, 1997, U.S. Pat. No. 5,870,335, the disclosures of which are incorporated herein by reference.
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Continuations (2)
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Number |
Date |
Country |
Parent |
09/197479 |
Nov 1998 |
US |
Child |
09/523828 |
|
US |
Parent |
08/812868 |
Mar 1997 |
US |
Child |
09/197479 |
|
US |