Patent Application
20090138536
The present invention relates to a linear interpolation algorithm, particularly to a precision-sensing linear interpolation algorithm, which applies to a system needing linear interpolation operation.
With maturation of communication market, communication-related IC is also persistently advancing, and more and more manufacturers increase the ratio of using computer graphics in small-size display systems. Due to prosperity of mobile electronic products, increasing running time of batteries can benefit a portable display device very much. Therefore, how to efficiently use batteries with image quality maintained stable is a challenge. Because of the superiority of realtime performance of the scan-conversion computer graphic system, the triangle-based rendering/shading technology has been the mainstream of the graphic subsystem of a realtime system.
The conventional pixel shading algorithm and scan-conversion algorithm do not treat the problem of power efficiency in algorithm level intentionally. Therefore, much power is wasted on unnecessary calculation.
Refer to
As a hardware divider has a higher price, the conventional technology usually adopts an iterative division calculation, which shares a same adder/subtractor with accumulative calculations. Refer to
A personal computer often adopts a lower setup overhead graphic algorithm to promote graphic performance. However, the conventional graphic algorithm is hard to achieve power efficiency and graphic performance simultaneously.
Accordingly, the present invention proposes a precision-sensing linear interpolation algorithm, which can achieve image quality, graphic performance and power efficiency simultaneously. Further; the present invention has superior scalability and generic and can be applied to various systems for graphics or needing linear interpolation.
The primary objective of the present invention is to provide a precision-sensing linear interpolation algorithm to modify the setup stage of the algorithm, shorten setup time, promote graphic performance and reduce power consumption in the setup stage.
Another objective of the present invention is to provide a precision-sensing linear interpolation algorithm having superior scalability and generic, wherein a masking method is used to decrease unnecessary bits and reduce the dynamic power consumption of the bit hardware.
The precision-sensing linear interpolation algorithm of the present invention comprises: (a) performing slope computation setup to obtain a difference term, (b) performing precision detection and setting the iteration number of iterative division calculations, (c) performing iterative division calculations to obtain the slopes, (d) removing bits unnecessary for the required precision with a bit-masking method, and (e) completing the linear interpolations with incremental addition calculations.
In the present invention, the precision detection is to obtain the difference between the theoretical quotient and the practical quotient, and the difference is used as a greater allowed tolerance of the system to reduce the iteration number of division calculations. The masking method sets the bits from the bit behind the greater allowed tolerance to the lowest bit to be 0 via an “AND 0” way.
The present invention is distinct from the conventional technology in that a precision detection is performed before iterative division calculations. Next, the iteration number of iterative division calculations is determined according to the required precision. After iterative division calculations, the bits in the decimal places redundant for the required precision are set to be zero with a bit mask. According to the precision required by a rendering, shading, or scan-conversion process of a triangle or span, the present invention adjust the precision the calculation needs to achieve and reduce the iteration number of calculations. Thus, the time occupied by iteration is reduced, and graphic performance is promoted. Further, the present invention utilizes a mask to set the bits redundant for the required precision to be 0. Thereby, the number of the switching activities of the circuit is reduced, and the dynamic power consumption is decreased, and the power efficiency is promoted.
Below, the technical contents of the present invention are described in detail with the embodiments. However, it should be noted that the embodiments are only to exemplify the present invention but not to limit the scope of the present invention.
Refer to
The present invention is distinct from the conventional technology in that a precision detection is performed before iterative division calculations. Next, the iteration number of iterative division calculations is determined according to the required precision. After iterative division calculations, the bits in the decimal places unnecessary for the required precision are set to be zero with a bit mask. Via precision detection and bit masking, the present invention promotes algorithm efficiency and reduces dynamic power consumption.
Below is demonstrated the precision analysis of the present invention, which can achieve the same quality images as the conventional algorithm. For simplifying expressions, D denotes the dividend in slope computation, and S denotes the divisor, wherein {D, S} are integer; QF denotes the practical quotient of the division calculation using non-floating point number and limited bits; QR denotes the theoretic quotient of the correct quotient; E denotes the difference between the theoretic quotient and the practical quotient. The abovementioned variables meet Equations 1-5:
Q
R
=Q
F
+E (1)
2k≦D<2k+1 (2)
2m≦S<2m+1 (3)
D=Q
R
·S=Q
F
·S+ES (4)
E·S=D−Q
F
·S (5)
In the scan-conversion process, the difference between the theoretic quotient QR and the practical quotient QF will be accumulated to E·S. Suppose the accumulated difference should be smaller than 2−r (Equation 6) for different systems. Therefore, the quotient in practical calculation has to meet the inequality of Equation 7. Equation 8 means that the highest decimal place where error is allowed to appear in practical calculation is the (m+r+1)th place after the decimal point. Usually, r=1. Thus, (m+2) decimal places are needed. Therefore, the iteration number of division calculations is k+2, which is the sum of k−m for the integer part and m+2 for the decimal fraction part. For RGB color dimensions, a greater error term E is allowed, and the iteration number of division calculations can be smaller
E·S<2−r (6)
E<S
−1·2−r=2−m−r (7)
E=2−m−r−1=2−(m+r+1) (8)
After the approximate quotient is obtained, the bits from behind the (m+r+1)th bit to the lowest bit are set to be 0 via the “AND 0” way. Thus, 1 will not appears in lower bits when incremental addition calculation is used to obtain Pi shown in
Compared with the conventional algorithm, the present invention can reduce the time spent on the division calculations of the slopes of most spans. Refer to
Real systems are used to very the improved algorithm proposed by the present invention, and the results are shown in the table below. In comparison with the conventional algorithm, the present invention can upgrade power efficiency by from 42.6 to 76.5% in variation with the sizes of the triangles plotted by the improved algorithm,
Those described above are only the preferred embodiments to exemplify the present invention but not to limit the scope of the present invention. Any equivalent modification or variation according to the present invention is to be also included within the scope of the present invention.
