Patent Application
20050278664
The present invention relates generally to the computer modeling of Very Large-Scale Integration (VLSI) and, more particularly, to more accurately predicting power consumption with computer models.
In VLSI design, power consumption is a significant factor. Battery life, heat produced, packaging, and so forth can be adversely affected by power consumption. Hence, low power chips are desirable.
Estimation of power consumption begins with breaking a chip into smaller analytic components. The smaller analytic components are known as macros, which are essentially smaller block portions of a larger circuit. For example, a macro can be a latch, a raised cosine filter, or a variety of other components. Examining smaller components of a chip allow for convenience in modeling. There are also a variety of simulator software packages that can be used to construct circuits, for example Simulated Program for Integrated Circuits Emphasis (SPICE).
Typically, once the chip has been broken down into macros, an energy model for each macro can be developed based on the input pins. One conventional method is to use a logic simulator to obtain the average switching factors and the average power densities. Then based on the average switching factors and power densities, the power consumption for an entire chip can be extrapolated. Estimations based on these conventional methods may yield an overall maximum of power consumption; however, these conventional methods do not accurately model the fine grain clock gating that is required in a number of microprocessors today.
Full chip simulations, however, require a substantial amount of computer power and time. Making assumptions, though, to model the power consumption for an entire chip is inaccurate. Therefore, there is a need for a method and/or apparatus for modeling power consumption for a chip with varying circuit topologies that uses a reasonable amount of computer power and time that addresses at least some of the problems associated with conventional methods and apparatuses for modeling power consumption of a chip.
The present invention provides a method, an apparatus, and a computer program for predicting power consumption of circuits on a chip. In order to predicting power consumption under real world conditions, the chip should first be separated into a plurality of macros. Once the chip has been broken down into smaller units, power consumption is then predicted for each macro. The power consumption predictions are based on a plurality of switching factors for each macro of the plurality of macros. After a number of data points have been acquired which yield power consumptions at varying switching factors, power consumption for all switching factors for each macros can be extrapolated based on the plurality of switching factors for each macro to yield energy model data for each macro.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electro-magnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art.
It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor such as a computer or an electronic data processor in accordance with code such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise.
Referring to
The modeled macro 100 is utilized to generate energy model data. The switching factors of the plurality of data inputs 104 and the control inputs 106 of the macro 102 are varied to output data through the plurality of outputs 108. The macro 102 can be a variety of macro types, such as a latch macro. A switching factor is a percentage of the inputs that toggle after a given cycle. For example, a fifty percent switching factor is at a time where one-half of the input pins are toggled. Measurements of the power consumption at various switching factors are taken. Typically, power consumption measurements are taken at fifty percent, at one hundred percent, and at zero percent. However, more data points can be gathered by taking measurements at a variety of other switching factors. Once the power consumption measurements have been taken, then power at a given switching factor can be extrapolated from the power consumption measurements. These extrapolations of power consumption for a given switching factors are the energy model data. Also, the extrapolations can encompass a variety of linear and non-linear extrapolation techniques, such a least square fitting and splines.
The modeled macro 100, however, does not have to be completed either to determine the energy model data for power consumption. In fact, macros, such as the macro 102, can be modeled at various stages of design and development to determine relative amounts of power consumption. By allowing a designer to be able to model power consumption of a given macro at every stage of development, the time required to design a specific macro or chip is substantially reduced. Also, modeling the macro can assist a designer in the development because of the known power consumptions as the design progresses.
Referring to
In step 202, the energy model data is determined. A determination of the energy model data is typically made from the modeled macro 100 of
The net capacitance should then be calculated in step 204. Chip floor plans, with all of the respective macro placements, are utilized. Based on the layout and the capacitance of the individual macros, an overall net capacitance for the chip can be determined.
In step 206, the power consumption modeler is run. The power consumption modeler combines the data generated as a result of the net capacitance determination and the energy model data. The net power consumption can be determined for each cycle. Different workloads and logic implementations can be utilized when running the power consumption modeler to determine power consumption of a variety of situations without having to reformulate the net capacitance or the energy model data.
As a result of the methodology for determining power consumption, the design time decrease while maintaining a high degree of accuracy. Due to energy model data for macros being stored, design patterns can be varied to minimize power usage. Moreover, accurate power estimations for large custom microprocessors can be made with low processing time requirements.
Referring to
There are numerous benefits to utilizing the power consumption modeler. The amount of computing power and time required is minimized because each of the macros has an individual energy model. Moreover, the power consumption modeler has the ability to determine power consumption on a cycle-by-cycle basis and to predict power usage over time. Also, power consumption predictions can be made for macros in various stages of completeness.
It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying mechanisms on which these programming models can be built.
Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
