This patent document relates to video coding and decoding techniques, devices and systems.
In spite of the advances in video compression, digital video still accounts for the largest bandwidth use on the internet and other digital communication networks. As the number of connected user devices capable of receiving and displaying video increases, it is expected that the bandwidth demand for digital video usage will continue to grow.
The present document describes various embodiments and techniques for buffer management and block vector coding for intra block copy mode for decoding or encoding video or images.
In one example aspect, a method of video or image (visual data) processing is disclosed. The method includes determining a size of a buffer to store reference samples for prediction in an intra block copy mode; and performing a conversion between a current video block of visual media data and a bitstream representation of the current video block, using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture.
In another example aspect, another method of visual data processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reconstructed samples for prediction in an intra block copy mode, wherein the buffer is used for storing the reconstructed samples before a loop filtering step; and performing the conversion using the reconstructed samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture.
In yet another example aspect, another method of visual data processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reconstructed samples for prediction in an intra block copy mode, wherein the buffer is used for storing the reconstructed samples after a loop filtering step; and performing the conversion using the reconstructed samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in a same video region with the current video block without referring to a reference picture.
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reconstructed samples for prediction in an intra block copy mode, wherein the buffer is used for storing the reconstructed samples both before a loop filtering step and after the loop filtering step; and performing the conversion using the reconstructed samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture.
In another example aspect, another method of video processing is disclosed. The method includes using a buffer to store reference samples for prediction in an intra block copy mode, wherein a first bit-depth of the buffer is different than a second bit-depth used to represent visual media data in the bitstream representation; and performing a conversion between a current video block of the visual media data and a bitstream representation of the current video block, using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture.
In yet another example aspect, another method of video processing is disclosed. The method includes initializing a buffer to store reference samples for prediction in an intra block copy mode, wherein the buffer is initialized with a first value; and performing a conversion between a current video block of visual media data and a bitstream representation of the current video block using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture.
In yet another example aspect, another method of video processing is disclosed. The method includes initializing a buffer to store reference samples for prediction in an intra block copy mode, wherein, based on availability of one or more video blocks in visual media data, the buffer is initialized with pixel values of the one or more video blocks in the visual media data; and performing a conversion between a current video block that does not belong to the one or more video blocks of the visual media data and a bitstream representation of the current video block, using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture.
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reference samples for prediction in an intra block copy mode; performing the conversion using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture; and for a pixel spatially located at location (x0, y0) and having a block vector (BVx, BVy) included in the motion information, computing a corresponding reference in the buffer based on a reference location (P mod M, Q mod N) where “mod” is modulo operation and M and N are integers representing x and y dimensions of the buffer, wherein the reference location (P, Q) is determined using the block vector (BVx, BVy) and the location (x0, y0).
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reference samples for prediction in an intra block copy mode; performing the conversion using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture; and for a pixel spatially located at location (x0, y0) and having a block vector (BVx, BVy) included in the motion information, computing a corresponding reference in the buffer based on a reference location (P, Q), wherein the reference location (P, Q) is determined using the block vector (BVx, BVy) and the location (x0, y0).
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reference samples for prediction in an intra block copy mode, wherein pixel locations within the buffer are addressed using x and y numbers; and performing, based on the x and y numbers, the conversion using the reference samples stored in the buffer, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture.
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reference samples for prediction in an intra block copy mode, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture; for a pixel spatially located at location (x0, y0) of the current video block and having a block vector (BVx, BVy), computing a corresponding reference in the buffer at a reference location (P, Q), wherein the reference location (P, Q) is determined using the block vector (BVx, BVy) and the location (x0, y0); and upon determining that the reference location (P, Q) lies outside the buffer, re-computing the reference location using a sample in the buffer.
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reference samples for prediction in an intra block copy mode, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture; for a pixel spatially located at location (x0, y0) of the current video block relative to an upper-left position of a coding tree unit including the current video block and having a block vector (BVx, BVy), computing a corresponding reference in the buffer at a reference location (P, Q), wherein the reference location (P, Q) is determined using the block vector (BVx, BVy) and the location (x0, y0); and upon determining that the reference location (P, Q) lies outside the buffer, constraining at least a portion of the reference location to lie within a pre-defined range.
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block of visual media data and a bitstream representation of the current video block, a buffer that stores reference samples for prediction in an intra block copy mode, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture; for a pixel spatially located at location (x0, y0) of the current video block relative to an upper-left position of a coding tree unit including the current video block and having a block vector (BVx, BVy), computing a corresponding reference in the buffer at a reference location (P, Q), wherein the reference location (P, Q) is determined using the block vector (BVx, BVy) and the location (x0, y0); and upon determining that the block vector (BVx, BVy) lies outside the buffer, padding the block vector (BVx, BVy) according to a block vector of a sample value inside the buffer.
In yet another example aspect, another method of video processing is disclosed. The method includes resetting, during a conversion between a video and a bitstream representation of the video, a buffer that stores reference samples for prediction in an intra block copy mode at a video boundary; and performing the conversion using the reference samples stored in the buffer, wherein the conversion of a video block of the video is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the video block without referring to a reference picture.
In yet another example aspect, another method of video processing is disclosed. The method includes performing a conversion between a current video block and a bitstream representation of the current video block; and updating a buffer which is used to store reference samples for prediction in an intra-block copy mode, wherein the buffer is used for a conversion between a subsequent video block and a bitstream representation of the subsequent video block, wherein the conversion between the subsequent video block and a bitstream representation of the subsequent video block is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the subsequent video block without referring to a reference picture.
In yet another example aspect, another method of video processing is disclosed. The method includes determining, for a conversion between a current video block and a bitstream representation of the current video block, a buffer that is used to store reconstructed samples for prediction in an intra block copy mode, wherein the conversion is performed in the intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the current video block without referring to a reference picture; and applying a pre-processing operation to the reconstructed samples stored in the buffer, in response to determining that the reconstructed samples stored in the buffer are to be used for predicting sample values during the conversation.
In yet another example aspect, another method of video processing is disclosed. The method includes determining, selectively for a conversion between a current video block of a current virtual pipeline data unit (VPDU) of a video region and a bitstream representation of the current video block, whether to use K1 previously processed VPDUs from an even-numbered row of the video region and/or K2 previously processed VPDUs from an odd-numbered row of the video region; and performing the conversion, wherein the conversion excludes using remaining of the current VPDU, wherein the conversion is performed in an intra block copy mode which is based on motion information related to a reconstructed block located in same video region with the video block without referring to a reference picture.
In yet another example aspect, a video encoder or decoder apparatus comprising a processor configured to implement an above described method is disclosed.
In another example aspect, a computer readable program medium is disclosed. The medium stores code that embodies processor executable instructions for implementing one of the disclosed methods.
These, and other, aspects are described in greater details in the present document.
Section headings are used in the present document for ease of understanding and do not limit scope of the disclosed embodiments in each section only to that section. The present document describes various embodiments and techniques for buffer management and block vector coding for intra block copy mode for decoding or encoding video or images.
This patent document is related to video coding technologies. Specifically, it is related to intra block copy in video coding. It may be applied to the standard under development, e.g. Versatile Video Coding. It may be also applicable to future video coding standards or video codec.
Video coding standards have evolved primarily through the development of the well-known ITU-T and ISO/IEC standards. The ITU-T produced H.261 and H.263, ISO/IEC produced MPEG-1 and MPEG-4 Visual, and the two organizations jointly produced the H.262/MPEG-2 Video and H.264/MPEG-4 Advanced Video Coding (AVC) and H.265/HEVC standards. Since H.262, the video coding standards are based on the hybrid video coding structure wherein temporal prediction plus transform coding are utilized. To explore the future video coding technologies beyond HEVC, Joint Video Exploration Team (JVET) was founded by VCEG and MPEG jointly in 2015. Since then, many new methods have been adopted by JVET and put into the reference software named Joint Exploration Model (JEM). In April 2018, the Joint Video Expert Team (JVET) between VCEG (Q6/16) and ISO/IEC JTC1 SC29/WG11 (MPEG) was created to work on the VVC standard targeting at 50% bitrate reduction compared to HEVC.
2.1 Inter Prediction in HEVC/H.265
Each inter-predicted PU has motion parameters for one or two reference picture lists. Motion parameters include a motion vector and a reference picture index. Usage of one of the two reference picture lists may also be signalled using inter pred_idc. Motion vectors may be explicitly coded as deltas relative to predictors.
When a CU is coded with skip mode, one PU is associated with the CU, and there are no significant residual coefficients, no coded motion vector delta or reference picture index. A merge mode is specified whereby the motion parameters for the current PU are obtained from neighbouring PUs, including spatial and temporal candidates. The merge mode can be applied to any inter-predicted PU, not only for skip mode. The alternative to merge mode is the explicit transmission of motion parameters, where motion vector (to be more precise, motion vector differences (MVD) compared to a motion vector predictor), corresponding reference picture index for each reference picture list and reference picture list usage are signalled explicitly per each PU. Such a mode is named Advanced motion vector prediction (AMVP) in this disclosure.
When signalling indicates that one of the two reference picture lists is to be used, the PU is produced from one block of samples. This is referred to as ‘uni-prediction’. Uni-prediction is available both for P-slices and B-slices.
When signalling indicates that both of the reference picture lists are to be used, the PU is produced from two blocks of samples. This is referred to as ‘bi-prediction’. Bi-prediction is available for B-slices only.
The following text provides the details on the inter prediction modes specified in HEVC. The description will start with the merge mode.
2.2 Current Picture Referencing
Current Picture Referencing (CPR), or once named as Intra Block Copy (IBC) has been adopted in HEVC Screen Content Coding extensions (HEVC-SCC) and the current VVC test model. IBC extends the concept of motion compensation from inter-frame coding to intra-frame coding. As demonstrated in
Following a BV to find its reference block, the prediction can be generated by copying the reference block. The residual can be got by subtracting the reference pixels from the original signals. Then transform and quantization can be applied as in other coding modes.
However, when a reference block is outside of the picture, or overlaps with the current block, or outside of the reconstructed area, or outside of the valid area restricted by some constrains, part or all pixel values are not defined. Basically, there are two solutions to handle such a problem. One is to disallow such a situation, e.g. in bitstream conformance. The other is to apply padding for those undefined pixel values. The following sub-sessions describe the solutions in detail.
2.3 CPR in HEVC Screen Content Coding Extensions
In the screen content coding extensions of HEVC, when a block uses current picture as reference, it should guarantee that the whole reference block is within the available reconstructed area, as indicated in the following spec text:
The variables offsetX and offsetY are derived as follows:
offsetX=(ChromaArrayType==0)?0:(mcCLX[0]&0x7?2:0) (8-104)
offsetY=(ChromaArrayType==0)?0:(mcCLX[1]&0x7?2:0) (8-105)
It is a requirement of bitstream conformance that when the reference picture is the current picture, the luma motion vector mvLX shall obey the following constraints:
Thus, the case that the reference block overlaps with the current block or the reference block is outside of the picture will not happen. There is no need to pad the reference or prediction block.
2.4 Examples of CPR/IBC
In a VVC test model, the whole reference block should be with the current coding tree unit (CTU) and does not overlap with the current block. Thus, there is no need to pad the reference or prediction block.
When dual tree is enabled, the partition structure may be different from luma to chroma CTUs. Therefore, for the 4:2:0 colour format, one chroma block (e.g., CU) may correspond to one collocated luma region which have been split to multiple luma CUs.
The chroma block could only be coded with the CPR mode when the following conditions shall be true:
If any of the two condition is false, the chroma block shall not be coded with CPR mode.
It is noted that the definition of ‘valid BV’ has the following constraints:
In some examples, the reference area for CPR/IBC is restricted to the current CTU, which is up to 128×128. The reference area is dynamically changed to reuse memory to store reference samples for CPR/IBC so that a CPR/IBC block can have more reference candidate while the reference buffer for CPR/IBC can be kept or reduced from one CTU.
Suppose that the current luma CU's position relative to the upper-left corner of the picture is (x, y) and block vector is (BVx, BVy). In the current design, if the BV is valid can be told by that the luma position ((x+BVx)>>6<<6+(1<<7), (y+BVy)>>6<<6) has not been reconstructed and ((x+BVx)>>6<<6+(1<<7), (y+BVy)>>6<<6) is not equal to (x>>6<<6, y>>6<<6).
2.6 In-Loop Reshaping (ILR)
The basic idea of in-loop reshaping (ILR) is to convert the original (in the first domain) signal (prediction/reconstruction signal) to a second domain (reshaped domain).
The in-loop luma reshaper is implemented as a pair of look-up tables (LUTs), but only one of the two LUTs need to be signaled as the other one can be computed from the signaled LUT. Each LUT is a one-dimensional, 10-bit, 1024-entry mapping table (1D-LUT). One LUT is a forward LUT, FwdLUT, that maps input luma code values Yi to altered values Yr: Yr=FwdLUT [K]. The other LUT is an inverse LUT, InvLUT, that maps altered code values Yr to Yr: Ŷi=InvLUT [Yr]. (YL represents the reconstruction values of Yr to Ŷi:
2.6.1 PWL Model
Conceptually, piece-wise linear (PWL) is implemented in the following way:
Let x1, x2 be two input pivot points, and y1, y2 be their corresponding output pivot points for one piece. The output value y for any input value x between x1 and x2 can be interpolated by the following equation:
y=((y2−y1)/(x2−x1))*(x−x1)+y1
In fixed point implementation, the equation can be rewritten as:
y=((m*x+2FP_PREC-1)>>FP_PREC)+c
where m is scalar, c is an offset, and FP_PREC is a constant value to specify the precision.
In some examples, the PWL model is used to precompute the 1024-entry FwdLUT and InvLUT mapping tables; but the PWL model also allows implementations to calculate identical mapping values on-the-fly without pre-computing the LUTs.
2.6.2.1 Luma Reshaping
A method of the in-loop luma reshaping provides a lower complexity pipeline that also eliminates decoding latency for block-wise intra prediction in inter slice reconstruction. Intra prediction is performed in reshaped domain for both inter and intra slices.
Intra prediction is always performed in reshaped domain regardless of slice type. With such arrangement, intra prediction can start immediately after previous TU reconstruction is done. Such arrangement can also provide a unified process for intra mode instead of being slice dependent.
16-piece piece-wise linear (PWL) models are tested for luma and chroma residue scaling instead of the 32-piece PWL models.
Inter slice reconstruction with in-loop luma reshaper (light-green shaded blocks indicate signal in reshaped domain: luma residue; intra luma predicted; and intra luma reconstructed)
2.6.2.2 Luma-Dependent Chroma Residue Scaling
Luma-dependent chroma residue scaling is a multiplicative process implemented with fixed-point integer operation. Chroma residue scaling compensates for luma signal interaction with the chroma signal. Chroma residue scaling is applied at the TU level. More specifically, the following applies:
The average is used to identify an index in a PWL model. The index identifies a scaling factor cScalelnv. The chroma residual is multiplied by that number.
It is noted that the chroma scaling factor is calculated from forward-mapped predicted luma values rather than reconstructed luma values
2.6.2.3 Signalling of ILR Side Information
The parameters are (currently) sent in the tile group header (similar to ALF). These reportedly take 40-100 bits.
In some examples, the added syntax is highlighted in italics.
In 7.3.2.1 Sequence parameter set RBSP syntax
In 7.3.3.1 General tile group header syntax
qtbtt_dual_tree_intra_flag && tile_group_type = = I ) ) )
Add a new syntax table tile group reshaper model:
tile_group_reshaper_model ( ) {
reshaper_model_max_bin_idx; i+ + ) {
In General sequence parameter set RBSP semantics, add the following semantics:
In tile group header syntax, add the following semantics
Add Tile_Group_Reshaper_Model( ) Syntax
When reshape_model_bin_delta_sign_CW_flag[i] is not present, it is inferred to be equal to 0.
The variable RspDeltaCW[i]=(12*reshape_model_bin_delta_sign_CW [i])*reshape_model_bin_delta_abs_CW [i];
The variable RspCW[i] is derived as following steps:
The variable OrgCW is set equal to (1<<BitDepthy)/(MaxBinIdx+1).
The value of RspCW [i] shall be in the range of 32 to 2*OrgCW−1 if the value of BitDepthy is equal to 10.
The variables InputPivot[i] with i in the range of 0 to MaxBinIdx+1, inclusive are derived as follows
InputPivot[i]=i*OrgCW
The variable ReshapePivot[i] with i in the range of 0 to MaxBinIdx+1, inclusive, the variable ScaleCoef[i] and InvScaleCoeff[i] with i in the range of 0 to MaxBinIdx, inclusive, are derived as follows:
The variable ChromaScaleCoef[i] with i in the range of 0 to MaxBinIdx, inclusive, are derived as follows:
At the encoder side, each picture (or tile group) is firstly converted to the reshaped domain. And all the coding process is performed in the reshaped domain. For intra prediction, the neighboring block is in the reshaped domain; for inter prediction, the reference blocks (generated from the original domain from decoded picture buffer) are firstly converted to the reshaped domain. Then the residual are generated and coded to the bitstream.
After the whole picture (or tile group) finishes encoding/decoding, samples in the reshaped domain are converted to the original domain, then deblocking filter and other filters are applied.
Forward reshaping to the prediction signal is disabled for the following cases:
Current block is intra-coded
Current block is coded as CPR (current picture referencing, aka intra block copy, IBC)
Current block is coded as combined inter-intra mode (CIIP) and the forward reshaping is disabled for the intra prediction block
In the current design of CPR/IBC, some problems exist.
In some embodiments, a regular buffer can be used for CPR/IBC block to get reference.
A function isRec(x, y) is defined to indicate if pixel (x, y) has been reconstructed and be referenced by IBC mode. When (x, y) is out of picture, of different slice/tile/brick, isRec(x, y) return false; when (x, y) has not been reconstructed, isRec(x, y) returns false. In another example, when sample (x, y) has been reconstructed but some other conditions are satisfied, it may also be marked as unavailable, such as out of the reference area/in a different VPDU, and isRec(x, y) returns false.
A function isRec(c, x,y) is defined to indicate if sample (x, y) for component c is available. For example, if the sample (x, y) hasn't been reconstructed yet, it is marked as unavailable. In another example, when sample (x, y) has been reconstructed but some other conditions are satisfied, it may also be marked as unavailable, such as it is out of picture/in a different slice/tile/brick/in a different VPDU, out of allowed reference area. isRec(c, x,y) returns false when sample (x, y) is unavailable, otherwise, it returns true.
In the following discussion, the reference samples can be reconstructed samples. It is noted that ‘pixel buffer’ may response to ‘buffer of one color component’ or ‘buffer of multiple color components’.
Reference Buffer for CPR/IBC
Denote the width and height of an IBC buffer as Wbuf and Hbuf. For a W×H block (may be a luma block, chroma block, CU, TU, 4×4, 2×2, or other subblocks) starting from (X, Y) relative to the upper-left corner of a picture, the following may apply to tell if a block vector (BVx, BVy) is valid or not. Let Wpic and Hpic be the width and height of a picture and; Wctu and Hctu be the width and height of a CTU. Function floor(x) returns the largest integer no larger than x. Function isRec(x, y) returns if sample (x, y) has been reconstructed.
The following, the width and height of a VPDU is denoted as WVPDU (e.g., 64) and HVPDU (e.g., 64), respectively in luma samples. Alternatively, WVPDU and/or HVPDU may denote the width and/or height of other video unit (e.g., CTU).
An implementation of the buffer for IBC is described below:
The buffer size is 128×128. CTU size is also 128×128. For coding of the 1st CTU in a CTU row, the buffer is initialized with 128 (for 8-bit video signal). For coding of the k-th CTU in a CTU row, the buffer is initialized with the reconstruction before loop-filtering of the (k−1)-th CTU.
When coding a block starting from (x, y) related to the current CTU, a block vector (BVx, BVy)=(x−x0, y−y0) is sent to the decoder to indicate the reference block is from (x0,y0) in the IBC buffer. Suppose the width and height of the block are w and h respectively. When finishing coding of the block, a w×h area starting from (x, y) in the IBC buffer will be updated with the block's reconstruction before loop-filtering.
Suppose that CTU size is W×W, an implementation of IBC buffer with size mW×W and bitdepth being B, at the decoder is as below.
At the beginning of decoding a CTU row, initialize the buffer with value (1<<(B−1)) and set the starting point to update (xb, yb) to be (0,0).
When a CU starting from (x, y) related to a CTU upper-left corner and with size wxh is decoded, the area starting from (xb+x, yb+y) and w×h size will be updated with the reconstructed pixel values of the CU, after bit-depth aligned to B-bit.
After a CTU is decoded, the starting point to update (xb, yb) will be set as ((xb+W) mod mW, 0).
When decoding an IBC CU with block vector (BVx, BVy), for any pixel (x, y) related to a CTU upper-left corner, its prediction is extracted from the buffer at position ((x+BVx) mod mW, (y+BVy) mode W) after bit-depth alignment to the bit-depth of prediction signals.
In one example, B is set to 7, or 8 while the output/input bitdepth of the block may be equal to 10.
For a luma CU or joint luma/chroma CU starting from (x, y) related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(((x+BVx)>>6<<6)+128−(((y+BVy)>>6)&1)*64+(x %64), ((y+BVy)>>6<<6)+(y %64)) is true.
For a chroma CU starting from (x, y) related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(((x+BVx)>>5<<5)+64−(((y+BVy)>>5)&1)*32+(x %32), ((y+BVy)>>5<<5)+(y %32)) is true.
For a chroma block or sub-block starting from (x, y) in 4:2:0 format related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(c, (x+BVx+64, y+BVy) is true, where c is a chroma component.
For a chroma block or sub-block starting from (x, y) in 4:4:4 format related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(c, (x+BVx+128, y+BVy) is true, where c is a chroma component.
For a luma CU or joint luma/chroma CU starting from (x, y) related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(((x+BVx)>>6<<6)+128−(((y+BVy)>>6)&1)*64+(x %64), ((y+BVy)>>6<<6)+(y %64)) is true.
For a chroma block or sub-block starting from (x, y) in 4:2:0 format related to the upper-left corner of a picture and a block vector (BVx, BVy), the block vector is invalid when isRec(c, ((x+BVx)>>5<<5)+64−(((y+BVy)>>5)&1)*32+(x %32), ((y+BVy)>>5<<5)+(y %32)) is true, where c is a chroma component.
This embodiment highlights an implementation of keeping two most coded VPDUs in the 1st VPDU row and one most coded VPDU in the 2nd VPDU row of a CTU/CTB row, excluding the current VPDU.
When VPDU coding order is top to bottom and left to right, the reference area is illustrated as in
When VPDU coding order is left to right and top to bottom and the current VPDU is not to the right side of the picture boundary, the reference area is illustrated as in
When VPDU coding order is left to right and top to bottom and the current VPDU is to the right side of the picture boundary, the reference area may be illustrated as
Given a luma block (x, y) with size w×h, a block vector (BVx, BVy) is valid or not can be told by checking the following condition:
isRec(((x+BVx+128)>>6<<6)−(refy&0x40)+(x%64),((y+BVy)>>6<<6)+(refy>>6==y>>6)?(y%64):0), where refy=(y&0x40)?(y+BVy):(y+BVy+w−1).
If the above function returns true, the block vector (BVx, BVy) is invalid, otherwise the block vector might be valid.
If CTU size is 192×128, a virtual buffer with size 192×128 is maintained to track the reference samples for IBC.
A sample (x, y) relative to the upper-left corner of the picture is associated with the position (x %192, y %128) relative to the upper-left corner of the buffer. The following steps show how to mark availability of the samples associate with the virtual buffer for IBC reference.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
If CTU size is 128×128 or CTU size is greater than VPDU size (e.g., 64×64 in current design) or CTU size is greater than VPDU size (e.g., 64×64 in current design), a virtual buffer with size 192×128 is maintained to track the reference samples for IBC. In the following, when a<0, (a % b) is defined as floor(a/b)*b, where Floor© returns the largest integer no larger than c.
A sample (x, y) relative to the upper-left corner of the picture is associated with the position (x %192, y %128) relative to the upper-left corner of the buffer. The following steps show how to mark availability of the samples associate with the virtual buffer for IBC reference.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
If CTU size is SxS, S is not equal to 128, let Wbuf be equal to 128*128/S. A virtual buffer with size WbufxS is maintained to track the reference samples for IBC. The VPDU size is equal to the CTU size in such a case.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
If CTU size is 128×128 or CTU size is greater than VPDU size (e.g., 64×64 in current design) or CTU size is greater than VPDU size (e.g., 64×64 in current design), a virtual buffer with size 256×128 is maintained to track the reference samples for IBC. In the following, when a<0, (a % b) is defined as floor(a/b)*b, where Floor© returns the largest integer no larger than c.
A sample (x, y) relative to the upper-left corner of the picture is associated with the position (x %256, y %128) relative to the upper-left corner of the buffer. The following steps show how to mark availability of the samples associate with the virtual buffer for IBC reference.
A position (xPrevVPDU, yPrevVPDU) relative to the upper-left corner of the picture is recorded to stand for the upper-left sample of the most recently decoded VPDU.
When CTU size is not 128×128 or less than 64×64 or less than 64×64, the same process applies as in the previous embodiment, i.e. embodiment #14.
An IBC reference availability marking process is described as follows. The changes are indicated in bolded, underlined, italicized text in this document.
7.3.7.1 General Slice Data Syntax
BufWidth is equal to (CtbSizeY=128)?256:(128*128/CtbSizeY) and BufHeight is equal to CtbSizeY.
7.3.7.5 Coding Unit Syntax
8.6.2 Derivation Process for Motion Vector Components for IBC Blocks
8.6.2.1 General
. . .
It is a requirement of bitstream conformance that when the block vector validity checking process in clause 8.6.3.2 is invoked with the block vector mvL, isBVvalid shall be true.
. . .
8.6.3 Decoding Process for Ibc Blocks
8.6.3.1 General
This process is invoked when decoding a coding unit coded in ibc prediction mode.
Inputs to this process are:
. . .
For each coding subblock at subblock index (xSbIdx, ySbIdx) with xSbIdx=0 numSbX−1, and ySbIdx=0 . . . numSbY−1, the following applies:
If cIdx is equal to 0, nIbcBufW is set to ibcBufferWidth, otherwise nIbcBufW is set to (ibcBufferWidth/SubWidthC). The foiling applies:
predSamples[xSb+x][ySb+y]=ibcBuf[(xSb+x+(mv[xSb][ySb][0]>>4))% nIbcRefW][ySb+y+(mv[xSb][ySb][1]>>4)]
Inputs to this process are:
Outputs of this process is a flag isBVvalid to indicate if the block vector is valid or not.
The following applies
if (isDecoded[xTL>>2][yTL>>2]==0) or (isDecoded[xBR>>2][yTL>>2]==0) or (isDecoded[xBR>>2][yBR>>2]==0), isBVvalid is set aural to false.
8.7.5 Picture Reconstruction Process
8.7.5.1 General
Inputs to this process are:
Output of this process are
Denote nIbcBufW as the width of ibcBuf, the following applies:
ibcBuf[(xCurr+i) & (nIbcBufW−1)][(yCurr+j) & (ctbSize−1)]=recSamples[xCurr+i][yCurr+j]
This is identical to the previous embodiment except for the following changes
BufWidth is equal to (CtbSizeY==128)?192:(128*128/CtbSizeY) and BufHeight is equal to CtbSizeY.
The changes in some examples are indicated in bolded, underlined, text in this document.
7.3.7 Slice Data Syntax
7.3.7.1 General Slice Data Syntax
7.4.8.5 Coding Unit Semantics
When all the following conditions are true, the history-based motion vector predictor list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138)
Set vSize as min(ctbSize, 64) and wIbcBuf as (128*128/ctbSize). The width and height of ibcBuf is wIbcBuf and ctbSize accordingly.
If refreshIbcBuf is equal to 1, the following applies
When (x0% vSize) is equal to 0 and (y0% vSize) is equal to 0, for x=x0 . . . x0+vSize−1 and y=y0 . . . y0+vSize−1, the following applies
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
It is a requirement of bitstream conformance that the luma block vector mvL shall obey the following constraints:
((yCb+(mvL[1]>>4))% wIbcBuf)+cbHeight is less than or equal to ctbSize
For x=xCb . . . xCb+cbWidth−1 and y=yCb . . . yCb+cbHeight−1, ibcBuff[(x+(myL[0]>>4))% wIbcBuf][(y+(mvL[1]>>4))% ctbSize] shall not be equal to −1.
8.7.5 Picture Reconstruction Process
8.7.5.1 General
Inputs to this process are:
Output of this process are a reconstructed picture sample array recSamples and an IBC buffer array ibcBuf.
Depending on the value of the colour component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
After decoding the current coding unit, the following applies:
ibcBuf[(xCurr+i) % wIbcBuf][yCurr+j) % ctbSize]=recSamples[xCurr+i][yCurr+j]
for i=0 . . . nCurrSw−1, j=0 . . . nCurrSh−1.
The changes in some examples are indicated in bolded, underlined, italicized text in this document.
7.3.7 Slice Data Syntax
7.3.7.1 General Slice Data Syntax
7.4.8.5 Coding Unit Semantics
When all the following conditions are true, the history-based motion vector predictor list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138)
Set vSize as min(ctbSize, 64) and wIbcBufY as (128*128/CtbSizeY).
ibcBufL is a array with width being wIbcBufY and height being CtbSizeY.
ibcBufCb and ibcBufCr are arrays with width being wIbcBufC=(wIbcBufY/SubWidthC) and height being (CtbSizeY/SubHeightC), i.e. CtbSizeC.
If resetIbcBuf is equal to 1, the following applies
ibcBufL[x% wIbcBufY][y% CtbSizeY]=−1, for x=x0 . . . x0+wIbcBufY−1 and y=y0 . . . y0+CtbSizeY−1
ibcBufCr[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0 . . . x0+wIbcBufC−1 and y=y0 . . . y0+CtbSizeC−1
ibcBufCr[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0 . . . x0+wIbcBufC−1 and y=y0 . . . y0+CtbSizeC−1
When (x0% vSizeY) is equal to 0 and (y0% vSizeY) is equal to 0, the following applies
ibcBufL[x% wIbcBufY][y% CtbSizeY]=−1, for x=x0 . . . x0+vSize−1 and y=y0 . . . y0+vSize−1
ibcBufCb[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0/SubWidthC . . . x0/SubWidthC+vSize/SubWidthC−1 and y=y0/SubHeightC . . . y0/SubHeightC+vSize/SubHeightC−1
ibcBufCr[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0/SubWidthC . . . x0/SubWidthC+vSize/SubWidthC−1 and y=y0/SubHeightC . . . y0/SubHeightC+vSize/SubHeightC−1
8.6.2 Derivation Process for Motion Vector Components for IBC Blocks
8.6.2.1 General
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
Clause 8.6.2.5 is invoked with mvL as input and mvC as output.
It is a requirement of bitstream conformance that the luma block vector mvL shall obey the following constraints:
((yCb+(mvL[1]>>4))% CtbSizeY)+cbHeight is less than or equal to CtbSizeY
This process is invoked when decoding a coding unit coded in ibc prediction mode.
Inputs to this process are:
Outputs of this process are:
For x=xCb . . . xCb+Width−1 and y=yCb . . . yCb+Height−1, the following applies
If cIdx is qual to 0
predSamples[x][y]=ibcBufL[(x+mv[0]>>4))% wIbcBufY][(y+(mv[1]>>4))% CtbSizeY]
if cIdx is equal to 1
predSamples[x][y]=ibcBufCb[(x+mv[0]>>5))% wIbcBufC][(y+(mv[1]>>5))% CtbSizeC]
if cIdx is equal to 2
predSamples[x][y]=ibcBufCr[(x+mv[0]>>5))% wIbcBufC][(y+(mv[1]>>5))% CtbSizeC]
8.7.5 Picture Reconstruction Process
8.7.5.1 General
Inputs to this process are:
Output of this process are a reconstructed picture sample array recSamples and IBC buffer arrays ibcBufL, ibcBufCb, ibcBufCr.
Depending on the value of the colour component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
After decoding the current coding unit, the following may apply:
If cIdx is equal to 0, and if treeType is equal to SINGLE_TREE or DUAL_TREE_LUMA, the following applies
ibcBufL[(xCurr+i) % wIbcBufY][(yCurr+j) % CtbSizeY]=recSamples[xCurr+i][yCurr+j]
If cIdx is equal to 1, and if treeType is equal to SINGLE_TREE or DUAL_TREE_CHROMA, the following applies
ibcBufCb[(xCurr+i) % wIbcBufC][(yCurr+j) % CtbSizeC]=recSamples[xCurr+i][yCurr+j]
If cIdx is equal to 2, and if treeType is equal to SINGLE_TREE or DUAL_TREE_CHROMA, the following applies
ibcBufCr[(xCurr+i) % wIbcBufC][(yCurr+j) % CtbSizeC]=recSamples[xCurr+i][yCurr+i]
The changes in some examples are indicated in bolded, underlined, text in this document.
7.3.7 Slice Data Syntax
7.3.7.1 General Slice Data Syntax
7.4.8.5 Coding Unit Semantics
When all the following conditions are true, the history-based motion vector predictor list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
IsInSmr[x0][y0] is equal to TRUE.
SmrX[x0][y0] is equal to x0.
SmrY[x0][y0] is equal to y0.
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138)
Set vSize as min(ctbSize, 64) and wIbcBufY as (128*128/CtbSizeY).
ibcBufL is a array with width being wIbcBufY and height being CtbSizeY.
ibcBufCb and ibcBufCr are arrays with width being wIbcBufC=(wIbcBufY/SubWidthC) and height (CtbSizeY/SubHeightC), i.e. CtbSizeC.
If resetIbcBuf is equal to 1, the following applies
ibcBufL[x% wIbcBufY][y% CtbSizeY]=−1, for x=x0 . . . x0+wIbcBufY−1 and y=y0 . . . y0+CtbSizeY−1
ibcBufCb[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0 . . . x0+wIbcBufC−1 and y=y0 . . . y0+CtbSizeC−1
ibcBufCr[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0 . . . x0+wIbcBufC−1 and y=y0 . . . y0+CtbSizeC−1
When (x0% vSizeY) is equal to 0 and (v0% vSizeY) is equal to 0, the following applies
ibcBufL[x% wIbcBufY][y% CtbSizeY]=−1, for x=x0 . . . x0+min(vSize,cbWidth)−1 and y=y0 . . . v0+min(vSize,cbHeight)−1
ibcBufCb[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0/SubWidthC . . . x0/SubWidthC+min(vSize/SubWidthC, cbWidth)−1 and
y=y0/SubHeightC . . . y0/SubHeightC+min(vSize/SubHeightC,cbHeight)−1
ibcBufCr[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0/SubWidthC . . . x0/SubWidthC+min(vSize/SubWidthC,cbWidth)−1 and
y=y0/SubHeightC . . . y0/SubHeightC+min(vSize/SubHeightC,cbHeight)−1
8.6.2 Derivation Process for Motion Vector Components for IBC Blocks
8.6.2.1 General
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
Clause 8.6.2.5 is invoked with mvL as input and mvC as output.
It is a requirement of bitstream conformance that the luma block vector mvL shall obey the following constraints:
((yCb+(mvL[1]>>4))% CtbSizeY)+cbHeight is less than or equal to CtbSizeY
This process is invoked when decoding a coding unit coded in ibc prediction mode.
Inputs to this process are:
Outputs of this process are:
For x=xCb . . . xCb+Width−1 and y=yCb . . . yCb+Height−1, the following applies
If cIdx is qual to 0
predSamples[x][y]=ibcBufL[(x+mv[0]>>4))% wIbcBufY][(y+(mv[1]>>4))% CtbSizeY]
if cIdx is equal to 1
predSamples[x][y]=ibcBufCb(x+mv[0]>>5))% wIhcBufC][(y+(mv[1]>>5))% CtbSizeC]
if cIdx is equal to 2
predSamples[x][y]=ibcBufCr[(x+mv[0]>>5))% wThcBufC][(y+(mv[1]>>5))% CtbSizeC]
8.7.5 Picture Reconstruction Process
8.7.5.1 General
Inputs to this process are:
Output of this process are a reconstructed picture sample array recSamples and IBC buffer arrays ibcBufL, ibcBufCb, ibcBufCr.
Depending on the value of the colour component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
After decoding the current coding unit, the following may apply:
If cIdx is equal to 0, and if treeType is equal to SINGLE_TREE or DUAL_TREE_LUMA, the following applies
ibcBufL[(xCurr+i) % wIbcBufY][(yCurr+j) % CtbSizeY]=recSamples[xCurr+i][yCurr+j]
If cIdx is equal to 1, and if treeType is equal to SINGLE_TREE or DUAL_TREE_CHROMA, the following applies
ibcBufCb[(xCurr+i) % wIbcBufC][(yCurr+j) % CtbSizeC]=recSamples[xCurr+i][yCurr+j]
If cIdx is equal to 2, and if treeType is equal to SINGLE_TREE or DUAL_TREE_CHROMA, the following applies
ibcBufCr[(xCurr+i) % wIbcBufC][(yCurr+j) % CtbSizeC]=recSamples[xCurr+i][yCurr+j]
The changes in some examples are indicated in bolded, underlined, italicized text in this document.
7.3.7 Slice Data Syntax
7.3.7.1 General Slice Data Syntax
7.4.8.5 Coding Unit Semantics
When all the following conditions are true, the history-based motion vector predictor list for the shared merging candidate list region is updated by setting NumHmvpSmrIbcCand equal to NumHmvpIbcCand, and setting HmvpSmrIbcCandList[i] equal to HmvpIbcCandList[i] for i=0 . . . NumHmvpIbcCand−1:
The following assignments are made for x=x0 . . . x0+cbWidth−1 and y=y0 . . . y0+cbHeight−1:
CbPosX[x][y]=x0 (7-135)
CbPosY[x][y]=y0 (7-136)
CbWidth[x][y]=cbWidth (7-137)
CbHeight[x][y]=cbHeight (7-138)
Set vSize as min(ctbSize, 64) and wIbcBufY as (128*128/CtbSizeY).
ibcBufL is a array with width being wIbcBufY and height being CtbSizeY.
ibcBufCb and ibcBufCr are arrays with width being wIbcBufC=(wIbcBufY/SubWidthC) and height being (CtbSizeY/SubHeightC), i.e. CtbSizeC.
If resetIbcBuf is equal to 1, the following applies
ibcBufL[x% wIbcBufY][y% CtbSizeY]=−1, for x=x0 . . . x0+wIbcBufY−1 and y=y0 . . . y0+CtbSizeY−1
ibcBufCb[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0 . . . x0+wIbcBufC−1 and y=y0 . . . y0+CtbSizeC−1
ibcBufCr[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0 . . . x0+wIbcBufC−1 and v=v0.40+CtbSizeC]
When (x0% vSizeY) is equal to 0 and (y0% vSizeY) is equal to 0, the following applies
ibcBufL[x% wIbcBufY][y% CtbSizeY]=−1, for x=x0 . . . x0+max(vSize,cbWidth)−1 and y=y0 . . . y0+max(vSize,cbHeight)−1
ibcBufCb[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0/SubWidthC . . . x0/SubWidthC+max(vSize/SubWidthC,cbWidth)−1 and
y=y0/SubHeightC . . . y0/SubHeightC+max(vSize/SubHeightC,cbHeight)−1
ibcBufCr[x% wIbcBufC][y% CtbSizeC]=−1, for x=x0/SubWidthC . . . x0/SubWidthC+max(vSize/SubWidthC,cbWidth)−1 and
y=y0/SubHeightC . . . y0/SubHeightC+max(vSize/SubHeightC,cbHeight)−1
8.6.2 Derivation Process for Motion Vector Components for IBC Blocks
8.6.2.1 General
Inputs to this process are:
Outputs of this process are:
The luma motion vector mvL is derived as follows:
The updating process for the history-based motion vector predictor list as specified in clause 8.6.2.6 is invoked with luma motion vector mvL.
Clause 8.6.2.5 is invoked with mvL as input and mvC as output.
It is a requirement of bitstream conformance that the luma block vector mvL shall obey the following constraints:
((yCb+(mvL[1]>>4))% CtbSizeY)+cbHeight is less than or equal to CtbSizeY
This process is invoked when decoding a coding unit coded in ibc prediction mode.
Inputs to this process are:
Outputs of this process are:
For x=xCb . . . xCb+Width−1 and y=yCb . . . yCb+Height−1, the following applies
If cIdx is equal to 0
predSamples[x][y]=ibcBufL(x+mv[0]>>4))% wIbcBuf[Y][(y+(mv[1]>>4))% CtbSizeY]
if cIdx is equal to 1
predSamples[x][y]=ibcBufCb[(x+mv[0]>>5))% wIbcBufC][(y+(mv[1]>>5))% CtbSizeC]
if cIdx is equal to 2
predSamples[x][y]=ibcBufCr[(x+mv[0]>>5))% wIbcBufC][(y+(mv[1]>>5))% CtbSizeC]
8.7.5 Picture Reconstruction Process
8.7.5.1 General
Inputs to this process are:
Output of this process are a reconstructed picture sample array recSamples and IBC buffer arrays ibcBufL, ibcBufCb, ibcBufCr.
Depending on the value of the colour component cIdx, the following assignments are made:
Depending on the value of slice_lmcs_enabled_flag, the following applies:
After decoding the current coding unit, the following may apply:
If cIdx is equal to 0, and if treeType is equal to SINGLE_TREE or DUAL_TREE_LUMA, the following applies
ibcBufL(xCurr+i) % wIbcBuf[Y][(yCurr+j) % CtbSizeY]=recSamples[xCurr+i][yCurr+i]
If cIdx is equal to 1, and if treeType is equal to SINGLE_TREE or DUAL_TREE_CHROMA, the following applies
ibcBufCb[(xCurr+i) % wIbcBufC][(yCurr+j) % CtbSizeC]=recSamples[xCurr+i][yCurr+j]
If cIdx is equal to 2, and if treeType is equal to SINGLE_TREE or DUAL_TREE_CHROMA, the following applies
ibcBufCr[(xCurr+i) % wIbcBufC][(yCurr+j) % CtbSizeC]=recSamples[xCurr+i][yCurr+j]
The following clauses describe some example preferred features implemented by embodiments of method 600 and other methods. Additional examples are provided in Section 4 of the present document.
Additional embodiments and examples of clauses 37 to 41 are described in Item 7 in Section 4.
Additional embodiments and examples of clauses 42 to 43 are described in Item 28 to 31 and 34 in Section 4.
Additional embodiments and examples of clause 4 are described in Item 35 in Section 4.
Additional embodiments and examples of clause 4 are described in Item 36 in Section 4.
Items 23-30 in the previous section provide additional examples and variations of the above clauses 58-62.
The bitstream representation corresponding to a current video block need not be a contiguous set of bits and may be distributed across headers, parameter sets, and network abstraction layer (NAL) packets.
In Section A, we present another example embodiment in which the current version of the VVC standard may be modified for implementing some of the techniques described in the present document.
This section analyzes several issues in the current IBC reference buffer design and presents a different design to address the issues. An independent IBC reference buffer is proposed instead of mixing with decoding memory. Compared with the current anchor, the proposed scheme shows −0.99%/−0.71%/−0.79% AI/RA/LD-B luma BD-rate for class F and −2.57%/−1.81%/−1.36% for 4:2:0 TGM, with 6.7% memory reduction; or −1.31%/−1.01%/−0.81% for class F and −3.23%/−2.33%/−1.71% for 4:2:0 TGM with 6.7% memory increase.
Intra block copy, i.e. IBC (or current picture referencing, i.e. CPR previously) coding mode, is adopted. It is realized that IBC reference samples should be stored in on-chip memory and thus a limited reference area of one CTU is defined. To restrict the extra on-chip memory for the buffer, the current design reuses the 64×64 memory for decoding the current VPDU so that only 3 additional 64×64 blocks' memory is needed to support IBC. When CTU size is 128×128, currently the reference area is shown in
In the current draft (VVC draft 4), the area is defined as
Thus, the total reference size is a CTU.
The current design assumes to reuse the 64×64 memory for decoding the current VPDU and the IBC reference is aligned to VPDU memory reuse accordingly. Such a design bundles VPDU decoding memory with the IBC buffer. There might be several issues:
To address issues listed in the above sub-section, we propose to have a dedicated IBC buffer, which is not mixed with decoding memory.
For 128×128 CTU, the buffer is defined as 128×128 with 8-bit samples, when a CU (x, y) with size w×h has been decoded, its reconstruction before loop-filtering is converted to 8-bit and written to the w×h block area starting from position (x %128, y %128). Here the modulo operator % always returns a positive number, i.e. for x<0, x % L¬−(−x % L), e.g. −3%128=125.
Assume that a pixel (x, y) is coded in IBC mode with BV=(BVx, BVy), it is prediction sample in the IBC reference buffer locates at ((x+BVx) %128, (y+BVy) %128) and the pixel value will be converted to 10-bit before prediction.
When the buffer is considered as (W, H), after decoding a CTU or CU starting from (x, y), the reconstructed pixels before loop-filtering will be stored in the buffer starting from (x % W, y % H). Thus, after decoding a CTU, the corresponding IBC reference buffer will be updated accordingly. Such setting might happen when CTU size is not 128×128. For example, for 64×64 CTU, with the current buffer size, it can be considered as a 256×64 buffer. For 64×64 CTU,
In such a design, because the IBC buffer is different from the VPDU decoding memory, all the IBC reference buffer can be used as reference.
When the bit-depth of the IBC buffer is 8-bit, compared with the current design that needs 3 additional 10-bit 64×64 buffer, the on-chip memory increase is (8*4)/(10*3)−100%=6.7%.
If we further reduce the bit-depth. The memory requirement can be further reduced. For example, for 7-bit buffer, the on-chip memory saving is 100%−(7*4)/(10*3)=6.7%.
With the design, the only bitstream conformance constrain is that the reference block shall be within the reconstructed area in the current CTU row of the current Tile.
When initialization to 512 is allowed at the beginning of each CTU row, all bitstream conformance constrains can be removed.
In some embodiments, the disclosed methods can be implemented using VTM-4.0 software.
For a 10-bit buffer implementation and CTC, the decoder is fully compatible to the current VTM4.0 encoder, which means that the proposed decoder can exactly decode the VTM-4.0 CTC bitstreams.
For a 7-bit buffer implementation, the results shown in Table I.
For a 8-bit buffer implementation, the results shown in Table II.
The system 1700 may include a coding component 1704 that may implement the various coding or encoding methods described in the present document. The coding component 1704 may reduce the average bitrate of video from the input 1702 to the output of the coding component 1704 to produce a coded representation of the video. The coding techniques are therefore sometimes called video compression or video transcoding techniques. The output of the coding component 1704 may be either stored, or transmitted via a communication connected, as represented by the component 1706. The stored or communicated bitstream (or coded) representation of the video received at the input 1702 may be used by the component 1708 for generating pixel values or displayable video that is sent to a display interface 1710. The process of generating user-viewable video from the bitstream representation is sometimes called video decompression. Furthermore, while certain video processing operations are referred to as “coding” operations or tools, it will be appreciated that the coding tools or operations are used at an encoder and corresponding decoding tools or operations that reverse the results of the coding will be performed by a decoder.
Examples of a peripheral bus interface or a display interface may include universal serial bus (USB) or high definition multimedia interface (HDMI) or Displayport, and so on. Examples of storage interfaces include SATA (serial advanced technology attachment), PCI, IDE interface, and the like. The techniques described in the present document may be embodied in various electronic devices such as mobile phones, laptops, smartphones or other devices that are capable of performing digital data processing and/or video display.
Some embodiments of the present document are now presented in clause-based format.
1. A method of visual media processing, comprising:
2. The method of 1, wherein the reference location (P, Q) is determined as P=x0+BVx and Q=y0+BVy.
3. A method of visual media processing, comprising:
4. The method of clause 3, wherein the reference location (P, Q) is determined as P=x0+BVx, and Q=y0+BVy.
5. The method of any one or more of clauses 3-4, further comprising:
6. The method of any one or more of clauses 3-4, further comprising:
7. The method of clause 6, wherein the predetermined value corresponds to a mid-grey value.
8. A method of visual media processing, comprising:
9. The method of clause 8, wherein the x and y numbers vary as follows:
10. The method of clause 8, wherein the pixel locations within the buffer are addressed using a single number denoted 1 such that 1=y*M+x, 1=0, 1, . . . , M*N−1, wherein M and N are pixel width and pixel height of the buffer.
11. The method of any one or more of clauses 8-10, wherein, the current bitstream representation includes a block vector for the conversion, wherein the block vector, denoted as (BVx,BVy) is equal to (x−x0,y−y0) in the buffer, wherein (x0, y0) correspond to an upper-left position of a coding tree unit including the current video block.
12. The method of any one or more of clauses 8-10, wherein, the current bitstream representation includes a block vector for the conversion, wherein the block vector, denoted as (BVx,BVy) is equal to (x−x0+Tx,y−y0+Ty) in the buffer, where (x0, y0) correspond to an upper-left position of a coding tree unit including the current video block and wherein Tx and Ty are offset values.
13. The method of clause 12, wherein Tx and Ty are pre-defined offset values.
14. The method of any of clauses 1-13, wherein the conversion includes generating the bitstream representation from the current video block.
15. The method of any of clauses 1-13, wherein the conversion includes generating pixel values of the current video block from the bitstream representation.
16. A video encoder apparatus comprising a processor configured to implement a method recited in any one or more of clauses 1-13.
17. A video decoder apparatus comprising a processor configured to implement a method recited in any one or more of clauses 1-13.
18. A computer readable medium having code stored thereon, the code embodying processor-executable instructions for implementing a method recited in any of or more of clauses 1-13.
In the present document, the term “video processing” may refer to video encoding, video decoding, video compression or video decompression. For example, video compression algorithms may be applied during conversion from pixel representation of a video to a corresponding bitstream representation or vice versa. The bitstream representation of a current video block may, for example, correspond to bits that are either co-located or spread in different places within the bitstream, as is defined by the syntax. For example, a macroblock may be encoded in terms of transformed and coded error residual values and also using bits in headers and other fields in the bitstream.
From the foregoing, it will be appreciated that specific embodiments of the presently disclosed technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the presently disclosed technology is not limited except as by the appended claims.
Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing unit” or “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
It is intended that the specification, together with the drawings, be considered exemplary only, where exemplary means an example. As used herein, the use of “or” is intended to include “and/or”, unless the context clearly indicates otherwise.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
Number | Date | Country | Kind |
---|---|---|---|
PCT/CN2019/074598 | Feb 2019 | WO | international |
PCT/CN2019/076695 | Mar 2019 | WO | international |
PCT/CN2019/076848 | Mar 2019 | WO | international |
PCT/CN2019/077725 | Mar 2019 | WO | international |
PCT/CN2019/079151 | Mar 2019 | WO | international |
PCT/CN2019/085862 | May 2019 | WO | international |
PCT/CN2019/088129 | May 2019 | WO | international |
PCT/CN2019/091691 | Jun 2019 | WO | international |
PCT/CN2019/093552 | Jun 2019 | WO | international |
PCT/CN2019/094957 | Jul 2019 | WO | international |
PCT/CN2019/095297 | Jul 2019 | WO | international |
PCT/CN2019/095504 | Jul 2019 | WO | international |
PCT/CN2019/095656 | Jul 2019 | WO | international |
PCT/CN2019/095913 | Jul 2019 | WO | international |
PCT/CN2019/096048 | Jul 2019 | WO | international |
This application is a continuation of International Application No. PCT/CN2020/074160 filed on Feb. 2, 2020, which claims the priority to and benefits of International Patent Application No. PCT/CN2019/074598, filed on Feb. 2, 2019, International Patent Application No. PCT/CN2019/076695, filed on Mar. 1, 2019, International Patent Application No. PCT/CN2019/076848, filed on Mar. 4, 2019, International Patent Application No. PCT/CN2019/077725, filed on Mar. 11, 2019, International Patent Application No. PCT/CN2019/079151, filed on Mar. 21, 2019, International Patent Application No. PCT/CN2019/085862, filed on May 7, 2019, International Patent Application No. PCT/CN2019/088129, filed on May 23, 2019, International Patent Application No. PCT/CN2019/091691, filed on Jun. 18, 2019, International Patent Application No. PCT/CN2019/093552, filed on Jun. 28, 2019, International Patent Application No. PCT/CN2019/094957, filed on Jul. 6, 2019, International Patent Application No. PCT/CN2019/095297, filed on Jul. 9, 2019, International Patent Application No. PCT/CN2019/095504, filed on Jul. 10, 2019, International Patent Application No. PCT/CN2019/095656, filed on Jul. 11, 2019, International Patent Application No. PCT/CN2019/095913, filed on Jul. 13, 2019, and International Patent Application No. PCT/CN2019/096048, filed on Jul. 15, 2019. The entire disclosures of the aforementioned applications are incorporated by reference as part of the disclosure of this application.
Number | Name | Date | Kind |
---|---|---|---|
7916728 | Mimms | Mar 2011 | B1 |
8295361 | Tseng et al. | Oct 2012 | B2 |
8947449 | Dodd | Feb 2015 | B1 |
9426463 | Seregin et al. | Aug 2016 | B2 |
9491460 | Seregin et al. | Nov 2016 | B2 |
9591325 | Li et al. | Mar 2017 | B2 |
9860559 | Zhang et al. | Jan 2018 | B2 |
9877043 | He et al. | Jan 2018 | B2 |
9918105 | Pang et al. | Mar 2018 | B2 |
10148981 | Zhu et al. | Dec 2018 | B2 |
10178403 | Seregin et al. | Jan 2019 | B2 |
10200706 | Hellman | Feb 2019 | B2 |
10264290 | Xu et al. | Apr 2019 | B2 |
10284874 | He et al. | May 2019 | B2 |
10306240 | Xiu et al. | May 2019 | B2 |
10368091 | Li et al. | Jul 2019 | B2 |
10412387 | Pang et al. | Sep 2019 | B2 |
10440378 | Xu et al. | Oct 2019 | B1 |
10469863 | Zhu et al. | Nov 2019 | B2 |
10516882 | He et al. | Dec 2019 | B2 |
10567754 | Li et al. | Feb 2020 | B2 |
10582213 | Li et al. | Mar 2020 | B2 |
10728552 | Tsukuba | Jul 2020 | B2 |
10841607 | Park et al. | Nov 2020 | B2 |
10873748 | Chen et al. | Dec 2020 | B2 |
11025945 | Park et al. | Jun 2021 | B2 |
11070816 | Xu et al. | Jul 2021 | B2 |
11184637 | Li et al. | Nov 2021 | B2 |
11228775 | Xu et al. | Jan 2022 | B2 |
11375217 | Xu et al. | Jun 2022 | B2 |
11438613 | Xu et al. | Sep 2022 | B2 |
11523107 | Xu et al. | Dec 2022 | B2 |
11528476 | Xu et al. | Dec 2022 | B2 |
11546581 | Xu et al. | Jan 2023 | B2 |
11570753 | Xue et al. | Jan 2023 | B2 |
11575888 | Xu et al. | Feb 2023 | B2 |
11729414 | Park et al. | Aug 2023 | B2 |
11876957 | Jang et al. | Jan 2024 | B2 |
20040076237 | Kadono | Apr 2004 | A1 |
20040218816 | Hannuksela | Nov 2004 | A1 |
20050129115 | Jeon | Jun 2005 | A1 |
20050212970 | Joskin | Sep 2005 | A1 |
20060233237 | Lu et al. | Oct 2006 | A1 |
20060244748 | Long et al. | Nov 2006 | A1 |
20080025407 | Winger | Jan 2008 | A1 |
20080043845 | Nakaishi | Feb 2008 | A1 |
20080181300 | Hosaka et al. | Jul 2008 | A1 |
20080219352 | Tokumitsu et al. | Sep 2008 | A1 |
20080260034 | Wang et al. | Oct 2008 | A1 |
20100014584 | Feder et al. | Jan 2010 | A1 |
20100054329 | Bronstein et al. | Mar 2010 | A1 |
20100228957 | Rabinovitch et al. | Sep 2010 | A1 |
20110122950 | Ji et al. | May 2011 | A1 |
20110217714 | Makrigiorgos | Sep 2011 | A1 |
20110249754 | Karczewicz et al. | Oct 2011 | A1 |
20120002716 | Antonellis et al. | Jan 2012 | A1 |
20120201308 | Prasad et al. | Aug 2012 | A1 |
20120236931 | Karczewicz et al. | Sep 2012 | A1 |
20130003864 | Sullivan | Jan 2013 | A1 |
20130246746 | Gainey, Jr. et al. | Sep 2013 | A1 |
20130329784 | Chuang et al. | Dec 2013 | A1 |
20140072041 | Seregin et al. | Mar 2014 | A1 |
20140160139 | MacInnis et al. | Jun 2014 | A1 |
20140301465 | Kwon et al. | Oct 2014 | A1 |
20140314148 | Lainema et al. | Oct 2014 | A1 |
20140348240 | Kim et al. | Nov 2014 | A1 |
20140376611 | Kim et al. | Dec 2014 | A1 |
20150063440 | Pang et al. | Mar 2015 | A1 |
20150131724 | Lin et al. | May 2015 | A1 |
20150176721 | Schoonover et al. | Jun 2015 | A1 |
20150195559 | Chen et al. | Jul 2015 | A1 |
20150264348 | Zou et al. | Sep 2015 | A1 |
20150264372 | Kolesnikov et al. | Sep 2015 | A1 |
20150264373 | Wang et al. | Sep 2015 | A1 |
20150264383 | Cohen et al. | Sep 2015 | A1 |
20150264386 | Pang et al. | Sep 2015 | A1 |
20150264396 | Zhang et al. | Sep 2015 | A1 |
20150271487 | Li et al. | Sep 2015 | A1 |
20150271517 | Pang et al. | Sep 2015 | A1 |
20150296213 | Hellman | Oct 2015 | A1 |
20150334405 | Rosewarne et al. | Nov 2015 | A1 |
20150373357 | Pang et al. | Dec 2015 | A1 |
20150373358 | Pang et al. | Dec 2015 | A1 |
20150373359 | He et al. | Dec 2015 | A1 |
20160100163 | Rapaka et al. | Apr 2016 | A1 |
20160100189 | Pang | Apr 2016 | A1 |
20160104457 | Wu et al. | Apr 2016 | A1 |
20160105682 | Rapaka et al. | Apr 2016 | A1 |
20160219298 | Li et al. | Jul 2016 | A1 |
20160227222 | Hu et al. | Aug 2016 | A1 |
20160227244 | Rosewarne | Aug 2016 | A1 |
20160241858 | Li et al. | Aug 2016 | A1 |
20160241868 | Li et al. | Aug 2016 | A1 |
20160241875 | Wu et al. | Aug 2016 | A1 |
20160323573 | Ikai | Nov 2016 | A1 |
20160330474 | Liu et al. | Nov 2016 | A1 |
20160337661 | Pang et al. | Nov 2016 | A1 |
20160360210 | Xiu et al. | Dec 2016 | A1 |
20160360234 | Tourapis et al. | Dec 2016 | A1 |
20170054996 | Xu et al. | Feb 2017 | A1 |
20170070748 | Li et al. | Mar 2017 | A1 |
20170076419 | Fries et al. | Mar 2017 | A1 |
20170094271 | Liu et al. | Mar 2017 | A1 |
20170094299 | Damudi et al. | Mar 2017 | A1 |
20170094314 | Zhao et al. | Mar 2017 | A1 |
20170099490 | Seregin et al. | Apr 2017 | A1 |
20170099495 | Rapaka et al. | Apr 2017 | A1 |
20170134724 | Liu et al. | May 2017 | A1 |
20170142418 | Li et al. | May 2017 | A1 |
20170188033 | Lin et al. | Jun 2017 | A1 |
20170223379 | Chuang et al. | Aug 2017 | A1 |
20170280159 | Xu et al. | Sep 2017 | A1 |
20170289566 | He et al. | Oct 2017 | A1 |
20170289572 | Ye et al. | Oct 2017 | A1 |
20170295379 | Sun et al. | Oct 2017 | A1 |
20170302936 | Li et al. | Oct 2017 | A1 |
20170372494 | Zhu et al. | Dec 2017 | A1 |
20170374369 | Chuang et al. | Dec 2017 | A1 |
20180048909 | Liu et al. | Feb 2018 | A1 |
20180101708 | Gao | Apr 2018 | A1 |
20180103260 | Chuang et al. | Apr 2018 | A1 |
20180115787 | Koo et al. | Apr 2018 | A1 |
20180152727 | Chuang et al. | Apr 2018 | A1 |
20180124411 | Nakagami | May 2018 | A1 |
20180160122 | Xu et al. | Jun 2018 | A1 |
20180184093 | Xu et al. | Jun 2018 | A1 |
20180205966 | Kang et al. | Jul 2018 | A1 |
20180220130 | Zhang et al. | Aug 2018 | A1 |
20180255304 | Jeon et al. | Sep 2018 | A1 |
20180302645 | Laroche et al. | Oct 2018 | A1 |
20180343471 | Jacobson et al. | Nov 2018 | A1 |
20180376165 | Alshin et al. | Dec 2018 | A1 |
20190007705 | Zhao et al. | Jan 2019 | A1 |
20190031194 | Kim et al. | Jan 2019 | A1 |
20190068992 | Tourapis et al. | Feb 2019 | A1 |
20190089975 | Liu et al. | Mar 2019 | A1 |
20190191167 | Drugeon et al. | Jun 2019 | A1 |
20190200038 | He et al. | Jun 2019 | A1 |
20190208217 | Zhou et al. | Jul 2019 | A1 |
20190215532 | He et al. | Jul 2019 | A1 |
20190238864 | Xiu et al. | Aug 2019 | A1 |
20190246143 | Zhang et al. | Aug 2019 | A1 |
20200007877 | Zhou | Jan 2020 | A1 |
20200036997 | Li et al. | Jan 2020 | A1 |
20200037002 | Xu et al. | Jan 2020 | A1 |
20200045329 | Hashimoto et al. | Feb 2020 | A1 |
20200077087 | He et al. | Mar 2020 | A1 |
20200084454 | Liu et al. | Mar 2020 | A1 |
20200092579 | Zhu et al. | Mar 2020 | A1 |
20200099953 | Xu et al. | Mar 2020 | A1 |
20200137401 | Kim et al. | Apr 2020 | A1 |
20200177900 | Xu et al. | Jun 2020 | A1 |
20200177910 | Li et al. | Jun 2020 | A1 |
20200177911 | Aono et al. | Jun 2020 | A1 |
20200204819 | Hsieh et al. | Jun 2020 | A1 |
20200213608 | Chen et al. | Jul 2020 | A1 |
20200213610 | Kondo | Jul 2020 | A1 |
20200244991 | Li et al. | Jul 2020 | A1 |
20200260072 | Park et al. | Aug 2020 | A1 |
20200396465 | Zhang et al. | Dec 2020 | A1 |
20200404255 | Zhang et al. | Dec 2020 | A1 |
20200404260 | Zhang et al. | Dec 2020 | A1 |
20200413048 | Zhang et al. | Dec 2020 | A1 |
20210021811 | Xu et al. | Jan 2021 | A1 |
20210029373 | Park | Jan 2021 | A1 |
20210120261 | Lim et al. | Apr 2021 | A1 |
20210136405 | Chen et al. | May 2021 | A1 |
20210152833 | Gao et al. | May 2021 | A1 |
20210258598 | Hendry et al. | Aug 2021 | A1 |
20210274201 | Xu et al. | Sep 2021 | A1 |
20210274202 | Xu et al. | Sep 2021 | A1 |
20210297674 | Xu et al. | Sep 2021 | A1 |
20210314560 | Lai et al. | Oct 2021 | A1 |
20210321127 | Zhao et al. | Oct 2021 | A1 |
20210360270 | Xu et al. | Nov 2021 | A1 |
20210368164 | Xu et al. | Nov 2021 | A1 |
20210368178 | Xu et al. | Nov 2021 | A1 |
20210385437 | Xu et al. | Dec 2021 | A1 |
20220132105 | Xu et al. | Apr 2022 | A1 |
20220132106 | Xu et al. | Apr 2022 | A1 |
20220150474 | Xu et al. | May 2022 | A1 |
20220150540 | Xu et al. | May 2022 | A1 |
20220166993 | Xu et al. | May 2022 | A1 |
20220174310 | Xu et al. | Jun 2022 | A1 |
20220210444 | Xu et al. | Jun 2022 | A1 |
20220353494 | Xu et al. | Nov 2022 | A1 |
20230007273 | Gao et al. | Jan 2023 | A1 |
20230019459 | Xu et al. | Jan 2023 | A1 |
Number | Date | Country |
---|---|---|
1589028 | Mar 2005 | CN |
1759610 | Apr 2006 | CN |
102017638 | Apr 2011 | CN |
102595118 | Jul 2012 | CN |
103026706 | Apr 2013 | CN |
105027567 | Nov 2015 | CN |
105393536 | Mar 2016 | CN |
105474645 | Apr 2016 | CN |
105532000 | Apr 2016 | CN |
105556967 | May 2016 | CN |
105659602 | Jun 2016 | CN |
105684409 | Jun 2016 | CN |
105765974 | Jul 2016 | CN |
105847795 | Aug 2016 | CN |
105847843 | Aug 2016 | CN |
105874791 | Aug 2016 | CN |
105874795 | Aug 2016 | CN |
105981382 | Sep 2016 | CN |
106105215 | Nov 2016 | CN |
106415607 | Feb 2017 | CN |
106416243 | Feb 2017 | CN |
106464896 | Feb 2017 | CN |
106464904 | Feb 2017 | CN |
106464921 | Feb 2017 | CN |
106576171 | Apr 2017 | CN |
106576172 | Apr 2017 | CN |
106717004 | May 2017 | CN |
106797466 | May 2017 | CN |
106797475 | May 2017 | CN |
106797476 | May 2017 | CN |
106961609 | Jul 2017 | CN |
107005717 | Aug 2017 | CN |
107018418 | Aug 2017 | CN |
107205149 | Sep 2017 | CN |
107211155 | Sep 2017 | CN |
107409226 | Nov 2017 | CN |
107431819 | Dec 2017 | CN |
107615762 | Jan 2018 | CN |
107615763 | Jan 2018 | CN |
107615765 | Jan 2018 | CN |
107646195 | Jan 2018 | CN |
107683606 | Feb 2018 | CN |
107846597 | Mar 2018 | CN |
107852490 | Mar 2018 | CN |
107852505 | Mar 2018 | CN |
107925769 | Apr 2018 | CN |
107925773 | Apr 2018 | CN |
101198063 | Jun 2018 | CN |
108141605 | Jun 2018 | CN |
108141619 | Jun 2018 | CN |
108632609 | Oct 2018 | CN |
109076210 | Dec 2018 | CN |
109691099 | Apr 2019 | CN |
109792487 | May 2019 | CN |
110495177 | Nov 2019 | CN |
110945871 | Mar 2020 | CN |
3253059 | Dec 2017 | EP |
2882190 | Nov 2018 | EP |
3981148 | Apr 2022 | EP |
3900349 | Aug 2023 | EP |
2533905 | Jul 2016 | GB |
106416250 | Feb 2017 | IN |
201847033775 | Oct 2018 | IN |
4360093 | Nov 2009 | JP |
2016534660 | Nov 2016 | JP |
2016539542 | Dec 2016 | JP |
2017130938 | Jul 2017 | JP |
2017519460 | Jul 2017 | JP |
2017522789 | Aug 2017 | JP |
2017535148 | Nov 2017 | JP |
2017535150 | Nov 2017 | JP |
6324590 | May 2018 | JP |
2018521539 | Aug 2018 | JP |
2018524872 | Aug 2018 | JP |
2020017970 | Jan 2020 | JP |
2021521728 | Aug 2021 | JP |
20160072181 | Jun 2016 | KR |
20170020928 | Feb 2017 | KR |
20170063895 | Jun 2017 | KR |
20190137806 | Dec 2019 | KR |
2587420 | Jun 2016 | RU |
2654129 | May 2018 | RU |
2679566 | Feb 2019 | RU |
2004008772 | Jan 2004 | WO |
2008047316 | Apr 2008 | WO |
2008067734 | Jun 2008 | WO |
2011127964 | Oct 2011 | WO |
2012167713 | Dec 2012 | WO |
2013128010 | Sep 2013 | WO |
2015108793 | Jul 2015 | WO |
2015142854 | Sep 2015 | WO |
2016054985 | Apr 2016 | WO |
2016057208 | Apr 2016 | WO |
2016057701 | Apr 2016 | WO |
2016127889 | Aug 2016 | WO |
2016138854 | Sep 2016 | WO |
2016192594 | Dec 2016 | WO |
2016192677 | Dec 2016 | WO |
2016200043 | Dec 2016 | WO |
2016200984 | Dec 2016 | WO |
2017041692 | Mar 2017 | WO |
2017058633 | Apr 2017 | WO |
2018190207 | Oct 2018 | WO |
2019006300 | Jan 2019 | WO |
2019009590 | Jan 2019 | WO |
2019017694 | Jan 2019 | WO |
2019022843 | Jan 2019 | WO |
2019131778 | Jul 2019 | WO |
2016150343 | Sep 2019 | WO |
2020113156 | Jun 2020 | WO |
2020156540 | Aug 2020 | WO |
2020228744 | Nov 2020 | WO |
2020259677 | Dec 2020 | WO |
2021004495 | Jan 2021 | WO |
Entry |
---|
US 11,412,213 B2, 08/2022, Xu et al. (withdrawn) |
Gao et al. “Bitstram Conformance with a Virtual IBC Buffer Concept,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019, document JVET-O1171, 2019. |
Hannuksela et al. “Versatile Video Coding (Draft 6),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE Jul. 3-12, 2019, document JVET-O2001, 2019. |
Heng et al. “Non-CE8: Comments on Current Picture Referencing,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13th Meeting: Marrakech, MA, Jan. 9-18, 2019, document JVET-M0402, 2019. |
Rapaka et al. “On Storage of Unfiltered and Filtered Current Decoded Pictures,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 22nd Meeting: Geneva, CH, Oct. 15-21, 2015, document JVET-V0050, 2015. |
Xu et al. “Non-CE8: IBC Search Range Increase for Small CTU Size,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 14th Meeting, Geneva, CH, Mar. 19-27, 2019, document JVET-N0384, 2019. |
Xu et al. “An Implementation of JVET-O0568 based on the IBC Buffer Design of JVET-O0127,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019, document JVET-01161, 2019. |
Xu et al. “Bitstram Conformance with a Virtual IBC Buffer Concept,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019, document JVET-O1170, 2019. |
Extended European Search Report from European Patent Application No. 20747609.4 dated May 11, 2022 (10 pages). |
Extended European Search Report from European Patent Application No. 20748900.6 dated May 11, 2022 (10 pages). |
Extended European Search Report from European Patent Application No. 20765739.6 dated May 19, 2022 (7 pages). |
Extended European Search Report from European Patent Application No. 20836430.7 dated Jul. 22, 2022 (12 pages). |
Extended European Search Report from European Patent Application No. 20837885.1 dated Jul. 7, 2022 (15 pages). |
Extended European Search Report from European Patent Application No. 20837744.0 dated Jul. 5, 2022 (12 pages). |
Notice of Allowance from U.S. Appl. No. 17/362,341 dated Jul. 7, 2022. |
Pham Van et al. “CE8.1.3: Extended CPR Reference with 1 Buffer Line,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13th Meeting, Marrakech, MA, Jan. 9-18, 2018, document JVET-M0474, 2018. |
Non Final Office Action from U.S. Appl. No. 17/978,263 dated Mar. 10, 2023. |
Chen et al. “CE9-related: BDOF Buffer Reduction and Enabling VPDU Based Application,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13th Meeting: Marrakech, MA, Jan. 9-18, 2019, document JVET-M0890, 2019. |
Tsai et al. “CE1-related: Picture Boundary CU Split Satisfying the VPDU Constraint,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13th Meeting: Marrakech, MA, Jan. 9-18, 2019, document JVET-M0888, 2019. |
Final Office Action from U.S. Appl. No. 17/320,033 dated Nov. 5, 2021. |
Final Office Action from U.S. Appl. No. 17/319,994 dated Nov. 16, 2021. |
Non Final Office Action from U.S. Appl. No. 17/362,341 dated Nov. 19, 2021. |
Non Final Office Action from U.S. Appl. No. 17/384,246 dated Nov. 26, 2021. |
Bross et al. “Versatile Video Coding (Draft 3),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC ITC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L1001, 2018. |
Bross et al. “Versatile Video Coding (Draft 4),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC ITC 1/SC 29/WG 11, 13th Meeting, Marrakech, MA, Jan. 9-18, 2019, document JVET-M1001, 2019. |
Bross et al. “Versatile Video Coding (Draft 5),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019, document JVET-N1001, 2019. |
Budagavi et al. “AHG8: Video-Coding Using Intra Motion Compensation,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 13th Meeting, Incheon, KR, Apr. 18-26, 2013, document JCTVC-M0350, 2013. |
Chen et al. “Algorithm Description of Joint Exploration Test Model 7 (JEM 7),” Joint Video Exploration Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 7th Meeting: Torino, IT, Jul. 13-21, 2017, document JVET-G1001, 2017. |
Chen et al.CE4: Affine Merge Enhancement with Simplification (Test 4.2.2), Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L0368, 2018. |
Chen et al. “CE4: Separate List for Sub-Block Merge Candidates (Test 4.2.8),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L0369, 2018. |
Gao et al. “CE8-Related: Dedicated IBC Reference Buffer without Bitstream Restrictions,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019, document JVET-00248, 2019. |
Hendry et al. “APS Partial Update—APS Buffer Management,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 9th Meeting, Geneva, CH, Apr. 27-May 7, 2012, document JCTVC-I0082, 2012. |
“Information Technology—High Efficiency Coding and Media Delivery in Heterogeneous Environments—Part 2: High Efficiency Video Coding” Apr. 20, 2018, ISO/DIS 23008, 4th Edition. |
Li et al. “CE8-Related: IBC Modifications,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Gothenburg, SE, Jul. 3-12, 2019, document JVET-00127, 2019. |
Liao et al. “CE10.3.1.b: Triangular Prediction Unit Mode,” Joint Video Exploration Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L0124, 2018. |
Lu et al. “CE12: Mapping Functions (Test CE12-1 and CE12-2),” Joint Video Experts Team (JVET) of ITU-t SG 16 WP B and ISO/IEC JTC 1/SC 29/WG 11, 13th Meeting, Marrakech, MA, Jan. 9-18, 2019, document JVET-M0427, 2019. |
Nam et al. “Non-CE8: Block Vector Predictor for IBC,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 12th Meeting, Macau, CN, Oct. 8-12, 2018, document JVET-L0159, 2018. |
Pang et al. “Intra Block Copy with Larger Search Region,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 17th Meeting, Valencia, ES, Mar. 27-Apr. 4, 2014, document JCTVC-Q0139, 2014. |
Pang et al. “SCCE1: Test 1.1—Intra Block Copy with Different Areas,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC1/SC29/WG11 18th Meeting, Sapporo, JP, Jun. 30-Jul. 9, 2014, document JCTVC-R0184, 2014. |
Rosewarne et al. “High Efficiency Video Coding (HEVC) Test Model 16 (HM 16) Improved Encoder Description Update 7,” Joint Collaborative Team on Video Coding (JCT-VC) ITU-T SG 16 WP3 and ISO/IEC JTC1/SC29/WG11, 25th Meeting, Chengdu, CN, Oct. 14-21, 2019, document JCTVC-Y1002, 2016. |
Sole et al. “HEVC Screen Content Coding Core Experiment 1 (SCCE1): Intra Block Copying Extensions,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC1/SC29/WG11 17th Meeting, Valencia, ES Mar. 27-Apr. 4, 2014 , document JCTVC-Q1121, 2014. |
Venugopal et al. “Cross Check of JVET-L0297 (CE8-Related: CPR Mode with Local Search Range Optimization),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L0518, 2018. |
Xu et al. “CE8: CPR Reference Memory Reuse Without Increasing Memory Requirement (CE8.1.2a and CE8.1.2d),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13 Meeting, Marrakesh, MA, Jan. 9-18, 2019, document JVET-M0407, 2019. |
Xu et al. “CE8: CPR Reference Memory Reuse Without Reduced Memory Requirement (CE8.1.2b and CE8.1.2c),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 13 Meeting, Marrakesh, MA, Jan. 9-18, 2019, document JVET-M0408. |
Xu et al. “Non-CE8: Reference Memory Reduction for Intra Block Copy,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019, document JVET-N0250, 2019. |
Xu et al. “Non-CE8: Intra Block Copy Clean-Up,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019, document JVET-N0251, 2019. |
Xu et al. “Non-CE8: IBC Search Range Adjustment for Implementation Consideration,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 14th Meeting, Geneva, CH, Mar. 19-27, 2019, document JVET-N0383, 2019. |
Xu et al. “Non-CE8: On IBC Reference Buffer Design,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 14th Meeting, Geneva, CH, Mar. 19-27, 2019, document JVET-N0472, 2019. |
Yang et al. “CE:4 Summary Report on Inter Prediction and Motion Vector Coding,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting: Macao, CN, Oct. 3-12, 2018, document JVET-L0024, 2018. |
Zhang et al. “Symmetric Intra Block Copy,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 17th Meeting, Valencia, ES, Mar. 27-Apr. 4, 2014, document JCTVC-Q0082, 2014. |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074155 dated Apr. 21, 2020 (11 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074156 dated Apr. 22, 2020 (10 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074159 dated Apr. 22, 2020 (9 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074160 dated Apr. 23, 2020 (10 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074161 dated Apr. 28, 2020 (11 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074162 dated Apr. 28, 2020 (8 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074163 dated Apr. 22, 2020 (11 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/074164 dated Apr. 29, 2020 (8 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/077415 dated Apr. 26, 2020 (9 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/077416 dated May 27, 2020 (10 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/077417 dated May 27, 2020 (9 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/077418 dated May 28, 2020 (9 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/098471 dated Oct. 10, 2020 (10 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/099702 dated Aug. 27, 2020 (9 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/100992 dated Sep. 28, 2020 (10 pages). |
International Search Report and Written Opinion from International Patent Application No. PCT/CN2020/100998 dated Oct. 12, 2020 (9 pages). |
Non Final Office Action from U.S. Appl. No. 17/320,008 dated Juy 12, 2021. |
Non Final Office Action from U.S. Appl. No. 17/319,994 dated Juy 26, 2021. |
Non Final Office Action from U.S. Appl. No. 17/320,033 dated Juy 27, 2021. |
Alshin et al. “RCE3: Intra Block Copy Search Range (Tests A),” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 1116th Meeting: San Jose, US, Jan. 9-17, 2014, document ICTVC-P0211, 2014. |
Hannuksela et al. “AHG12: single_slice_per_subpic_flag,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 16th Meeting: Geneva, CH, Oct. 1-11, 2019, document JVET-P1024, 2019. |
Li et al. “On Intra BC Mode,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC ITC 1/SC 29/WG 11 15th Meeting: Geneva, CH, Oct. 23-Nov. 1, 2013, document JCTVC-00183, 2013. |
Wang et al. “SCCE1: Result of Test 1.2 for IBC with Constrained Buffers from Left CTUs,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 18th Meeting: Sapporo, JP, Jun. 30-Jul. 9, 2014, document JCTVC-R0141, 2014. |
Xu et al. “Description of Core Experiment 8: Screen Content Coding Tools,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L1028, 2018. |
Xu et al. “CE8: Summary Report on Screen Content Coding,” Joint Video Experts Team (JVET)of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 1113th Meeting: Marrakesh, MA, Jan. 9-18, 2019, document JVET-M0028, 2019. |
Extended European Search Report from European Patent Application No. 20748417.1 dated Oct. 25, 2022 (11 pages). |
Chen et al. “Algorithm Description for Versatlie Video Coding and Test Model 3 (VTM 3),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L1002, 2018. |
Chen et al. “Algorithm Description for Versatlie Video Coding and Test Model 4 (VTM 4),” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 13th Meeting, Marrakech, MA Jan. 9-18, 2019, document JVET-M1002, 2019. |
Flynn et al. “BoG Report on Range Extensions Topics,” Joint Collaborative Team on Video Coding (JCT-VC) on ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 15th Meeting, Geneva, CH, Oct. 23-Nov. 1, 2013, document JCTVC-00352, 2013. |
Van et al. “CE8-Related: Restrictions for the Search Area of the IBC Blocks in CPR,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting: Macao, CN, Oct. 3-12, 208, document JVET-L0404, 2018. |
Xu et al. “Intra Block Copy in HEVC Screen Content Coding Extensions,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Dec. 2016, 6(4):409-419, XP011636923. |
Xu et al. “CE8-Related: CPR Mode with Local Search Range Optimization,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. 3-12, 2018, document JVET-L0297, 2018. |
“Encoder Decoder + Intra Block Copy + Buffer or Reference Buffer+ Bit Depth or Bit-Depth” Google Search, Mar. 22, 2022. |
“Intra Block Copy” Library USTPO Query for NPL, Mar. 22, 2022. |
Extended European Search Report from European Patent Application No. 20766750.2 dated Feb. 18, 2022 (21 pages). |
Non Final Office Action from U.S. Appl. No. 17/570,723 dated Mar. 25, 2022. |
Non Final Office Action from U.S. Appl. No. 17/570,753 dated Mar. 31, 2022. |
Non Final Office Action from U.S. Appl. No. 17/569,390 dated Apr. 1, 2022. |
“High Efficiency Video Coding,” ITU-T Telecommunication Standardization Sector of ITU, Series H: Audiovisual and Multimedia Systems, Infrastructure of Audiovisual Services—Coding of Moving Video, H.265, Apr. 2013. |
Huang et al. “Fast Intra Prediction for HEVC Screen Content,” Journal of Optoelectronics—Laser, Jun. 2018, 29 (6):604-609. |
Joshi et al. “High Efficiency Video Coding (HEVC) Screen Content Coding: Draft 6.” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 23rd Meeting: San Diego, USA, Feb. 19-26, 2016, document JCTVC-W1005, 2016. |
Rosewarne et al. “HEVC Range Extensions Test Model 6 Encoder Description,” Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11 16th Meeting: San José, US, Jan. 9-17, 2014, document JCTVC-P1013, 2014. |
Zuo et al. “Intra Block Copy for Intra-Frame Coding,” Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 10th Meeting: San Diego, US, Apr. 10-20, 2018, document JVET-J0042, 2018. |
Office Action from Canadian Patent Application No. 3127848 dated Jun. 29, 2023 (5 pages). |
Office Action from Canadian Patent Application No. 3146391 dated Jun. 27, 2023 (5 pages). |
Non Final Office Action from U.S. Appl. No. 17/386,430 dated Sep. 7, 2023. |
Non Final Office Action from U.S. Appl. No. 17/571,748 dated Sep. 14, 2023. |
Non Final Office Action from U.S. Appl. No. 17/461,150 dated Sep. 15, 2023. |
Non Final Office Action from U.S. Appl. No. 17/896,761 dated Aug. 4, 2023. |
Non Final Office Action from U.S. Appl. No. 17/386,519 dated Oct. 5, 2023. |
Final Office Action from U.S. Appl. No. 17/571,748 dated Jan. 11, 2024. |
Non Final Office Action from U.S. Appl. No. 17/386,510 dated Jan. 16, 2024. |
Final Office Action from U.S. Appl. No. 17/386,430 dated Feb. 22, 2024. |
Non Final Office Action from U.S. Appl. No. 18/076,031 dated Feb. 26, 2024. |
Office Action from Chinese Patent Application No. 202080011726.9 mailed Apr. 4, 2024. |
Notice of Reasons for Refusal from Japanese Patent Application No. 2023-082519 mailed Jun. 18, 2024. |
Number | Date | Country | |
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20210352279 A1 | Nov 2021 | US |
Number | Date | Country | |
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Parent | PCT/CN2020/074160 | Feb 2020 | WO |
Child | 17386403 | US |