BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a schematic diagram of a basic prior art DC-to-DC boost converter circuit.
FIG. 1B is a timing diagram illustrates the inductor current IL in FIG. 1A under both heavy load and light load conditions.
FIG. 2A is a schematic diagram of a prior art synchronous DC-to-DC boost converter circuit.
FIG. 2B is a timing diagram illustrates the inductor current IL in FIG. 2A under both heavy load and light load conditions.
FIG. 3 is a schematic diagram of another prior art synchronous DC-to-DC boost converter circuit which operates to turn off a P-channel output power transistor if the direction of the inductor current is reversed.
FIG. 4A is a schematic diagram of a synchronous DC-to-DC boost converter circuit according to the present invention.
FIG. 4B is a schematic diagram of a predictive duty cycle ratio generating circuit which can be used in block 2 of FIG. 4A.
FIG. 4C is a timing diagram showing the waveforms of various signals in the circuits of FIGS. 4A and 4B.
FIG. 5 is a diagram illustrating the inductor current cycle in the circuit of FIG. 4A.
FIG. 6 is a detailed block diagram of an implementation of the predictive duty cycle control circuit in block 2FIG. 4A.
FIG. 7A is a block diagram of an improved ramp voltage generator circuit which can be used instead of the circuitry in block 19A of FIG. 6 to synchronize operation of the predictive duty cycle controller with an external clock signal.
FIG. 7B is a timing diagram of waveforms of various signals in the circuit of FIG. 7A.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 4A, synchronous DC-to-DC boost converter 10 (referred to as “boost converter 10”) includes a predictive duty cycle controller 2 which receives Vin as an input voltage, Vref as a reference voltage, a feedback control signal VFB on conductor 9, and either an internal or external clock signal. An output VGN of predictive duty cycle controller 2 is coupled by conductor 8A to the gate of N-channel output power transistor 3, the source of which is connected to ground. The drain of transistor 3 is connected by conductor 4 to one terminal of an external (off-chip) inductor L (which, for example, may have and inductance value from 1 to 10 μH), the other terminal of which is connected by conductor 5 to an input circuit or device (not shown) that produces the input voltage Vin. A current IL flows through inductor L. Conductor 4 is also connected to the drain of P-channel output power transistor 4, the source of which is connected by conductor 7 to provide the output voltage Vout. Conductor 7 is coupled to ground by an external capacitor C (which, for example, may have a capacitance of 10 to 20 μF), and also is coupled to one terminal of resistor R1, the other terminal of which is connected by conductor 9 to one terminal of resistor R2. The other terminal of resistor R2 is connected to ground, so that resistors R1 and R2 form a voltage divider that generates feedback signal VFB as a scaled-down representation of the boosted output voltage Vout.
The gate of power output transistor 11 is connected by conductor 8B to receive another output VGP of predictive duty cycle controller 2, produced in response to Vin, Vref, and VFB. Predictive duty cycle controller 2 can be implemented by means of the circuitry shown in subsequently described FIG. 6.
Predictive duty cycle controller 2 determines the transition point (41 in FIG. 5) at which the ramp-up inductor current IL abruptly becomes a ramp-down current. (This is in contrast to the prior art, which directly controls the turn-off point (point 40 in FIG. 5) of P-channel transistor 11 in response to detecting of when the direction of inductor current IL is reversed.) A predictive duty ratio generator circuit is included in predictive duty cycle controller 2 to enable it to determine the transition point 41.
Referring to FIG. 4B, predictive duty ratio generation circuit 20C includes a resistor 21 of resistance R3 having one terminal connected to receive Vin and a second terminal connected to a first terminal of a resistor 22 having a resistance R4. A second terminal of resistor 22 is connected by conductor 23 to the (−) input of an operational amplifier 25 and also to one terminal of a feedback resistor 24 having a resistance R4. A second terminal of feedback resistor 24 is connected by conductor 26 to the output of operational amplifier 25. A resistor 27 of resistance R4 is coupled to reference voltage Vref, and a second terminal of resistor 27 is connected by conductor 28 to the (+) input of operational amplifier 25, and also is coupled to ground through series-coupled resistors 29 and 30 of resistances R4 and R3, respectively. The output 26 of operational amplifier 25 produces a duty ratio signal VM on the (−) input of comparator 31, which can be a relatively simple, inexpensive circuit.
The (+) input of comparator 31 in FIG. 4B is coupled by conductor 32 to receive a ramp signal VRAMP, which can be generated by, for example, either the ramp generator circuit 19B shown in FIG. 6 or the externally clocked ramp generator circuit 19B shown in FIG. 7. The height of the ramp voltage is designed to be Vref, and the width of the ramp voltage corresponds to the clock signal. The ratio of resistance R3 to resistance R4 should be chosen to match the ratio of resistance R1 to resistance R2. Comparator 31 produces the switch control signal VSW which is applied by means of conductor 33 to the input of a non-overlapping buffer circuit 57 in FIG. 6 which produces non-overlapping gate control signals VGN and VGP, as shown in FIG. 4C on conductors 8A and 8B, respectively, (which as previously mentioned, are connected to the gates of N-channel power transistor 3 and P-channel output power transistor 11, respectively).
As shown in the timing diagram of FIG. 4C, the beginning of each switching cycle of transistors 3 and 11 is the time at which N-channel output power transistor 3 is turned on to start the ramp-up or build-up of inductor current IL. That occurs at the beginning of the ramp-up of VRAMP. N-channel transistor 3 is switched off and P-channel transistor 11 is switched on at the instant at which VRAMP crosses the value of duty ratio control voltage VM produced by duty ratio circuit 20C of FIG. 4B. At the end of the period of an internal clock signal CLKINT (produced on conductor 47 in FIG. 6), inductor current IL will have ramped back down to approximately its initial value, i.e. to zero. The value of duty ratio control voltage VM controls the predictive duty cycle of the switch control signal VSW on conductor 33 so as to ensure that the inductor current IL decays to zero at precisely the instant that synchronous switching transistor 11 is turned off. VM as a percentage of Vref by design corresponds to the duty ratio of a lossless boost converter operating in PWM mode. Those skilled in the art will understand that this particular relationship ensures that the inductor current decays to zero at the end of each cycle.
In accordance with the present invention, synchronous DC-to-DC boost converter 10 of FIG. 4A sets the subsequently described predictive duty cycle of VSW produced on conductor 33 in FIG. 4B to an optimal fixed “duty ratio” based upon its input/output voltage relationship, rather than by controlling the precise turn-off times of power output transistor 11. The duty ratio coincides with the an ideal predictive duty cycle ratio of a lossless boost converter (with fixed Vout), in order to ensure that the inductor current IL at the end of each switching cycle (i.e., each cycle of CLKINT) will be same as at the beginning of the switching cycle.
The duty ratio in a boost converter is D=(Vout−Vin)/Vout. If the system is operating in PFM (pulse-frequency-modulation) mode where the starting value of inductor current IL in each ramp-up, ramp-down cycle is designed to be zero, then at the end of each cycle of internal clock CLKINT the values of the inductor current IL should return to approximately zero. That eliminates the need for a high speed, high precision comparator. The duty ratio D=(Vout−in)/Vout is relatively accurate since in PFM mode the load current is small and the IR loss is relatively small.
In the design of predictive duty ratio generation circuit 20C shown in FIG. 4B, the output voltage Vout is fixed. That allows the duty ratio generation to be achieved by means of resistive divider R1 and R2 as shown in FIG. 4B, the output of which produces a duty ratio control voltage VM on the (−) input of comparator 31, such that
V
M
=Vref−Vin×R4/(R3+R4).
VM is compared by comparator 31 to ramp voltage VRAMP, which is applied to the (+) input of comparator 31 of ramp generator circuit 19B in FIG. 7. The amplitude of VRAMP is set to the value of the reference voltage Vref by the circuitry shown in FIG. 7, and the width of VRAMP is set by the duration of one period of the clock signal CLKINT. Consequently, the duty ratio D produced is
D=V
M
/Vref=1×Vin×R4/{Vref×(R3+R4)},
wherein the resistances of resistors R1, R2, R3, and R4 are selected such that R3/R4=R1/R2.
Since Vout is equal to Vref×(R1+R2)/R2, it follows that the duty ratio D is given by
D=1−Vin/Vout=(Vout−Vin)/Vout.
If inductor current IL starts at zero (which often is the case in PFM mode operation wherein the load current demand is relatively low), the losses through transistors 3 and 11 are small enough that the predictive duty ratio very accurately predicts/determines both the slope of the inductor current IL at the beginning of the CLKINT cycle of the inductor current IL and the duration of the inductor current IL in the CLKINT cycle.
The duty ratio D defined by the foregoing expression causes inductor current IL to be approximately zero at the end of each cycle. Delay in comparator 31 tends to raise the generated duty ratio D slightly higher than the ideal value. As long as the delay of comparator 31 is only a small fraction of the CLKINT cycle, which is typically the case, the impact of the delay in comparator 31 is minimal and is substantially less than the impact of comparator delay that occurs when using the prior art technique of individually controlling the turn-off times of output power transistor 11 in response to detecting of a direction reversal of inductor current IL. Also, the effect of the input offset voltage of comparator 31 in FIG. 4B therefore is substantially less than the effect of the input offset voltage of comparator 12 in FIG. 3 using the prior art technique of controlling turn-on and turn-off times of output power transistor 11. The implementation of comparator 31 in FIG. 4B is much easier than the implementation required for comparator 12 in the prior art circuit shown in FIG. 3.
Thus, the present invention is focused on predicting/determining the optimal time to switch from N-channel transistor 3 being conductive to P-channel transistor 11 being conductive, whereas the prior art is focused on attempting to determine the individual times at which to turn P-channel transistor 11 off on the basis of detecting the direction of the inductor current IL.
Referring to FIG. 5, the present invention predicts/determines the optimum time of transition point 41 between up-ramping and down-ramping of IL , as represented by vertical dashed line 36, such that the falling ramp 38 of inductor current IL causes P-channel transistor 11 to be turned off at precisely the time IL has decayed to zero. Stated differently, duty cycle D is optimally determined by the circuitry in FIG. 4B such that the ramp-up and ramp-down of inductor current IL has the waveform shown in FIG. 5. This provides the advantage that the component requirements for producing the delay times and the offset voltages are less stringent than is the case for the prior art. To allow inductor current IL to completely ramp down to zero as shown in FIG. 5 before starting the next switching cycle, each ramp-up, ramp-down cycle (i.e., charge pumping cycle) during the PFM mode operation is always followed by an “idle” time (i.e., no-charge-pumping time), to avoid false operation. The circuits of FIGS. 4A and 4B result in the build-up or ramp-up 35 of inductor current IL in FIG. 5 during the fraction D of each switching cycle, and also result in the ramp-down 38 of IL occurs during the fraction 1−D of the switching cycle, because when N-channel transistor 3 is on, the inductor current build-up or ramp-up rate is equal to Vin/L, and the inductor current decay or ramp-down rate is set by Vout-Vin/L. Assuming steady state conditions, the value of inductor current IL ends up at the same value as the value at which it begins in the ramp-up/ramp-down cycle. By equating Vin/L×D to (Vout−Vin)/×*(1−D), the expression D=1-Vin/Vout can be readily derived.
Stated differently, the duty ratio control voltage VM has a value that corresponds to a duty ratio D of a ramp-up, ramp-down cycle of inductor current IL wherein the duty ratio D is the fraction of the period of the ramp-up, ramp-down cycle during which N-channel transistor 3 is on and 1−D is the fraction of the period of the ramp-up, ramp-down cycle during which P-channel transistor 11 is on, wherein the duty ratio D is represented by the simultaneous equations D=1−Vin/Vout and D=Vin/Vref.
Briefly, in PFM (pulse-frequency modulation) mode, synchronous DC-to-DC boost converter operates to cause IL to ramp up no more frequently than every other internal clock cycle. The reason for the pause or idle time in IL down-ramping operation during one or more successive internal clock cycles is to ensure that inductor current IL has completely ramped down to zero before beginning a new ramping cycle. This is desirable because a small negative value of IL would result in an undesirable increasing amount of reverse inductor current back-flowing into the source of the input voltage Vin if the ramping operation were to continue. (However, conventional PWM circuitry (not shown) can also be provided in boost converter 10 to accommodate the case wherein load current demand increases beyond the level that can be supplied by the above described IL ramping (i.e., charge pumping) every other clock cycle in PFM mode operation. (Operation of boost converter 10 can be automatically switched from PFM (pulse-frequency modulation) operation to ordinary PWM (pulse width modulation) operation in the presence of heavy load current demand using conventional techniques wherein IL ramping (charge pumping) occurs every internal CLKINT clock cycle and wherein the duty cycle of the IL ramping up/down time is continuously adjusted according to the load current demand. Note that under high load current demand conditions the minimum value Of IL is sufficiently high that there is no problem with IL direction reversal.)
More specifically, and referring to FIG. 6, predictive duty cycle controller 2 of FIG. 4A includes a PFM regulating circuit 62 which receives feedback voltage VFB on conductor 9 and an internal clock signal CLKINT on conductor 47 and generates a regulating or controlling signal DISABLE on conductor 61. The signal DISABLE is applied to a disable or control input of a conventional non-overlapping buffer circuit 57 which produces the non-overlapping gate control signals VGN and VGP on conductors 8A and 8B, respectively. Regulating circuit 62 includes a comparator 59 having its (+) input coupled to receive feedback signal VFB and its (−) input coupled to receive Vref. The output of comparator 59 is connected to one input of an OR gate 60 having its output connected to the input of a D-type flip-flop 56. The clock input of flip-flop 56 is connected to internal clock signal CLKINT and its output is connected by conductor 61 to produce the signal DISABLE on the input of an inverter 58, the output of which is connected to the other input of OR gate 59 (or other circuit which performs a logical OR'ing function).
Comparator 59 in FIG. 6 compares feedback voltage VFB which is scaled down from the value of Vout to the value of Vref, with the result that if VFB greater than Vref (meaning that Vout is a bit too high), then regulating circuit 62 will go into its pause or idle time or mode during which no more charge will be pumped to be eventually delivered by boost converter 10 to load 15. However, if Vout is less than desired, regulating circuit 62 will be activated to produce charge delivering operation (provided that the prior cycle was an idle cycle), and in the next clock cycle regulating circuit 62 will begin an idle condition and remain therein until VFB no longer exceeds Vref. This is what is meant by PFM (pulse frequency modulation) mode. Thus, in the PFM mode, when there is a low demand for load current, boost converter 10 delivers charge to the load somewhat sporadically, i.e., only as needed to maintain Vout equal to Vref (For example, boost converter 10 may pump charge during one internal clock cycle and then be in its idle state for the next 10 cycles.) As demand for load current increases, the relative number of IL ramping or charge pumping cycles increases and the number of idle cycles correspondingly decreases.
Predictive duty cycle controller 2 as shown in FIG. 6 includes predictive duty ratio generation circuit 20C of FIG. 4B, having its output on conductor 33 connected to apply the switch control signal VSW to an input of non-overlapping buffer 57, causing it to generate VGP and VGN as shown in the timing diagram of FIG. 4C.
Predictive duty cycle controller 2 as shown in FIG. 6 also includes a ramp generator 19A, wherein a constant current source 42 is used to linearly charge a capacitor 43. When the voltage on conductor 32 reaches the value of reference voltage Vref, comparator 44 is triggered to turn on RS latch 46, which generates the internal clock signal CLKINT on conductor 47 to reset capacitor 43 and also to clock flip-flop 56. The frequency of CLKINT is determined by the capacitance of capacitor 43, the value of Vref, and the magnitude of the current source 42 in FIG. 6 (or current mirror output transistor 42A in FIG. 7A).
Thus, the present invention in effect “predicts” when P-channel transistor 11 should be turned off and N channel transistor 3 should be turned on, and does not use the prior art technique of determining directly when the inductor current IL reverses direction in order to determine when to turn off P-channel transistor 11.
If an external clock CLKEXT is to be used, one can simply use an edge of the external clock to reset capacitor 43 to slave the internal ramp generation to the external clock. However, because of typical semiconductor process variations, or if the external clock signal is intentionally skewed, a problem with ramp generator 19A in FIG. 6 is that the magnitude of VRAMP on conductor 33 does not always reach the same value as Vref at the end of each internal CLKINT cycle. If that happens, it upsets the above described the duty ratio prediction/generation scheme, as can be recognized from the above described derivation of predictive duty cycle D. (For example, if the capacitance of capacitor 43 is too small, then VRAMP reaches and may exceed Vref. Or, for example, if an internal oscillator is running at, for example, 800 kHz, and CLKEXT is running at 1 MHz, then VRAMP would rise only to a value less than Vref because of the reduced available amount of ramping time. Or, if CLKEXT runs at 600 kHz, then there is a longer amount of available ramping time which will result in VRRAMP reaching the value of Vref.)
Most synchronous DC-to-DC boost converters provide an option for running an external clock (e.g., CLKEXT in FIG. 7 A) to synchronize the boost converter with respect to an external system (not shown), or perhaps to establish a desired operating frequency of the boost converter. In such cases, care needs to be taken to ensure that the magnitude of the ramp voltage (e.g., VRAMP) always reaches the same value (i.e., Vref) as in the case wherein only an internal clock (e.g., CLKINT in FIG. 6) is used.
A solution to the above mentioned problems of ramp generator 19A in FIG. 6 is provided by the ramp generator 19B of FIG. 7. This solution is accomplished by using a phase locked loop (PLL) to derive an output current to charge capacitor 43 to generate VRAMP with a maximum voltage or height equal to the value of Vref. In FIG. 7, ramp generator 19B includes the same basic ramp voltage generating circuitry as FIG. 6, including capacitor 43, comparator 44, transistor 45, latch 46, and delay circuit 48. P-channel transistor 42A in FIG. 7 is a current mirror output transistor that performs the same function as current source 42 in FIG. 6. However, the drain of current mirror output transistor 42A is connected by conductor 32 so as to linearly charge one terminal of capacitor 43 to produce the rising edges of VRAMP.
The other terminal of capacitor 43 is connected to a fixed reference, such as ground. Conductor 32 also is connected to the drain of a N-channel reset transistor 45, the source of which is connected to ground, and also to the (−) input of comparator 44, the (+) terminal of which is connected to Vref The output of comparator 44 is connected to the set input of RS latch 46, the output of which is connected by conductor 47 to the gate of reset transistor 45 and to one input of delay circuit 48. The output of delay circuit 48 is connected by conductor 49 to the reset input of flip-flop 46 and to a reset input of phase-frequency detector (PFD) circuit 50. When VRAMP is equal to Vref, comparator 44 switches flip-flop 46, causing reset transistor 45 to discharge capacitor 43 so as to produce the falling edges of VRAMP. Delay circuit 48 allows discharge transistor 45 to be turned on long enough to completely discharge capacitor 43. This also allows a minimum width of output pulse of RS latch 46, wherein the delay circuit 48 sets the width of the CLKINT pulses shown in the timing diagram of FIG. 7B, and also allows the output of comparator 44 to deactivate (meaning to undergo a transition from a high to a low output level) before the delayed pulse produced by delay circuit 48 on conductor 49 arrives at the reset (R) input of latch 46, so as to avoid unintended signal glitches.
The clock input 51 of PFD (phase-frequency detector) circuit 50 is connected to receive the external clock signal CLKEXT. The output of PFD circuit 50, which is a conventional phase frequency detector for use in a phase locked loop, is connected to the input of a conventional charge-pump-based loop filter 49, the output of which is connected to the gate and drain of a P-channel current mirror input transistor 44 and to the gate of current mirror output transistor 42A.
The phase of the pulse edge of the signal V49 produced at the output 49 of delay circuit 48 is compared to the phase of external clock CLKEXT by phase-frequency detector 50, the output of which is input to charge-Palm-based loop filter 49. Loop filter 49 then controls current mirror input transistor 44 to generate the output current in current mirror output transistor 42A. The derived signal V49 at the output of delay circuit 48 is phase and frequency locked to external clock CLKEXT. Therefore, phase locked loop 48 maintains the peak value of CLKEXT constant at Vref despite typical semiconductor process variations. Therefore, the latch output signal CLKINT is also phase and frequency locked with respect to external clock signal CLKEXT, but is skewed in phase with respect to internal signal V49 by the amount of delay produced in delay circuit 48. This is shown in the tuning diagram of FIG. 7B. Comparing the delay clock on conductor 49 with the external clock CLKINT effectively avoids the possibility of a “dead zone” during which the pulses of internal clock signal CLKINT turn on N-channel transistor 45 to discharge capacitor 43. During such a dead zone, current supplied by the phase locked loop circuitry 48 and current mirror output transistor 42A would have very little effect on VRAMP. Delay circuit 48 shifts the comparison of VRAMP with Vref by comparator 44 away from the dead zone.
Thus, the present invention in effect predicts/generates the turn-on time of the power output transistor 11 so at the end of each CLKINT cycle the inductor current IL has ramped down to zero, in contrast to the prior art technique of controlling the turn-off time of the synchronous switch by utilizing a fast and precise comparator. This eliminates the need for a costly high speed precision comparator.
While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention.
Patent Application
20080094861
