Printed wiring board with radiator and feed circuit

Information

  • Patent Grant
  • 11088467
  • Patent Number
    11,088,467
  • Date Filed
    Thursday, December 15, 2016
    7 years ago
  • Date Issued
    Tuesday, August 10, 2021
    2 years ago
Abstract
In one aspect, a unit cell of a phased array antenna includes a printed wiring board (PWB). The PWB includes a first layer comprising a radiator, a second layer comprising a feed circuit configured to provide excitation signals to the radiator, a plurality of vias connecting the feed circuit to the radiator, a signal layer, an active component layer comprising an active component bonded to the signal layer and a radio frequency (RF) connector connecting the signal layer to the feed circuit.
Description
BACKGROUND

Performance of an array antenna is often limited by the size and bandwidth limitations of the antenna elements which make up the array. Improving the bandwidth while maintaining a low profile enables array system performance to meet bandwidth and scan requirements of next generation of communication applications, such as software defined or cognitive radio. These applications also frequently require antenna elements that can support either dual linear or circular polarizations.


SUMMARY

In one aspect, a unit cell of a phased array antenna includes a printed wiring board (PWB). The PWB includes a first layer comprising a radiator, a second layer comprising a feed circuit configured to provide excitation signals to the radiator, a plurality of vias connecting the feed circuit to the radiator, a signal layer, an active component layer comprising an active component bonded to the signal layer and a radio frequency (RF) connector connecting the signal layer to the feed circuit.


In another aspect, a unit cell of a phased array antenna includes a printed wiring board (PWB). The PWB includes a first layer comprising a radiator that includes a first dipole arm, a second dipole arm, a third dipole arm and a fourth dipole arm. The PWB also includes a second layer that includes a quadrature feed circuit configured to provide excitation signals to the radiator using right hand circular polarization (RHCP). The PWB further includes a first via coupled to the first dipole arm, a second via coupled to the second dipole arm, a third via coupled to the third dipole arm, a fourth via coupled to the fourth dipole arm, wherein the first, second, third and fourth vias provide the excitation signal from the feed circuit, a fifth via coupled to the first dipole arm, a sixth via coupled to the second dipole arm, a seventh via coupled to the third dipole arm and an eighth via coupled to the fourth dipole arm, wherein the fifth, sixth, seventh and eighth vias provide ground. The PWB still further includes a third layer between the first and second layers, wherein the third layer comprises a dielectric having four rounded corners evenly spaced around the dialectic.


In a further aspect, a unit cell of a phased array antenna includes a first means for providing a radiated signal, a second means for generating excitation signals and a third means for providing the excitation signals from the second means to the first means.





DESCRIPTION OF THE DRAWINGS


FIG. 1A is a diagram of an example of a phased antenna array.



FIG. 1B is a diagram of an example of a unit cell of the phased array antenna.



FIG. 2A is a diagram of an example, of a side view of the unit cell of FIG. 1B.



FIG. 2B is a diagram of an example of a bottom view of the unit cell of FIG. 1B.



FIG. 2C is a diagram of an example of a top view of the unit cell of FIG. 1B.



FIG. 3 is a detailed diagram of an example of layers around a feed layer of FIG. 2A.



FIG. 4 is a diagram of a bottom view of one example of a backdrill and a corresponding via.



FIG. 5 is a diagram of an example of a printed wiring board (PWB).



FIG. 6A is a diagram of an example of realized gain versus angle for a patch radiator.



FIG. 6B is a diagram of an example of realized gain versus angle for a current loop radiator.



FIG. 7A is a diagram of an example of axial ratio versus angle for the patch radiator.



FIG. 7B is a diagram of an example of axial ratio versus angle for a current loop radiator.



FIG. 8 is a diagram of another example of a feed circuit.





DETAIL DESCRIPTION

Described herein is a phased array antenna that includes one or more unit cells. A unit cell includes a printed wiring board (PWB) that includes a radiator on a single layer of the PWB and a feed circuit on a single layer of the PWB. In one example, the radiator is a current loop radiator.


Current loop radiators described herein use low-cost materials compatible with FR4 processing thereby eliminating the need for higher cost materials to achieve performance over frequency and scan. Bandwidth in terms of frequency and scan volume can be improved in radiators by designing them with lower dielectric materials that are closer to air. But these materials typically result in increased material costs and/or fabrication complexity. Radiating structures that are naturally low-Q, high bandwidth, such as the current loop described herein, offer improved performance compared to elements such as the patch radiator that have inherently higher-Q and have less bandwidth. The current loop radiator designed for air instead of a dielectric has a bandwidth of more than 8:1 in both single and dual-polarized configurations. A current loop radiator described herein with a higher dielectric constant material achieves better axial ratio and insertion loss performance over scan and at a wider frequency bandwidth than was achieved with the previous patch radiator designs. The current loop radiator described herein also achieves significantly less variance over manufacturing tolerances than that achieved with the patch radiator.


Additionally, a current loop radiator described herein on oversized rectangular lattice achieves superior loss performance and maintain axial ratio performance near, at, and beyond grating lobe incidence better than prior art radiator designs, such as patch radiators. The grounded structure of the current loop described herein suppresses the scan blindness that typically causes large gain drops and impedance mismatch at and near grating lobe incidence. Further, the current loop radiator described herein can achieve axial ratio of less than 2 dB to be achieved out to 50-degree scan in both E- and H-Planes without any need for amplitude and phase adjustments between the linear components forming right hand circular polarization (RHCP). Because of this it is possible to cut the number of monolithic microwave integrated circuit (MIMIC) chips in half, saving significant cost and power without sacrificing receiver (RX) performance. An improvement in power and cost is possible for a transmitter (TX) (compressed) operation, but, in that case, halving the number of MIMIC chips reduces the effective isotropic radiated power (EIRP) by 3 dB all other things remaining the same.


Referring to FIGS. 1A and 1B, a phased array antenna 10 includes unit cells (e.g., a unit cell 100). In some examples, the phased array antenna 10 may be shaped as a rectangle, a square, an octagon and so forth. The unit cell 100 comprises a radome portion 102, a printed wiring board (PWB) 104 and an active layer 106 where active components are attached to layer 140 as shown in FIG. 2A. The PWB 110 includes a radiator 110 that is disposed on a dielectric 114.


Referring to FIGS. 2A to 2C, 3 and 4 the radome 102 includes a wide-angle impedance matching (WAIM) layer 112 between two air layers 108, 116. The active layer 104 includes air and active components 150 attached to the PWB 104 on layer 140.


The PWB 104 includes a radiator layer 110. The radiator layer 110 includes a radiator having four dipole arms (e.g., a dipole arm 220a, a dipole arm 220b, a dipole arm 220c and a dipole arm 220d). The dipole arms 220a-220d are excited by a feed circuit 202 (FIG. 2B) located at the feed layer 118 using vias. In one example, each dipole arm 220a-220d is connected to the feed layer by a corresponding via that extends through the dielectric 114. For example, the dipole arm 220a is connected to the feed circuit 202 by a via 208a, the dipole arm 220b is connected to the feed circuit 202 by a via 208b, the dipole arm 220c is connected to the feed circuit 202 by a via 208c, and the dipole arm 220d is connected to the feed circuit 202 by a via 208d.


Vias 208a-208d are backdrilled and filled with backdrill fill material to prevent the vias- 208a-208d from connecting to the ground plane 260b. For example, the via 208a is backdrilled from layer 260b and then filled with backdrill material 232a, the via 208b is backdrilled from layer 260b and then filled with backdrill material 232b, the via 208c is backdrilled from layer 260b and then filled with backdrill material 232c and the via 208d is backdrilled from layer 260b and then filled backdrill material 232d. The backdrills of these four vias 208a-208d are done in the same processing step and the filling of the four vias 208a-208d is also done in one processing step. The spacing between the radiator layer 110 and a ground plane 260a is typically around an eighth of a wavelength (so that with the image it is effectively a quarter wavelength) in the material (dielectric 114) between the radiator layer 110 and the ground plane 260a. In one example, the backdrill fill material is a permanent plug hole plugging ink such as PHP900 permanent hole plugging ink by San-El Kagaku Co. LTD.


Each of the dipole arms 220a-220d is grounded to the ground plane 260a, 260b by a corresponding via. For example, the dipole arm 220a is grounded using a via 210a, the dipole arm 220b is grounded using a via 210b, the dipole arm 220c is grounded using a via 210c and the dipole arm 220d is grounded using a via 210d. In one example, one or more of the vias 210a-210d are added at a particular distance from a respective via 208a-208d to control tuning.


The PWB 104 may also include other vias (e.g., a via 272) that extend through the PWB 104. The PWB 104 includes other backdrill operations and backfill material. For example, the dielectric 114 includes backdrilled material 270a-270c. The purpose of the backdrill fill material is to fill the hole created by the backdrill operation that separates the through vias from ground, which is done to simplify board construction by allowing more layer to layer connections to be made for a given number of laminations. The backdrill separates the via from the outer layers, but creates an exposed hole. This hole is filled with backdrill fill material (e.g., PHP900 by SAN-EI KAGAKU CO., LTD). That material is often plated over to provide electrical shielding.


In one example, the feed circuit 202 is a quadrature phase feed circuit. The feed circuit 202 includes a rat-race coupler 204a connected to the dipole arm 220a using the via 208a and the dipole arm 220c using the via 208c and a rat-race coupler 204b connected to the dipole arm 220b using the via 208b and the dipole arm 220d using the via 208d. The signals to the dipole arms 220a, 220c are 180° out of phase from one another and the signals to the dipole arms 220b, 220d are 180° out of phase from one another. In one example, the signals to the dipole arms 220a, 220b are 90° out of phase from one another and the signals to the dipole arms 220c, 220d are 90° out of phase from one another. In one particular example, the feed circuit 202 provides signals to the dipole arms 220a-220d using right hand circular polarization (RHCP).


The feed circuit 202 also includes a branch coupler 206 that connects to the rat-race couplers 204a, 204b. The rate race-coupler 202a includes a resistor 212a, the rat-race coupler 202b includes a resistor 212b and the branch coupler 206 includes a resistor 212c. The resistors 212a-212c provide isolation between the first rat-race coupler 202a, the second-rat-race coupler 202b and the branchline coupler 206, which improves scan performance. The branch coupler 206 is connected to a via 272, which is connected to a signal layer 140 where the active devices 150 are connected. In other examples, other methods of RF connection within the PWB may be used to connect the feed circuit 202 to the signal layer 140.


Portions of the dielectric 114 are removed to improve scan performance. In one example, a 0.25-inch drill is used to drill four holes 224a-224d to remove the dielectric 114.


The radiator can be tuned in several ways to optimize frequency of operation, polarization characteristics, and scan volume. Tuning features include via locations, dielectric constant and material thickness, pattern of the radiator circuit, spacing of the feed vias, and design of the feed circuitry. For some applications, control depth drills may be used the selectively remove dielectric material between the radiator circuit and the backplane to improve performance. The use of through metallized vias and control depth drills is also used to achieve connect the ground of the radiator and feed layer to the grounds of the CCA. This simplifies PWB construction and helps avoid the use of more expensive technology such as separate PWBs that require connectors or other interconnect components. The location and size of drills can be used as tuning features. Tightly coupled parasitic tuning elements can also be used near the radiator circuit layer for some designs to improve performance and/or reduce the depth of the radiator. The current loop feature such being low profile and being a well-grounded structure allows the current loop to offer improved grating lobe performance.


Referring to FIG. 5, an example of a PWB 104 is a PWB 500. In one example, the materials to fabricate the PWB 500 are materials compatible with FR4 processing. The PWB 500 includes a solder mask layer 501, a microstrip signal layer 502, stripline layers 516a-516j, power/ground layers 514a-514e, ground planes 517a-517b, a stripline feed signal layer 518. In this example, the feed layer is in the stripline signal layer 518 (e.g., feed circuit 202 (FIG. 2B) and the radiator layer is in the signal/patch layer 520. In this example, active components (e.g., active component 150) are bonded to the microstrip signal layer 502.


In one example, the solder mask 501 is a patterned LPI solder mask. In one example, the microstrip signal layer 502 includes copper and gold plating. In one example, the signal layers include copper. In one example, the power/ground layers include copper or copper plating. In one example, the stripline signal layer 518 includes Ticer TCR25 OPS (The manifold stripline layers 516a-516j may also have TICER TCR 25 OPS). In one example, the signal/patch layer 520 includes copper and silver plating.


Interposed between the metal layers are first material layers 504a-504e, second layers 506a-506b, third material layers 508a-508e, fourth material layers 510a-510e and fifth material layers 512a-512b. The PWB 500 also includes vias (e.g., a metal via 550) extending through the layers. Some of the vias include backfill material 552.


In one example, the first material layers 504a-504e are a phenyl ether blend resin material such as, for example, Megtron 6 manufactured by Panasonic. In one example, the second material layers 506a-506b are a high frequency laminate such as, for example, RO4360G2 manufactured by Rogers Corporation. In one example, the third material layers 508a-508e are a laminate, such as, for example, RO4350B manufactured by Rogers Corporation. In one example, the fourth material layers 510a-510e are a bond ply, such as, for example, RO4450F manufactured by Rogers Corporation. In one example, the fifth material layers 512a-512b are a laminate, such as, for example, RO4003 manufactured by Rogers Corporation.


Care is taken in stackup formation to reduce the number of laminations required in the PWB build to reduce cost and complexity. Additionally, the choice of prepregs in the PWB stackup has been developed to allow for higher number of laminations to help minimize producibility risks. The use of FR4 processing compatible materials is used to allow for high aspect ratio vias and reduced cost in fabrication. Because of these developments, no connectors and additional assembly is required to connect the radiator to the CCA. It achieves low cost, low profile, simple integration in a manner like the patch radiator, but with improved performance due to its lower Q nature.


In one example, the layers 501, 502, 504a-504c, 506a-506b, 514a-514e are laminated together to form substructure 530. The layers 508a-508e, 510a-510d, 516a-516j are laminated together to form a substructure 540. The layers 510e, 512a-512b, 517a, 517b, 518, 520 are laminated together to form the substructure 550. The substructure 530 is laminated to the substructure 540 using the layer 504d to form a substructure 560. The substructure 560 is laminated to the substructure 550 using the layer 504e to form the PWB 500.


Referring to FIGS. 6A and 6B, the unit cell 100 is a significant improvement from the patch radiator in realized gain. In FIG. 6A, the realized gain for a patch radiator may vary by more than 4 db. In FIG. 6B, the realized gain of the unit cell 100 varies by only 2 db.


Referring to FIGS. 7A and 7B, the unit cell 100 is a significant improvement from the patch radiator in axial ratio value near the grating lobes. In FIG. 7A, for the patch radiator, the axial ratio value, at about + or −60 degrees, is more than 20 db. In FIG. 7B, for the unit cell 100, the axial ratio value, at about + or −60, degrees is less than 10 db.


Referring to FIG. 8, another example of a feed circuit is the quadrature feed circuit 800. The feed circuit includes branch couplers 802a, 802b coupled to a rat-race coupler 806. The branch coupler 802a includes pads 820a, 820b and a resistor 812a and the branch coupler 802b includes pads 820c, 820d and a resistor 812b. The pads are connected to a corresponding one of the radiator dipole arms 220a-220d to provide 0°, 90°, 180°, 270° excitation of the radiator. The rat-race coupler 806 includes a pad 830, which connects to a coaxial port to receive signals. In one example, the difference in phase between the signals provided to pads 820a, 820b is 90° and the difference in phase between the signals provided to pads 820c, 820d is 90°.


Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.

Claims
  • 1. A unit cell of a phased array antenna comprising: a printed wiring board (PWB) comprising: a first layer comprising a radiator comprising: a first dipole arm; a second dipole arm; a third dipole arm; and a fourth dipole arm; a second layer comprising a quadrature feed circuit configured to generate and output excitation signals to the radiator using right hand circular polarization (RHCP); a first via coupled to the first dipole arm; a second via coupled to the second dipole arm; a third via coupled to the third dipole arm and a fourth via coupled to the fourth dipole arm, wherein the first, second, third and fourth vias provide the excitation signal from the feed circuit, a fifth via coupled to the first dipole arm; a sixth via coupled to the second dipole arm; a seventh via coupled to the third dipole arm and an eighth via coupled to the fourth dipole arm, wherein the fifth, sixth, seventh and eighth vias provide ground; a third layer between the first and second layers, wherein the third layer comprises a dielectric having four rounded corners evenly spaced around the dialecticwherein the feed circuit comprises: a first branchline coupler coupled to the first via and the second via; a second branchline coupler coupled to the third via and the fourth via; a rat-race coupler coupled to the first and second branchline couplers.
  • 2. The unit cell of claim 1, wherein the feed circuit comprises: a first rat-race coupler coupled to the first via and the third via;a second rat-race couple coupled to the second via and the fourth via;a branchline coupler coupled to the first and second rat race couplers.
  • 3. The unit cell of claim 2, wherein signals to the first and third dipole arms are 180° out of phase from one another, and wherein signals to the second and fourth dipole arms are 180° out of phase from one another.
  • 4. The unit cell of claim 3, wherein signals to the first and second dipole arms are 90° out of phase from one another, and wherein signals to the third and fourth dipole arms are 90° out of phase from one another.
  • 5. The unit cell of claim 2, wherein the feed circuit further comprises: a first resistor coupled to the first rat-race coupler;a second resistor coupled to the second rat-race coupler; anda third resistor coupled to the branchline coupler,wherein the first, second and third resistors provide isolation between the first rat-race coupler, the second-rat-race coupler and the branchline coupler.
  • 6. The unit cell of claim 1, wherein the four rounded corners are formed using a 0.25-inch drill bit.
  • 7. The unit cell of claim 1, further comprising: an active component layer comprising an active component bonded to the PWB; anda radome comprising a wide-angle impedance matching (WAIM) layer.
US Referenced Citations (100)
Number Name Date Kind
2015028 Gillette Sep 1935 A
3528050 Hindenburg Sep 1970 A
4647942 Counselman, III et al. Mar 1987 A
4690471 Marabotto et al. Sep 1987 A
5172082 Livingston et al. Dec 1992 A
5410281 Blum Apr 1995 A
5434575 Jelinek Jul 1995 A
5453751 Tsukamoto et al. Sep 1995 A
5455546 Frederick et al. Oct 1995 A
5603620 Hinze et al. Feb 1997 A
5644277 Gulick et al. Jul 1997 A
5745079 Wang et al. Apr 1998 A
5838282 Lalezari et al. Nov 1998 A
5880694 Wang et al. Mar 1999 A
5886590 Quan et al. Mar 1999 A
5995047 Freyssinier et al. Nov 1999 A
6100775 Wen Aug 2000 A
6114997 Lee Sep 2000 A
6147648 Granholm et al. Nov 2000 A
6184832 Geyh et al. Feb 2001 B1
6320542 Yamamoto Nov 2001 B1
6429816 Whybrew et al. Aug 2002 B1
6459415 Pachal et al. Oct 2002 B1
6512487 Taylor et al. Jan 2003 B1
6664867 Chen Dec 2003 B1
6686885 Barkdoll et al. Feb 2004 B1
6856297 Durham et al. Feb 2005 B1
6867742 Irion, II et al. Mar 2005 B1
6876336 Croswell et al. Apr 2005 B2
6882247 Allison et al. Apr 2005 B2
6935866 Kerekes et al. Aug 2005 B2
6977623 Durham et al. Dec 2005 B2
7012572 Schaffner et al. Mar 2006 B1
7084827 Strange et al. Aug 2006 B1
7113142 McCarville et al. Sep 2006 B2
7132990 Stenger et al. Nov 2006 B2
7138952 Mcgrath et al. Nov 2006 B2
7193490 Shimoda Mar 2007 B2
7221322 Durham et al. May 2007 B1
7272880 Pluymers et al. Sep 2007 B1
7315288 Livingston et al. Jan 2008 B2
7358921 Snyder et al. Apr 2008 B2
7411472 West et al. Aug 2008 B1
7414590 Bij De Vaate et al. Aug 2008 B2
7688265 Irion, II et al. Mar 2010 B2
7948441 Irion, II et al. May 2011 B2
8035992 Kushta et al. Oct 2011 B2
8325093 Holland et al. Dec 2012 B2
8753145 Lang et al. Jun 2014 B2
9136572 Carr et al. Sep 2015 B2
9402301 Paine et al. Jul 2016 B2
9437929 Isom et al. Sep 2016 B2
9490519 Lilly et al. Nov 2016 B2
9537208 Isom Jan 2017 B2
20030020654 Navarro et al. Jan 2003 A1
20030112200 Marino Jun 2003 A1
20030184476 Sikina et al. Oct 2003 A1
20050007286 Trott Jan 2005 A1
20050156802 Livingston et al. Jul 2005 A1
20060038732 Deluca et al. Feb 2006 A1
20060097947 McCarville et al. May 2006 A1
20080036665 Schadler Feb 2008 A1
20080150832 Ingram et al. Jun 2008 A1
20080169992 Ortiz et al. Jul 2008 A1
20080316131 Apostolos et al. Dec 2008 A1
20090073075 Irion, II et al. Mar 2009 A1
20090091506 Navarro et al. Apr 2009 A1
20090121967 Cunningham May 2009 A1
20090231225 Choudhury et al. Sep 2009 A1
20090284415 Worl Nov 2009 A1
20100164783 Choudhury et al. Jul 2010 A1
20100245202 Lewis et al. Sep 2010 A1
20110089531 Hillman et al. Apr 2011 A1
20120034820 Lang et al. Feb 2012 A1
20120068906 Asher et al. Mar 2012 A1
20120098706 Lin et al. Apr 2012 A1
20120146869 Holland Jun 2012 A1
20120212386 Massie Aug 2012 A1
20120287581 Sauerbier et al. Nov 2012 A1
20120306698 Warnick et al. Dec 2012 A1
20120313818 Puzella et al. Dec 2012 A1
20130026586 Seok et al. Jan 2013 A1
20130050055 Paradiso et al. Feb 2013 A1
20130175078 Pai Jul 2013 A1
20130187830 Warnick Jul 2013 A1
20130194754 Jung et al. Aug 2013 A1
20130207274 Liu et al. Aug 2013 A1
20130314292 Maley Nov 2013 A1
20140132473 Isom May 2014 A1
20140264759 Koontz et al. Sep 2014 A1
20150015453 Puzella et al. Jan 2015 A1
20150200460 Isom et al. Jul 2015 A1
20150263435 Song Sep 2015 A1
20150353348 Vandemeer et al. Dec 2015 A1
20160104934 Jang Apr 2016 A1
20160172755 Chen et al. Jun 2016 A1
20160352023 Dang et al. Dec 2016 A1
20180040955 Vouvakis Feb 2018 A1
20180090851 Feldman et al. Mar 2018 A1
20180337461 Kildal et al. Nov 2018 A1
Foreign Referenced Citations (22)
Number Date Country
103247581 Aug 2013 CN
204857954 Dec 2015 CN
1 970 952 Sep 2008 EP
1 970 952 Sep 2008 EP
U-1992027609 Mar 1992 JP
H07-106841 Apr 1995 JP
2000-312112 Nov 2000 JP
2006-504375 Feb 2006 JP
2008-244581 Oct 2008 JP
2012-044653 Mar 2012 JP
2012-174874 Sep 2012 JP
6195935 Sep 2017 JP
10-2011-0091574 Aug 2011 KR
10-2015-0120414 Oct 2015 KR
2014-03765 Apr 2014 TW
2014-34203 Sep 2014 TW
2016-05017 Feb 2016 TW
WO 2009077791 Jun 2009 WO
WO 2014168669 Oct 2014 WO
WO 2015006293 Jan 2015 WO
WO 2016138267 Sep 2016 WO
WO 2016138267 Sep 2016 WO
Non-Patent Literature Citations (129)
Entry
U.S. Appl. No. 14/881,582, filed Oct. 13, 2015, Viscarra et al.
U.S. Office Action dated Jun. 8, 2015 corresponding to U.S. Appl. No. 13/674,547; 23 Pages.
Response to U.S. Office Action dated Jun. 8, 2015 corresponding to U.S. Appl. No. 13/674,547; Response filed on Aug. 28, 2015; 18 Pages.
U.S. Final Office Action dated Dec. 3, 2015 corresponding to U.S. Appl. No. 13/674,547; 22 Pages.
Response to U.S. Final Office Action dated Dec. 3, 2015 corresponding to U.S. Appl. No. 13/674,547; Response filed on Feb. 22, 2016; 16 Pages.
U.S. Office Action dated Apr. 7, 2016 corresponding to U.S. Appl. No. 13/674,547; 27 Pages.
Response to U.S. Office Action dated Apr. 7, 2016 corresponding to U.S. Appl. No. 13/674,547; Response filed on Jun. 21, 2016; 16 Pages.
U.S. Final Office Action dated Jul. 1, 2016 corresponding to U.S. Appl. No. 13/674,547; 30 Pages.
Response to U.S. Final Office Action dated Jul. 1, 2016 corresponding to U.S. Appl. No. 13/674,547; Response filed on Aug. 18, 2016; 14 Pages.
Notice of Allowance dated Sep. 16, 2016 corresponding to U.S. Appl. No. 13/674,547; 17 Pages.
PCT International Search Report and Written Opinion dated Jun. 28, 2013 corresponding to International Application No. PCT/US2013/038408; 14 Pages.
PCT International Preliminary Report dated May 21, 2015 corresponding to International Application No. PCT/US2013/038408; 9 Pages.
European 161/162 Communication dated Jul. 9, 2015 corresponding to European Application No. 13721516.6; 2 Pages.
Response (with Amended Claims) to European 161/162 Communication dated Jul. 9, 2015 corresponding to European Application No. 13721516.6; Response filed on Jan. 19, 2016; 34 Pages.
Korean Office Action (with English Translation) dated Feb. 27, 2016 corresponding to Korean Application No. 10-2015-7010618; 4 Pages.
Response (with Foreign Associate Reporting Letter) to Korean Office Action dated Feb. 27, 2016 corresponding to Korean Application No. 10-2015-7010618; Response filed on Apr. 27, 2016; 15 Pages.
Japanese Office Action (with English Translation) dated Jun. 21, 2016 corresponding to Japanese Application No. 2015-541757; 8 Pages.
Response (with Foreign Associate Reporting Letter) to Japanese Office Action dated Jun. 21, 2016 corresponding to Japanese Application No. 2015-541757; Response filed on Sep. 21, 2016; 7 Pages.
PCT International Search Report and Written Opinion dated Aug. 30, 2016 corresponding to International Application No. PCT/US2016/034045; 11 Pages.
Hotte et al., “Directive and High-Efficiency Slotted Waveguide Antenna Array for V-Band Made by Wire Electrical Discharge Machining;” Electronics Letters, vol. 51, No. 5; Mar. 5, 2015; 2 Pages.
Kasemodel et al., “Broadband Array Antenna Enhancement with Spatially Engineered Dielectric;” U.S. Appl. No. 13/590,769, filed Aug. 21, 2012; 19 Pages.
Kasemodel et al., “Broadband Planar Wide-Scan Array Employing Tightly Coupled Elements and Integrated Balun;” Proceedings of the IEEE International Symposium on Phased Array Systems and Technology (ARRAY); Oct. 12-15, 2010; 6 Pages.
Kindt et al., “Polarization Correction in Dual-Polarized Phased Arrays of Flared Notches;” Proceedings of the IEEE International Symposium on Antennas and Propagation (APSURSI); Jul. 3-8, 2011; 4 Pages.
Mishra et al., “Array of SIW Resonant Slot Antenna for V Band Applications;” Proceedings of the International Conference on Microwave and Photoics (ICMAP); Dec. 13-15, 2013; 4 Pages.
Nesic et al., “Wideband Printed Antenna with Circular Polarization;” Proceedings of the IEEE Antennas and Propagation Society International Symposium; Jul. 13-18, 1997; 4 Pages.
Wong et al., “Broad-Band Single-Patch Circularly Polarized Microstrip Antenna with Dual Capacitively Coupled Feeds;” Proceedings of the IEEE Transactions on Antennas and Propagation, vol. 49, No. 1; Jan. 2001; 4 Pages.
Wong et al., “Design of Dual-Polarized L-Probe Patch Antenna Arrays With High Isolation;” Proceedings of the IEEE Transactions on Antennas and Propagation, vol. 52, No. 1; Jan. 2004; 8 Pages.
Wu et al., “A Wideband High-Gain High-Efficiency Hybrid Integrated Plate Array Antenna for V-Band Inter-Satellite Links;” Proceedings of the IEEE Transactions on Antennas and Propagation, vol. 63, No. 4; Apr. 2015; 9 Pages.
Chang-Chien et al., “MMIC Compatible Wafer-Level Packaging Technology;” Proceedings of the International Conference on Indium Phosphide and Related Materials (19th IPRM); May 14-18, 2007; 4 Pages.
Chang-Chien et al., “MMIC Packaging and Heterogeneous Integration Using Wafer-Scale Assembly;” Proceedings of the CS MANTECH Conference; May 14-17, 2007; 4 Pages.
Chang-Chien, “Wafer-Level Packaging and Wafer-Scale Assembly Technologies;” Presentation by Northrop Grumman Aerospace Systems (NGAS); Proceedings of the CS MANTECH Workshop 6; May 17, 2010; 43 Pages.
Green, “DARPA's Heterogeneous Integration Vision and Progress on Modular Design;” Presentation by DARPA; Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference (ASIP); Dec. 17, 2015; 17 Pages.
Gu et al., “W-Band Scalable Phased Arrays for Imaging and Communications;” Integrated Circuits for Communications, IEEE Communications Magazine; Apr. 2015; 9 Pages.
Popovic, “Micro-coaxial Micro-fabricated Feeds for Phased Array Antennas;” Proceedings of the 2010 IEEE International Symposium on Phased Array Systems and Technology (ARRAY); Oct. 12-15, 2010; 10 Pages.
Shin et al., “A 108-114 GHz 4×4 Wafer-Scale Phased Array Transmitter with High-Efficiency On-Chip Antennas;” IEEE Journal of Solid-State Circuits, vol. 48, No. 9; Sep. 2013; 15 Pages.
U.S. Appl. No. 15/381,286, filed Dec. 16, 2016, Teshiba et al.
U.S. Appl. No. 15/379,775, filed Dec. 15, 2016, Isom et al.
Urteaga, “3D Heterogeneous Integration of III-V Devices and Si CMOS;” Presentation by Teledyne Scientific Company; Proceedings of the 3D Architectures for Semiconductor Integration and Packaging Conference (ASIP); Dec. 17, 2015; 26 Pages.
Zihir et al., “A 60 GHz 64-element Wafer-Scale Phased-Array with Full-Reticle Design;” Proceedings of the 2015 IEEE MTT-S International Microwave Symposium; May 17-22, 2015; 3 Pages.
U.S. Non-Final Office Action dated May 18, 2017 for U.S. Appl. No. 14/881,582; 21 Pages.
PCT International Search Report and Written Opinion dated Jan. 3, 2018 for International Application No. PCT/US2017/055059; 17 Pages.
PCT International Search Report and Written Opinion dated Jan. 3, 2018 for International Application No. PCT/US2017/055222; 16 Pages.
Luo et al.; “Meander Line Coupled Cavity-Backed Slot Antenna for Broadband Circular Polarization”; IEEE Antennas and Wireless Propagation Letters; vol. 14; Feb. 2, 2015; 4 Pages.
Response to U.S. Non-Final Office Action dated May 18, 2017 for U.S. Appl. No. 14/881,582; Response filed on Jun. 5, 2017; 7 Pages.
Notice of Allowance dated Jun. 23, 2017 for U.S. Appl. No. 14/881,582; 8 Pages.
PCT International Search Report and Written Opinion dated Dec. 8, 2017 for International Application No. PCT/US2017/054836; 15 Pages.
Japanese Office Action dated Feb. 28, 2017 for Japanese Pat. App. No. 2015-541757 with English Translations; 4 Pages.
U.S. Non-Final Office Action dated Apr. 5, 2018 for U.S. Appl. No. 15/379,775; 16 Pages.
PCT International Preliminary Report and Written Opinion dated Apr. 26, 2018 for International Application No. PCT/US2016/034045; 8 Pages.
Response to U.S. Non-Final Office Action dated Apr. 5, 2018 for U.S. Appl. No. 15/379,775; Response filed Aug. 1, 2018; 17 Pages.
Tong et al., “Novel Sequential Rotation Technique for Broadband Circularly Polarized Microstrip Ring Antennas;” Loughborough Antennas & Propagation Conference; Mar. 17, 2008; 4 Pages.
PCT International Search Report and Written Opinion dated Apr. 26, 2018 for International Application No. PCT/US2018/015421; 15 Pages.
Taiwan Office Action (with Search Report) dated Jun. 19, 2018 for Taiwan Application No. 106135418; 18 Pages.
U.S. Non-Final Office Action dated Jul. 5, 2018 for U.S. Appl. No. 15/381,286; 8 Pages.
Response (with English Translation of Response, Current Claims and Amended Specification) to Taiwan Office Action dated Jun. 19, 2018 for Taiwan Application No. 106135418; Response filed on Sep. 12, 2018; 40 Pages.
Response to U.S. Non-Final Office Action dated Jul. 5, 2018 for U.S. Appl. No. 15/381,286; Response filed on Sep. 6, 2018; 8 Pages.
U.S. Final Office Action dated Sep. 21, 2018 for U.S. Appl. No. 15/379,775; 19 Pages.
U.S. Non-Final Office Action dated Oct. 9, 2018 for U.S. Appl. No. 15/731,906; 13 Pages.
Response to U.S. Non-Final Office Action dated Oct. 9, 2018 for U.S. Appl. No. 15/731,906; Response filed Nov. 16, 2018; 12 Pages.
Taiwan Examination Report (with English Translation) dated Oct. 31, 2018 for Taiwan Application No. 106135617; 23 Pages.
Taiwan Examination Report (with English Translation) dated Nov. 2, 2018 for Taiwan Application No. 106135613; 20 Pages.
Taiwan Examination Report (with English Translation) dated Nov. 26, 2018 for Taiwan Application No. 106135418; 8 Pages.
Taiwan Examination Report and Search Report (with English Translation) dated Apr. 15, 2019 for Taiwan Application No. 106135617; 21 Pages.
Response to Non-Final Office Action dated Feb. 27, 2019 for U.S. Appl. No. 15/381,286; Response filed May 21, 2019; 12 Pages.
Response (with Machine English Translation from Google Translator) to Taiwan Examination Report dated Apr. 15, 2019 for Taiwan Application No. 106135617; Response filed Jul. 4, 2019; 18 Pages.
Response to U.S. Final Office Action dated Jun. 11, 2019 for U.S. Appl. No. 15/381,286; Response filed Jul. 17, 2019; 7 Pages.
Taiwan Statement of Reasons for Re-Examination (with English Translation & Reporting Letter dated Jan. 8, 2019) dated Jan. 8, 2019 for Taiwan Application No. 106135418; 7 Pages.
Response to U.S. Final Office Action dated Jan. 2, 2019 for U.S. Appl. No. 15/381,286; Response and RCE filed Feb. 5, 2019; 10 Pages.
U.S. Non-Final Office Action dated Feb. 27, 2019 for U.S. Appl. No. 15/381,286; 17 Pages.
Taiwan Allowance Decision (with English Translation) dated Mar. 20, 2019 for Taiwan Application No. 106135613; 4 Pages.
Japanese Final Office Action (with English Translation) dated Feb. 28, 2017 for Japanese Application No. 2015-541757; 4 Pages.
European Examination Report dated Jun. 21, 2018 for European Application No. 13721516.6; 6 Pages.
Response to European Examination Report dated Jun. 21, 2018 for European Application No. 13721516.6; Response filed Oct. 26, 2018; 16 Pages.
U.S. Notice of Allowance dated Apr. 4, 2019 for U.S. Appl. No. 15/731,906; 5 Pages.
Response to U.S. Non-Final Office Action dated Jan. 14, 2019 for U.S. Appl. No. 15/379,775; Response filed Apr. 25, 2019; 10 Pages.
U.S. Final Office Action dated Jan. 2, 2019 for U.S. Appl. No. 15/381,286; 16 Pages.
Response to U.S. Final Office Action dated Sep. 21, 2018 for U.S. Appl. No. 15/379,775; Response filed Dec. 21, 2018; 13 Pages.
U.S. Non-Final Office Action dated Jan. 14, 2019 for U.S. Appl. No. 15/379,775; 22 Pages.
U.S. Notice of Allowance dated Dec. 14, 2018 for U.S. Appl. No. 15/731,906; 9 Pages.
Response (with English Translation, Claims and Specification) to Taiwan Examination Report dated Oct. 31, 2018 for Taiwan Application No. 106135617; Response filed Jan. 7, 2019; 22 Pages.
Response (with English Translation and Specification) to Taiwan Examination Report dated Nov. 2, 2018 for Taiwan Application No. 106135613; Response filed Jan. 8, 2019; 9 Pages.
U.S. Final Office Action dated Jun. 11, 2019 for U.S. Appl. No. 15/381,286; 18 Pages.
PCT International Preliminary Report dated Jun. 27, 2019 for International Application No. PCT/US2017/054836; 9 Pages.
PCT International Preliminary Report dated Jun. 27, 2019 for International Application No. PCT/US2017/055059; 13 Pages.
PCT International Preliminary Report dated Jun. 27, 2019 for International Application No. PCT/US2017/055222; 9 Pages.
European Communication Pursuant to Rules 161(1) and 162 EPC dated Jul. 23, 2019 for European Application No. 17785128.4; 3 Pages.
European Communication Pursuant to Rules 161(1) and 162 EPC dated Jul. 23, 2019 for European Application No. 17791226.8; 3 Pages.
European Communication Pursuant to Rules 161(1) and 162 EPC dated Jul. 23, 2019 for European Application No. 17784814.0; 3 Pages.
Korean Notice of Preliminary Rejection (with English Translation) dated Dec. 19, 2019 for Korean Application No. 10-2019-7013632; 11 Pages.
Taiwan Allowance Decision (with English Translation) dated Dec. 23, 2019 for Taiwan Application No. 106135418; 3 Pages.
Response (with English Translation) to Taiwan Examination Report dated Sep. 20, 2019 for Taiwan Application No. 106135418; Response filed Dec. 10, 2019; 12 Pages.
Examination Report dated Sep. 9, 2019 for European Application No. 13721516.6; 4 Pages.
U.S. Notice of Allowance dated Sep. 5, 2019 for U.S. Appl. No. 15/381,286; 13 Pages.
U.S. Notice of Allowance dated Sep. 17, 2019 for U.S. Appl. No. 15/379,775; 16 Pages.
Taiwan Office Action (with English Translation) dated Sep. 20, 2019 for Taiwan Application No. 106135418; 14 Pages.
Response (with Amended Claims) to European Examination Report dated Sep. 9, 2019 for European Application No. 13721516.6; Response filed Jan. 17, 2020; 6 Pages.
Response (with Amended Claims) to European Rule 161/162 Communication dated Jul. 23, 2019 for European Application No. 17785128.4; Response filed Jan. 27, 2020; 16 Pages.
Response (with Amended Claims) to European Rule 161/162 Communication dated Jul. 23, 2019 for European Application No. 17784814.0; Response filed Feb. 3, 2020; 24 Pages.
Response (with Machine English Translation) to Korean Office Action dated Dec. 19, 2019 for Korean Application No. 10-2019-7013632; Response filed Feb. 17, 2020; 33 Pages.
PCT International Preliminary Report dated Feb. 13, 2020 for International Application No. PCT/US2018/015421; 9 Pages.
Korean Office Action (with English Translation) dated Jul. 10, 2020 for Korean Application No. 10-2019-7010632; 13 Pages.
European Examination Report dated Jul. 29, 2020 for European Application No. 17784814.0; 7 Pages.
Japanese Decision to Grant (with Machine English Translation and Allowed Claims) dated Aug. 3, 2020 for Japanese Application No. 2019-525735; 7 Pages.
Response (with Machine English Translation) to Korean Office Action dated May 13, 2020 for Korean Application No. 10-2019-7012561; Response filed Jun. 1, 2020; 35 Pages.
Chinese First Office Action (with English Translation) dated Jul. 27, 2020 for Chinese Application No. 201780066115.2; 18 Pages.
Response (with Machine English Translation from Espacenet.com) to Korean Office Action dated Jul. 10, 2020 for Korean Application No. 10-2019-7010632; Response filed Aug. 19, 2020; 44 Pages.
Japanese Office Action (with English Translation) dated Aug. 18, 2020 for Japanese Application No. 2019-531284; 12 Pages.
European Rule 161/162 Communication dated Mar. 11, 2020 for European Application No. 18704713.9; 3 Pages.
Korean Notice of Rejection (with English Translation) dated May 13, 2020 for Korean Application No. 10-2019-7012561; 6 Pages.
Response to European Rule 161/162 Communication dated Mar. 11, 2020 for European Application No. 17791226.8; Response filed Jun. 1, 2020; 17 Pages.
Korean Notice of Allowance (with Machine English Translation and Allowed Claims) dated May 27, 2020 for Korean Application No. 10-2019-7013632; 6 Pages.
Response (with Machine English Translation from Espacenet.com) to Japanese Office Action dated Sep. 1, 2020 for Japanese Application No. 2019-531220; Response filed Nov. 26, 2020; 11 Pages.
Korean Office Action (with English Translation) dated Dec. 1, 2020 for Korean Application No. 10-2019-7012561; 9 Pages.
European Intention to Grant dated Nov. 10, 2020 for European Application No. 17785128.4; 5 Pages.
Response (with Machine English Translation from Espacenet.com) to Korean Office Action dated Sep. 23, 2020 for Korean Application No. 10-2019-7038981; Response filed Nov. 24, 2020; 25 Pages.
Response to European Examination Report dated Jul. 29, 2020 for European Application No. 17784814.0; Response filed Dec. 4, 2020; 15 Pages.
Response (with Machine English Translation) to Chinese First Office Action dated Jul. 27, 2020 for Chinese Application No. 201780066115.2; Response filed Dec. 10, 2020; 17 Pages.
Korean Decision to Grant (with Machine English Translation) dated Dec. 7, 2020 for Korean Application No. 10-2019-7010632; 9 Pages.
Japanese Decision to Grant (with Machine English Translation from Espacenet.com) with Allowed Claims dated Nov. 27, 2020 for Japanese Application No. 2019-531284; 8 Pages.
Japanese Office Action (with Machine English Translation) dated Sep. 1, 2020 for Japanese Application No. 2019-531220; 17 Pages.
Response (with Machine English Translation from Espacenet.com) to Korean Office Action dated Dec. 1, 2020 for Korean Application No. 10-2019-7012561; Response filed Dec. 28, 2020; 22 Pages.
Response (with Machine English Translation from Espacenet.com) to Japanese Office Action dated Aug. 18, 2020 for Japanese Application No. 2019-531284; Response filed Nov. 12, 2020; 12 Pages.
Office Action dated Sep. 23, 2020 for Korean Application No. 10-2019-7038981 with English Translation; 5 Pages.
Secondary European Response (with Amended Claims) filed on Sep. 24, 2020 for European Application No. 17785128.4; 9 Pages.
Japanese Notice of Allowance (with Machine English Translation from Epsacenet.com and Allowed Claims) dated Feb. 2, 2021 for Japanese Application No. 2019-531220; 9 Pages.
2nd Chinese Office Action (with English Translation) dated Apr. 2, 2021 for Chinese Application No. 201780066115.2; 6 Pages.
Examination Report dated Mar. 19, 2021 for European Application No. 13721516.6; 5 Pages.
European Examination Report dated Feb. 12, 2021 for European Application No. 17791226.8; 8 Pages.
Response to European Examination Report dated Feb. 12, 2021 for European Application No. 17791226.8; Response filed on Jun. 22, 2021; 18 Pages.
Related Publications (1)
Number Date Country
20180175512 A1 Jun 2018 US