Patent Grant
12043030
This application claims priorities from Japanese Patent Application No. 2021-151376 filed on Sep. 16, 2021, and Japanese Patent Application No. 2022-073449 filed on Apr. 27, 2022. The entire contents of the priority applications are incorporated herein by reference.
There is a printer which generates first to fourth driving pulses having different amplitudes, as driving signals for driving a piezoelectric element of each of nozzles. The first to fourth driving pulses are continuously generated during one cycle for printing one pixel. One of the first to fourth driving pulses is selected and applied to the piezoelectric element of each of the nozzles. Each of the nozzles discharges or ejects an ink in an amount corresponding to the amplitude of the selected driving pulse so as to form a dot having a desired size.
According to a first aspect of the present disclosure, there is provided a printing apparatus including:
In the time division multiplex signal, the third portion being the part of the second driving waveform is aligned between the first portion being the part of the first driving waveform and the second portion being other part of the first driving waveform, and the second portion being other part of the first driving waveform is aligned between the third portion being the part of the second driving waveform and the fourth portion being other part of the second driving waveform.
The time division multiplex signal is capable of transmitting the first data and the second data via single signal line.
The synchronization signal generating circuit is a circuit different from the signal generating circuit.
According to a second aspect of the present disclosure, there is provided a method of controlling driving of a printing apparatus including an energy generating element configured to cause a nozzle to discharge a liquid, the method including:
In the time division multiplex signal, the third portion being the part of the second driving waveform is aligned between the first portion being the part of the first driving waveform and the second portion being other part of the first driving waveform, and the second portion being other part of the first driving waveform is aligned between the third portion being the part of the second driving waveform and the fourth portion being other part of the second driving waveform.
The time division multiplex signal is capable of transmitting the first data and the second data via single signal line.
The synchronization signal generating circuit is a circuit different from the signal generating circuit.
According to a third aspect of the of the present disclosure, there is provided a non-transitory and computer-readable medium storing a program thereon, the program being executable by a controller of a printing apparatus which includes an energy generating element configured to cause a nozzle to discharge a liquid, the program is configured to cause the controller to:
In the time division multiplex signal, the third portion being the part of the second driving waveform is aligned between the first portion being the part of the first driving waveform and the second portion being other part of the first driving waveform, and the second portion being other part of the first driving waveform is aligned between the third portion being the part of the second driving waveform and the fourth portion being other part of the second driving waveform.
The time division multiplex signal is capable of transmitting the first data and the second data via single signal line.
The synchronization signal generating circuit is a circuit different from the signal generating circuit.
Although the four driving pulses are continuously generated during one cycle, only one driving pulse is selected. On this account, the time, which is allotted to the three driving pulses which are not selected, is the waiting time of the nozzle.
The present disclosure has been made taking the foregoing circumstances into consideration, an object of which is to provide a printing apparatus, a control method and a medium each of which is capable of adjusting the amplitude of a driving waveform applied to an energy generating element (energy application element) and reducing the waiting time of a nozzle.
According to a printing apparatus of an embodiment of the present disclosure, it is possible to adjust the amplitude of the driving waveform applied to the energy generating element and to reduce the waiting time of the nozzle.
The present disclosure will be explained below on the basis of the drawings depicting a printing apparatus according to a first embodiment.
As depicted in
Two guide rails 11 and 12, which guide the carriage 6 and which extend in the left-right direction, are provided above the platen 2. The carriage 6 has a housing (casing). An endless belt 13, which extends in the left-right direction, is connected to the housing of the carriage 6. The endless belt 13 is driven by a carriage driving motor 14. The carriage 6 is guided by the guide rails 11 and 12, and reciprocated in the moving direction in the area facing (opposed to) the platen 2 in accordance with the driving of the endless belt 13. More specifically, in a state that the carriage 6 supports the four inkjet heads 8, the carriage 6 performs a first movement in which the carriage 6 moves the head from a certain position to another position from the left to the right in the moving direction, and a second movement in which the carriage 6 moves the head from the another position to the certain position from the right to the left in the moving direction.
A cap 20 and a flushing receiver 21 are provided between the guide rails 11 and 12. The cap 20 and the flushing receiver 21 are arranged under or below the ink discharge device 3. The cap 20 is arranged at the right end portions of the guide rails 11 and 12, and the flushing receiver 21 is arranged at the left end portions of the guide rails 11 and 12. Note that the cap 20 may be arranged at the left end portions of the guide rails 11 and 12, and the flushing receiver 21 may be arranged at the right end portions of the guide rails 11 and 12.
The subtank 7 and the four ink-jet heads 8 are carried on the carriage 6, and the subtank 7 and the four ink-jet heads 8 are reciprocatively moved (reciprocated) in the moving direction together with the carriage 6. The subtank 7 is connected to a cartridge holder 15 via tubes 17. An ink cartridge 16 of one color or ink cartridges 16 of a plurality of colors (four colors in this embodiment) is or are installed to the cartridge holder 15. The four colors are exemplified, for example, by black, yellow, cyan, and magenta.
Four ink chambers (not depicted) are formed in the inside of the subtank 7. The four color inks, which are supplied from the four ink cartridges 16, are stored in the four ink chambers, respectively.
The four ink-jet heads 8 are arranged side by side in the moving direction under the subtank 7. A plurality of nozzles 80 (see
Each of the four ink-jet heads 8 is provided with an ink supply port and an ink discharge port. The ink supply port and the ink discharge port are connected to the ink chamber of the subtank 7, for example, via tubes. A circulating pump is intervened between the ink supply port and the ink chamber.
The ink sent from the ink chamber of the subtank 7 by the circulating pump flows into the ink-jet head 8 through the ink supply port, and the ink is discharged from the nozzle 80. The ink, which has not been discharged from the nozzle 80 returns to the ink chamber of the subtank 7 through the ink discharge port. The ink circulates between the ink chamber of the subtank 7 and the ink-jet head 8. The four ink-jet heads 8 discharge the four color inks supplied from the subtank 7 onto the recording paper 200, while moving in the moving direction together with the carriage 6.
As depicted in
The controller 50 receives a print job and driving waveform data from an external device 100, and the controller 50 stores the print job and the driving waveform data in the memory 55. The controller 50 controls the driving of, for example, the ink discharge device 3 and the conveying roller 4 based on the print job and executes a printing processing. Note that the controller 50 may be arranged in the inside of the carriage 6.
A second common electrode 86 is provided on the inside of the piezoelectric member 83. The second common electrode 86 is arranged on the upper side of each of the pressure chambers 81 and on the upper side of the first common electrode 84. The second common electrode 86 is arranged at a position at which the second common electrode 86 does not face (is not opposed to) the first common electrode 84. An individual electrode 85 is formed on the upper surface of the piezoelectric member 83, at a location on the upper side of each of the plurality of pressure chambers 81. The individual electrode 85 vertically faces the first common electrode 84 and the second common electrode 86 with the piezoelectric member 83 intervened therebetween. The vibration plate 82, the piezoelectric member 83, the first common electrode 84, the individual electrode 85, and the second common electrode 86 construct an actuator 88. In the first embodiment, although the actuator 88 has a three-layer structure, the actuator 88 may have a two-layer structure. Although the actuator 88 is of the piezoelectric system, the actuator 88 may be of the Bubble Jet (trademark) system or of the electrostatic force system.
A nozzle plate 87 is provided under or below the respective pressure chambers 81. A plurality of nozzles 80, which vertically penetrate, are formed on the nozzle plate 87. Each of the plurality of nozzles 80 is arranged on the lower side of one of the plurality of pressure chambers 81. The plurality of nozzles 80 constitute a plurality of nozzle arrays which extend, respectively, along the pressure chamber arrays.
The first common electrode 84 is connected to a COM terminal, i.e., the ground in this embodiment. The second common electrode 86 is connected to a VCOM terminal. The VCOM voltage is higher than the COM voltage. The individual electrode 85 is connected to a switch group 54 (see
The digital-analog converter 52 converts a digital signal into an analog signal. The amplifier 53 amplifies the analog signal. The switch group 54 is provided with a plurality of n-th switches 54(n) (n=1, 2, . . . N). The n-th switches 54(n) are constructed, for example, by an analog switch IC. One end of each of the plurality of n-th switches 54(n) is connected to the amplifier 53 via a common bus. The other end of each of the plurality of n-th switches 54(n) is connected to the individual electrode 85 corresponding to one of the plurality of nozzles 80.
A first capacitor 89a is constructed by the individual electrode 85, the first common electrode 84, and the piezoelectric member 83. A second capacitor 89b is constructed by the individual electrode 85, the second common electrode 86, and the piezoelectric member 83.
The control circuit 51 transmits the time series data to the digital-analog converter 52. As depicted in
The control circuit 51 transmits a switch control signal S1 for controlling the opening and closing of the plurality of n-th switches 54(n) to the switch control circuit 57. Further, the control circuit 51 transmits a generation instruction signal S3 for instructing generation of a synchronization signal S2a corresponding to the driving waveform A, a synchronization signal S2b corresponding to the driving waveform B, and generation of a synchronization signal S2c corresponding to the driving waveform C to the synchronization signal generating circuit 56. Note that the three synchronization signals S2a, S2b and S2c may be simply expressed as a “synchronization signal S2” as well (see
The switch control signal S1 includes first selection information indicating as to which one of the plurality of n-th switches 54(n) is to be selected, and second selection information indicating as to which one of the three synchronization signals S2a, S2b and S2c is to be selected. The first selection information and the second selection information are associated with each other.
The synchronization signal generating circuit 56 includes a counter synchronized with the counter of the control circuit 51, and generates the synchronization signals S2a, S2b and S2c from the generation instruction signal S3 based on the counter.
A time interval (pulse interval) between the rising edges (time points of the rising edges) of the pulse of the generation instruction signal S3 is 3Δt. The synchronization signal S2b is generated by delaying the rising edge (time point of the rising edge) of the generation instruction signal S3 by Δt, and the pulse interval of the generation instruction signal S3 and the pulse interval of the synchronization signal S2b are the same. The synchronization signal S2c is generated by delaying the rising edge of the generation instruction signal S3 by 2Δt, and the pulse interval of the generation instruction signal S3 and the pulse interval of the synchronization signal S2c are the same. The synchronization signal S2a is generated by delaying the rising edge of the generation instruction signal S3 by 3Δt, and the pulse interval of the generation instruction signal S3 and the pulse interval of the synchronization signal S2a are the same. That is, the generation instruction signal S3 and the synchronization signal S2a are similar signals.
The switch group 54 opens and closes a selected n-th switch 54(n) at an opening and closing timing indicated by a selected synchronization signal among the synchronization signals S2a to S2c. In other words, the switch group 54 opens and closes the n-th switch 54(n) in accordance with a predetermined sampling frequency. The switch group 54, the synchronization signal generating circuit 56 and the switch control circuit 57 construct a separating circuit 50b. In other words, the switch group 54, the synchronization signal generating circuit 56 and the switch control circuit 57 are in the inside of the housing of the separating circuit 50b.
In a case that the synchronization signal S2b is selected and that the pulse of the synchronization signal S2b is in the high level interval, the switch group 54 closes the n-th switch 54(n); in a case that the synchronization signal S2b is selected and that the pulse of the synchronization signal S2b is in the low level interval, the switch group 54 opens the n-th switch 54(n). The electric charge, which is applied to the individual electrode 85 in a case that the n-th switch 54(n) is closed, is held by the first capacitor 89a and the second capacitor 89b. As depicted in
In a case that the synchronization signal S2c is selected and that the pulse of the synchronization signal S2c is in the high level interval, the switch group 54 closes the n-th switch 54(n); in a case that the synchronization signal S2c is selected and that the pulse of the synchronization signal S2c is in the low level interval, the switch group 54 opens the n-th switch 54(n). The electric charge, which is applied to the individual electrode 85 in a case that the n-th switch 54(n) is closed, is held by the first capacitor 89a and the second capacitor 89b. As depicted in
The predetermined sampling frequency as described above is not less than a resonance frequency of the inkjet head 8, and is, for example, 24 kHz. Further, the inkjet head 8 includes the separating circuit 50b and an FPC (Flexible Printed Circuits, not depicted). For example, the separating circuit 50b is provided on the FPC connected to the inkjet head 8. Since the inkjet head 8 includes the separating circuit 50b, the driving waveform signal Pa, the driving waveform signal Pb, and the driving waveform signal Pc separated from the time division multiplex signal may be transmitted only using a signal line of a few centimeters. Therefore, blunting, etc., of the driving waveform signal Pa, the driving waveform signal Pb and the driving waveform signal Pc can be suppressed.
The controller 50 determines whether the flushing processing is completed (step S5). In a case that the flushing processing is not completed (step S5: NO), the controller 50 returns the processing to Step S5. In a case that the flushing processing is completed (step S5: YES), the controller 50 enters into to a standby state (step S6), and ends the processing. The controller 50 stands by in the standby state until, for example, a print job is received.
The controller 50 executes one printing task (step S13). The term “printing task” is a unit constructing the print job. Specifically, the printing task is a liquid discharging processing performed during a period of time in which the ink-jet head 8 is (being) moved rightward or leftward in an amount corresponding to a width in the left-right direction of the recording paper 200. Subsequently, the controller 50 determines whether or not one printing task is completed (step S14). Note that the carriage 6 performs one movement in one printing task. In a case that one printing task is not completed (step S14: NO), the controller 50 returns the processing to Step S14. In a case that one printing task is completed (step S14: YES), the controller 50 determines whether or not the print job is completed (step S15).
In a case that the print job is completed (step S15: YES), the controller 50 executes the flushing processing (step S20) and ends the printing processing. In a case that the print job is not completed (step S15: NO), the controller 50 determines whether or not it is a timing to execute the flushing processing (step S16). The flushing processing is periodically executed for the purpose of the maintenance of the nozzles 80. In a case that it is the timing to execute the flushing processing (step S16: YES), the controller 50 transmits the generation instruction signal from the controlling circuit 51 to the synchronization signal generating circuit 56 (step S17), generates the synchronization signal in the synchronization signal generating circuit 56 (step S18), and executes the flushing processing (step S19). After the controller 50 executes the flushing processing, the controller 50 returns the processing to Step S13. As a result, even in a case that the synchronization signal generated by the synchronization signal generating circuit 56 is deviated, the generation instruction signal is transmitted from the control circuit 51 to the synchronization signal generating circuit 56 at the timing of the flushing processing, thereby making it possible to correct the deviation of the synchronization signal generated by the synchronization signal generating circuit 56. In a case that it is not the timing to execute the flushing processing (step S16: NO), the controller 50 determines whether or not it is a timing to execute a undischarge flushing processing (step S21).
The undischarge flushing processing is a processing to be performed in order to prevent the nozzles 80 from drying without performing the discharge of the ink. In particular, the undischarge flushing processing is a processing in which the piezoelectric member 83 is slightly deformed to vibrate or shake the surface (meniscus) of the ink. For example, the undischarge flushing processing is executed in the cap 20. The undischarge flushing is periodically executed. In a case that it is the timing to execute the undischarge flushing processing (step S21: YES), the controller 50 transmits the generation instruction signal from the control circuit 51 to the synchronization signal generating circuit 56 (step S22), generates the synchronization signal in the synchronization signal generating circuit 56 (step S23), and executes the undischarge flushing processing (step S24). In Step S24, the controller 50 supplies a driving waveform corresponding to the undischarge flushing processing to the individual electrode 85. After the controller 50 executes the undischarge flushing processing, the controller 50 returns the processing to Step S13. As a result, even in a case that the synchronization signal generated by the synchronization signal generating circuit 56 is deviated, the generation instruction signal is transmitted from the control circuit 51 to the synchronization signal generating circuit 56 at the timing of the undischarge flushing processing, thereby making it possible to correct the deviation of the synchronization signal generated by the synchronization signal generating circuit 56. In a case that it is not the timing to execute the undischarge flushing processing (step S21: NO), the controller 50 returns the processing to Step S13.
The controller 50 may perform the generation of the time division multiplex signal and the separation of the driving waveform signal at either one of the time of executing the flushing processing (steps S4, S12, S19, S20) and the time of executing the undischarge flushing processing (step S24). That is, the generation of the time division multiplex signal and the separation of the driving waveform signal may be performed in a case that the actuator 88 is (being) driven.
A second embodiment of the present disclosure will be explained below, on the basis of the drawing which depicts a printing apparatus 1 according to the second embodiment. Constitutive components according to the second embodiment, which are the same as or equivalent to the constitutive components according to the first embodiment, are designated by the same reference numerals as those of the first embodiment, and any detailed explanation will be omitted.
In the controller 50 according to the first embodiment, the signal line W for transmitting the generation instruction signal S3 is the dedicated line which transmits only the generation instruction signal S3 and does not transmit any other signals. However, the controlling circuit 51 may transmit the generation instruction signal S3 to the synchronization signal generating circuit 56, by using a signal line for transmitting the time division multiplex signal. That is, as depicted in
A third embodiment of the present disclosure will be explained below on the basis of the drawing which depicts a printing apparatus 1 according to the third embodiment. Constitutive components according to the third embodiment, which are the same as or equivalent to the constitutive components according to the first embodiment, are designated by the same reference numerals as those of the first embodiment, and any detailed explanation will be omitted.
In the controller 50 according to the first embodiment, the signal line W for transmitting the generation instruction signal S3 is the dedicated line which transmits only the generation instruction signal S3 and does not transmit any other signals. However, the controlling circuit 51 may transmit the generation instruction signal S3 to the synchronization signal generating circuit 56, by using a signal line for transmitting the switch control signal S1. That is, as depicted in
A fourth embodiment of the present disclosure will be explained below on the basis of the drawing which depicts a printing apparatus 1 according to the fourth embodiment. Constitutive components according to the fourth embodiment, which are the same as or equivalent to the constitutive components according to the first embodiment, are designated by the same reference numerals as those of the first embodiment, and any detailed explanation will be omitted.
In the controller 50 according to the first embodiment, the synchronization signal generating circuit 56 is arranged in the inside of the housing of the separating circuit 50b, but the synchronization signal generating circuit 56 may be arranged at the outside of the housing of the separating circuit 50b as depicted in
A fifth embodiment of the present disclosure will be explained below on the basis of the drawing which depicts a printing apparatus 1 according to the fifth embodiment. Any detailed explanation on processes according to the fifth embodiment, which are the same as or equivalent to the processes according to the first embodiment, will be omitted.
In the first embodiment, the controller 50 transmits the generation instruction signal from the control circuit 51 to the synchronization signal generating circuit 56 at the flushing processing execution timing or at the undischarge flushing processing execution timing during printing, and generates the synchronization signal in the synchronization signal generating circuit 56. However, the timing of performing the transmitting of the generation instruction signal and the generation of the synchronization signal is not limited to this. It is allowable, for example, to set the above-described timing before the execution of one print task or after the completion of the print job.
As depicted in
Next, the controller 50 determines whether or not one printing task is completed (step S35). In a case that one printing task is not completed (step S35: NO), the controller 50 returns the processing to Step S35. In a case that one printing task is completed (step S35: YES), the controller 50 determines whether or not the print job is completed (step S36).
In a case that the print job is completed (step S36: YES), the controller 50 transmits the generation instruction signal from the control circuit 51 to the synchronization signal generating circuit 56 (step S39). The controller 50 generates the synchronization signal in the synchronization signal generating circuit 56 (step S40), executes the flushing processing (step S41), and ends the printing processing. In a case that the print job is not completed (step S36: NO), the controller 50 determines whether or not it is the timing to execute the flushing processing (step S37). In a case that it is the timing to execute the flushing processing (step S37: YES), the controller 50 executes the flushing processing (step S38) and returns the processing to Step S32. In a case that it is not the timing to execute the flushing processing (step S37: NO), the controller 50 determines whether or not it is the timing to execute the undischarge flushing processing (step S42).
In a case that it is the timing to execute the undischarge flushing processing (step S42: YES), the controller 50 executes the undischarge flushing processing (step S43), and returns the processing to Step S32. In a case that it is not the timing to execute the undischarge flushing processing (step S42: NO), the controller 50 returns the processing to Step S32.
A sixth embodiment of the present disclosure will be explained below on the basis of the drawings which depict a printing apparatus 1 according to the sixth embodiment. Constitutive components according to the sixth embodiment, which are the same as or equivalent to the constitutive components according to the first embodiment, are designated by the same reference numerals as those of the first embodiment, and any detailed explanation will be omitted.
The printing apparatus 1 in each of the above-described embodiments is a serial head type printing apparatus in which the inkjet head 8 is moved by the carriage 6. It is allowable, however, that the printing apparatus 1 is a line head type printing apparatus which performs printing in a state that the inkjet head 8 is fixed. As depicted in
The second substrate 950 includes a FPGA 951 as a controller, a non-volatile memory 952 such as an EEPROM, a digital-analog converter (D/A converter) 920, a first power supply circuit 921, a second power supply circuit 922, a third power supply circuit 923, a fourth power supply circuit 924, a fifth power supply circuit 925, a sixth power supply circuit 926, a synchronization signal generating circuit 956, etc. Further, the flexible circuit board 960 includes a non-volatile memory 962 such as an EEPROM, a driver IC 927, etc. Note that the separating circuit is constructed of the driver IC 927.
Under the control of a FPGA 51a provided on a first substrate 5a of the controller 50, the FPGA 951 transmits a time division multiplex signal, which is generated by the FPGA 51a by reading the driving waveform data from the memory 55 and which is transmitted to the FPGA 951, to the driver IC 927 via a signal line 933. That is, the signal generating circuit (multiplexing circuit, multiplexer) is constructed of the FPGA 51a and the memory 55. Further, the FPGA 951 transmits the generation instruction signal S3 to the synchronization signal generating circuit 956, and the synchronization signal generating circuit 956 transmits the synchronization signal S2 to the driver IC 927.
The FPGA 951 transmits a setting signal, which is an analog signal for setting the output voltage of each of the first power supply circuit 921 to the sixth power supply circuit 926, via the digital-analog converter 920 under the control of FPGA 51a provided on the first substrate 5a of the controller 50. Each of the power supply circuits 921 to 926 outputs an output voltage designated by the setting signal to the driver IC 927 via one of wirings VDD1 to VDD5 and a wiring HVDD.
The FPGA 951 transmits, via a control line 940 to the driver IC 927, a control signal for selecting the power supply circuit and a synchronization signal S2 used for generating a driving signal to be transmitted to each of signal lines 934(n) (n=1, 2, . . . N). The driver IC 927 transmits the driving signal to the individual electrode 85 (see
In a case that the synchronization signal generating circuit 956 is arranged at the outside of the separating circuit (driver IC 927) as depicted in
A seventh embodiment of the present disclosure will be explained below on the basis of the drawing which depicts a printing apparatus 1 according to the seventh embodiment. Constitutive components according to the seventh embodiment, which are the same as or equivalent to the constitutive components according to the first embodiment, are designated by the same reference numerals as those of the first embodiment, and any detailed explanation will be omitted.
In each of the embodiments described above, the synchronization signal S2 is generated by delaying the rising edge (time point of the rising edge) of the generation instruction signal S3 by a predetermined time period. However, a method of generating the synchronization signal S2 is not limited thereto. In the seventh embodiment, the separating circuit 50b includes a memory 55a storing the synchronization signal table 551. The synchronization signal generating circuit 56 generates the synchronization signal S2 on the basis of the synchronization signal table 551. Note that the memory 55a may be arranged at the outside of the separating circuit 50b, for example, on a carriage or on a head bar.
The memory 55a is a volatile memory such as DRAM, SRAM, and the like. Note that, the memory 55a may be a nonvolatile memory. The control circuit 51 transmits the synchronization signal table 551, which has been read out from the external device 100 or undepicted nonvolatile memory, to the memory 55a as a storing instruction signal S4 when, for example, the main power supply of the printing apparatus 1 is turned on. When the storing instruction signal S4 is transmitted to the memory 55a from the control circuit 51, the memory 55a stores the synchronization signal table 551. Note that, the control circuit 51 may update the synchronization signal table 551 stored in the memory 55a by reading out the synchronization signal table 551 from the external device 100 or the undepicted volatile memory periodically and transmitting the read synchronization signal table 551 to the memory 55a periodically. In the example depicted in
As depicted in
When the generation instruction signal S3 is transmitted from the control circuit 51 to the synchronization signal generating circuit 56, the synchronization signal generation circuit 56 reads out the synchronization signal table 551 from the memory 55a, and then generates the synchronization signal S2 on the basis of the generation instruction signal S3 and the synchronization signal table 551. Specifically, the synchronization signal generating circuit 56 generates each of the synchronization signals S2 (see,
In the first embodiment, the generation instruction signal is transmitted from the control circuit 51 to the synchronization signal generating circuit 56 at the timing of the undischarge flushing processing, but the present disclosure is not limited to this. It is allowable that a detection circuit which detects a deviation in the synchronization signal generated by the synchronization signal generating circuit 56 is provided; that in a case that the detection circuit detects the deviation in the synchronization signal generated by the synchronization signal generating circuit 56, the detection circuit transmits a signal to the control circuit 51; and that the generation instruction signal S3 is transmitted from the control circuit 51 to the synchronization signal generating circuit 56.
The embodiments disclosed herein are exemplary in all senses, and should be interpreted not restrictive or limiting in any way. The technical features described in the respective embodiments can be combined with each other, and the scope of the present invention is intended to encompass all the changes within the scope of the claims and a scope equivalent to the scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-151376 | Sep 2021 | JP | national |
| 2022-073449 | Apr 2022 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20170113461 | Netsu et al. | Apr 2017 | A1 |
| 20230311490 | Maeda | Oct 2023 | A1 |
| Number | Date | Country |
|---|---|---|
| S5888469 | Jun 1983 | JP |
| 2010142978 | Jul 2010 | JP |
| 2017080891 | May 2017 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20230083297 A1 | Mar 2023 | US |
