Patent Grant
12162279
This application claims priority from Japanese Patent Application No. 2021-161820 filed on Sep. 30, 2021. The entire content of the priority application is incorporated herein by reference.
There is a printer which generates first to fourth driving pulses having different amplitudes, as driving signals for driving a piezoelectric element of each of nozzles. The first to fourth driving pulses are continuously generated during one cycle for printing one pixel. One of the first to fourth driving pulses is selected and applied to the piezoelectric element of each of the nozzles. Each of the nozzles discharges or ejects an ink in an amount corresponding to the amplitude of the selected driving pulse so as to form a dot having a desired size.
According to a first aspect of the present disclosure, there is provided a printing apparatus including:
The energy generating element is configured to be driven by the driving waveform signal separated by the separator.
According to a second aspect of the present disclosure, there is provided a printing apparatus including:
Both a first period of time and a second period of time are included in a same one cycle of the time division multiplex signal.
The second period of time is different from the first period of time.
A number of the data to be used by the signal generator so as to generate the time division multiplex signal during the first period of time is smaller than a number of the data to be used by the signal generator so as to generate the time division multiplex signal during the second period of time.
The energy generating element is configured to be driven by the driving waveform signal separated by the separator.
In the above-described printer, although the four driving pulses are continuously generated during one cycle, only one driving pulse is selected. On this account, the time, which is allotted to the three driving pulses that are not selected, is the waiting time of the nozzle.
The present disclosure has been made taking the foregoing circumstances into consideration, an object of which is to provide a printing apparatus which is capable of reducing the waiting time of a nozzle by adjusting the amplitude of a driving waveform applied to an energy generating element (energy application element).
In the printing apparatus according to an aspect of the present disclosure, the time division multiplex signal is generated based on the plurality of pieces of data each indicating one of the driving waveforms which are mutually different. The driving waveform signal which corresponds to any one of the mutually different driving signals is separated from the generated time division multiplex signal. The energy generating element is configured to be driven by the separated driving waveform signal. By separating any one of the driving waveform signals, it is possible to adjust the shape of the driving waveform to be applied to the energy generating element. Further, the one cycle for printing one pixel includes only a cycle of any one of the driving waveforms, and does not include a cycle of another waveform. Accordingly, it is possible to reduce the waiting time of the nozzle.
A first embodiment of the present disclosure will be explained below on the basis of the drawings depicting a printing apparatus according to the first embodiment.
As depicted in
Two guide rails 11, 12, which guide the carriage 6 and which extend in the left-right direction, are provided over or above the platen 2. An endless belt 13, which extends in the left-right direction, is connected to the carriage 6. The endless belt 13 is driven by a carriage driving motor 14. The carriage 6 is reciprocatively moved in the moving direction in an area opposed to or facing the platen 2 while being guided by the guide rails 11, 12 in accordance with the driving of the endless belt 13. More specifically, the carriage 6 performs a first movement in which the carriage 6 moves the heads 8 from a certain position to another position from the left to the right in the moving direction, and a second movement in which the carriage 6 moves the heads 8 from the another position to the certain position from the right to the left in the moving direction, in a state in which the carriage 6 supports the four ink-jet heads 8.
A cap 20 and a flushing receiver 21 are provided between the guide rails 11, 12. The cap 20 and the flushing receiver 21 are arranged under or below the ink discharge device 3. The cap 20 is arranged at right end portions of the guide rails 11, 12, and the flushing receiver 21 is arranged at left end portions of the guide rails 11, 12. Note that the cap 20 may be arranged at the left end portions of the guide rails 11 and 12 and that the flushing receiver 21 may be arranged at the right end portions of the guide rails 11 and 12.
The subtank 7 and the four ink-jet heads 8 are carried on the carriage 6, and the subtank 7 and the four ink-jet heads 8 are reciprocatively moved (reciprocate) in the moving direction together with the carriage 6. The subtank 7 is connected to a cartridge holder 15 via tubes 17. An ink cartridge 16 of one color or ink cartridges 16 of a plurality of colors (four colors in this embodiment) is/are installed to the cartridge holder 15. The four colors are exemplified, for example, by black, yellow, cyan, and magenta.
Four ink chambers (not depicted) are formed at the inside of the subtank 7. The four color inks, which are supplied from the four ink cartridges 16, are stored in the four ink chambers respectively.
The four ink-jet heads 8 are arranged side by side in the moving direction on the lower side of the subtank 7. A plurality of nozzles 80 (see
The ink-jet head 8 is provided with an ink supply port (not depicted in the drawings) and an ink discharge port (not depicted in the drawings). The ink supply port and the ink discharge port are connected to the ink chamber of the subtank 7, for example, via tubes. A circulating pump (not depicted in the drawings) intervenes between the ink supply port and the ink chamber.
The ink, which is fed from the ink chamber of the subtank 7 by the circulating pump, passes through the ink supply port to flow into the ink-jet head 8, and the ink is discharged (ejected) from the nozzles 80. The ink, which has not been discharged from the nozzles 80, passes through the ink discharge port, and the ink returns to the ink chamber of the subtank 7. The ink is circulated between the ink chamber of the subtank 7 and the ink-jet head 8. The four ink-jet heads 8 discharge the four color inks supplied from the subtank 7 onto the recording paper 200, while being moved in the moving direction together with the carriage 6.
As depicted in
A second common electrode 86 is provided at the inside of the piezoelectric member 83. The second common electrode 86 is arranged on the upper side of each of the pressure chambers 81 and on the upper side of the first common electrode 84. The second common electrode 86 is arranged at a position at which the second common electrode 86 does not face (is not opposed to) the first common electrode 84. An individual electrode 85 is formed on the upper surface of the piezoelectric member 83, at a location on the upper side of each of the plurality of pressure chambers 81. The individual electrode 85 vertically faces the first common electrode 84 and the second common electrode 86 with the piezoelectric member 83 intervening therebetween. The vibration plate 82, the piezoelectric member 83, the first common electrode 84, the individual electrode 85, and the second common electrode 86 constitute an actuator 88.
A nozzle plate 87 is provided under or below the respective pressure chambers 81. A plurality of nozzles 80, which vertically penetrate, are formed through the nozzle plate 87. Each of the plurality of nozzles 80 is arranged on the lower side of each of the plurality of pressure chambers 81. The plurality of nozzles 80 constitute a plurality of nozzle arrays which extend, respectively, along the pressure chamber arrays.
The first common electrode 84 is connected to a COM terminal, i.e., the ground in this embodiment. The second common electrode 86 is connected to a VCOM terminal. The VCOM voltage is higher than the COM voltage. The individual electrode 85 is connected to a switch group 54 (see
The digital-analogue converter 52 converts a digital signal into an analog signal. The amplifier 53 amplifies the analog signal. The switch group 54 is provided with a plurality of n-th switches 54(n) (n=1, 2, . . . , N). Each of the plurality of n-th switches 54(n) is constructed, for example, by an analog switch IC. One end of each of the plurality of nth switches 54(n) is connected to the amplifier 53 via a common bus. The other end of each of the plurality of n-th switches 54(n) is connected to the individual electrode 85 which corresponds to one of the plurality of nozzles 80. In other words, one piece of the n-th switch 54(n) is provided with respect to one piece of the actuator 88.
A first capacitor 89a is constructed by the individual electrode 85, the first common electrode 84, and the piezoelectric member 83. A second capacitor 89b is constructed by the individual electrode 85, the second common electrode 86, and the piezoelectric member 83.
Driving waveform data Da to Dd are stored, respectively, in the memories 55a to 55d. Each of the driving waveform data Da to Dd is data indicating a voltage waveform to be applied to the individual electrode 85, namely, a driving waveform for driving the actuator 88, and is quantized data. The respective driving waveform data Da to Dd indicate mutually different driving waveforms.
The memory 55b stores the driving waveform data Db. The driving waveform data Db includes the time table Ttb and the voltage table Tvb. In the time table Ttb, a time tb(X) associated with the address X is stored. In the present embodiment, tb(0) to tb(4) are, respectively, 4 μs, 1 μs, 9 μs, 1 μs and 5 μs. In the voltage table Tvb, a voltage value Vb(X) associated with the address X is stored. In the present embodiment, Vb(0) to Vb(4) are, respectively, 0, V1, V2, V1 and 0.
The memory 55c stores the driving waveform data Dc. The driving waveform data Dc includes the time table Ttc and the voltage table Tvc. In the time table Ttc, a time tc(X) associated with the address X is stored. In the present embodiment, tc(0) to tc(4) are, respectively, 2 μs, 1 μs, 5 μs, 1 μs and 11 μs. In the voltage table Tvc, a voltage value Vc(X) associated with the address X is stored. In the present embodiment, Vc(0) to Vc(4) are, respectively, 0, V1, V2, V1 and 0.
The memory 55d stores the driving waveform data Dd. The driving waveform data Dd includes the time table Ttd and the voltage table Tvd. In the time table Ttd, a time td(X) associated with the address X is stored. In the present embodiment, td(0) to td(4) are, respectively, 8 μs, 1 μs, 5 μs, 1 μs and 5 μs. In the voltage table Tvd, a voltage value Vd(X) associated with the address X is stored. In the present embodiment, Vd(0) to Vd(4) are, respectively, 0, V1, V2, V1 and 0.
The CPU 51a causes the memory 55a to output, to the counter 56a, the times of the time table Tta in the order of the address, and causes the memory 55a to output, to the selector circuit 60 and the comparing circuit 57, the voltages of the voltage table Tva in the order of the address. For example, the memory 55a stores the address X as a parameter. The CPU 51a sets the address X to be 0 (zero). The memory 55a refers to the address 0, and outputs ta(0) of the time table Tta, namely, 2 μs, to the counter 56a; the counter 56a, into which ta(0) is inputted, outputs a comparison timing signal Sa to the comparing circuit 57. The counter 56a measures the inputted time 2 μs, and after the measurement, the counter 56a outputs an address increment signal Spa to the memory 55a. In a case that the address increment signal Spa is inputted to the memory 55a, the memory 55a increments the address X by 1 (one), refers to the address 1, and outputs ta(1) of the time table Tta, namely, 1 μs, to the counter 56a. The counter 56a, into which ta(1) is inputted, outputs the comparison timing signal Sa to the comparing circuit 57. In such a manner, every time the time ta(X) is inputted from the time table Tta, the counter 56a outputs the comparison timing signal Sa to the comparing circuit 57; every time the counter 56a completes the measurement of the time ta(X), the counter 56a outputs the address increment signal Spa to the memory 55a.
In a case that the CPU 51a sets the address X to be 0 (zero), the memory 55a outputs the voltage value Va(0) of the voltage table Tva, namely 0 (zero), to the selector circuit 60 and the comparing circuit 57. Afterwards, in a case that the address increment signal Spa is inputted to the memory 55a, the memory 55a increments the address X by 1 (one), and outputs the voltage value Va(1), namely V1, to the selector circuit 60 and the comparing circuit 57. In such a manner, in a case that the address X is set to be 0 (zero) and every time the address increment signal Spa is inputted to the memory 55a, the memory 55a outputs the voltage value of the voltage table Tva to the selector circuit 60 and the comparing circuit 57. Namely, the memory 55a outputs the voltage value of the voltage table Tva, in the order of address, to the selector circuit 60 and the comparing circuit 57.
Similarly, the CPU 51a causes the memory 55b to 55d to output, respectively, the times tb(X) to td(X) of the time table Tta to Ttd to the counters 56b to 56d, respectively, in the order of address; the counters 56b to 56d output, respectively, the timing signals Sb to Sd to the comparing circuit 57 every time the times tb(X) to td(X) are inputted, respectively, to the counter 56b to 56d. Every time the time corresponding to the address X lapses, the counters 56b to 56d output, respectively, the address increment signals SPb to Spd to the memories 55b to 55d, respectively.
Similarly, in a case that the address X is set to be 0 (zero) and every time the address increment signals Spb to Spd are inputted to the memories 55b to 55d, respectively, the memories 55b to 55d output, respectively, the voltage values Vb(X) to Vd(X) of the voltage table Tva to Tvd to the selector circuit 60 and the comparing circuit 57. Namely, the memories 55b to 55d output, respectively, the voltage values Vb(X) to Vd(X) to the selector circuit 60 and the comparing circuit 57, in the order of address.
An upper view of
A middle view of
Further, the quantized data A0 is continuous with the quantized data B0, the quantized data B0 is continuous with the quantized data C0, and the quantized data C0 is continuous with the quantized data D0. In other words, the quantized data C0, the quantized data D0, any other quantized data, and any data of any other waveform are absent between the quantized data A0 and the quantized data B0. Further, the quantized data A0, the quantized data D0, any other quantized data, and any data of any other waveform are absent between the quantized data B0 and the quantized data C0. Further, the quantized data A0, the quantized data B0, any other quantized data, and any data of any other waveform are absent between the quantized data C0 and the quantized data D0.
The control circuit 51 outputs the time series data to the digital-analogue converter 52. As depicted in
As indicated in
TS1 to TS10 are classified into mutually different four sampling frequencies wherein TS1 corresponds to a first sampling frequency, TS2 and TS3 correspond to a second sampling frequency, TS4 to TS6 correspond to a third sampling frequency, and TS7 to TS10 correspond to a fourth sampling frequency. For example, in a case that the fourth sampling frequency corresponds to 24 MHz, the third sampling frequency corresponds to 18 MHz, the second sampling frequency corresponds to 12 MHz and the first sampling frequency corresponds to 6 MHz.
In a case that any one of the comparison timing signals Sa to Sd is inputted to the comparing circuit 57, the comparing circuit 57 compares the voltage values inputted, respectively, from the voltage tables Tva to Tvd. The points of time at which any one of the comparison timing signals Sa to Sd is inputted to the comparing circuit 57 are the points of time 0 (zero), 2, 3, 4, 5, 8, 9, 14, 15, 17 and 18 in the upper view of
In a case that there are four same voltage values, TS1 is allocated to each of the four same voltage values. In a case that there are three same voltage values, TS2 is allocated to each of the three same voltage values, and T3 is allocated to a remaining one voltage value; or TS3 is allocated to each of the three same voltage values, and T2 is allocated to a remaining one voltage value.
In a case that there are two same voltage values and that remaining two voltage values are mutually different, TS4 is allocated to each of the two same voltage values, and T5 and TS6 are allocated to remaining two voltage values, respectively; or TS5 is allocated to each of the two same voltage values, and T4 and TS6 are allocated to remaining two voltage values, respectively; or TS6 is allocated to each of the two same voltage values, and T4 and TS5 are allocated to remaining two voltage values, respectively.
In a case that two voltage values are a first voltage value, that remaining two voltage values are a second voltage value and that the first voltage value and the second voltage value are different from each other, TS2 is allocated to the first voltage value, and TS3 is allocated to the second voltage value.
In a case that four voltage values are mutually different, TS7 to TS10 are allocated, respectively, to the four different voltage values.
The comparing circuit 57 associates the time slots with the respective voltage values Va(X) to Vd(X), and outputs the time slots and the respective voltage values Va(X) to Vd(X) which are associated with each other to the switching circuit 59 and the respective synchronization signal generating circuits 62a to 62d. The frequency generating circuit 58 generates a reference frequency (24 MHz in the present embodiment), and outputs the reference frequency to the switching circuit 59 and the respective synchronization signal generating circuits 62a to 62d.
For example, as depicted in the upper view of
In a case that the switching circuit 59 selects one voltage value, the switching circuit 59 generates a frequency of 6 MHz based on the reference frequency and TS1. The switching circuit 59 associates TS1, the frequency of 6 MHz and the voltage value Va(X) with each other, and outputs TS1, the frequency of 6 MHz and the voltage value Va(X) which are associated with each other to the selector circuit 60. As depicted in the middle view of
For example, as depicted in the upper view of
As depicted in the middle view of
For example, as depicted in the upper view of
As depicted in the middle view of
For example, as depicted in the upper view of
As depicted in the middle view of
As described above, the voltage value used for generating the time division multiplex signal during the period of time from the point of time 0 to the point of time 1 μs included in one cycle of the time division multiplex signal is only the voltage value Va(X). In other words, the number (quantity) of the driving waveform data to be used is 1 (one). The voltage value used for generating the time division multiplex signal during the period of time from the point of time 2 μs to the point of time 3 μs included in the one cycle is the voltage values Va(X) and Vb(X). In other words, the number (quantity) of the driving waveform data to be used is 2 (two). The voltage value used for generating the time division multiplex signal during the period of time from the point of time 4 μs to the point of time 5 μs included in the one cycle is the voltage values Va(X), Vb(X) and Vd(X). In other words, the number (quantity) of the driving waveform data to be used is 3 (three).
The selector circuit 60 outputs the respective signals generated to the multiplex signal outputting circuit 61; and the multiplex signal outputting circuit 61 outputs the time division multiplex signal to the digital-analog convertor 52 (see the middle view of
As described above, the frequency generating circuit 58 outputs the reference frequency to the respective synchronization signal generating circuits 62a to 62d; and the comparing circuit 57 associates the time slots and the respective voltage values Va(X) to Vd(X), and outputs the time slots and the respective voltage values Va(X) to Vd(X) which are associated with each other to the respective synchronization signal generating circuits 62a to 62d.
As depicted in the lower view of
The time slot associated with the voltage value Va(X) is TS2 during a period of time from the point of time 5 to the point of time 8; the synchronization signal A is in a state of the high level during a period of time from the point of time 5 to the point of time 5.5, and is in a state of the low level during a period of time from the point of time 5.5 to the point of time 6. The synchronization signal A is in a state of the high level during a period of time from the point of time 6 to the point of time 6.5, and is in a state of the low level during a period of time from the point of time 6.5 to the point of time 7. The synchronization signal A is in a state of the high level during a period of time from the point of time 7 to the point of time 7.5, and is in a state of the low level during a period of time from the point of time 7.5 to the point of time 8. The time slot associated with the voltage value Va(X) is TS3 during a period of time from the point of time 8 to the point of time 9; the synchronization signal A is in a state of the low level during a period of time from the point of time 8 to the point of time 8.5, and is in a state of the high level during a period of time from the point of time 8.5 to the point of time 9. The time slot associated with the voltage value Va(X) is TS3 during a period of time from the point of time 9 to the point of time 14; the synchronization signal A is in a state of the low level during a period of time from the point of time 9 to the point of time 9.5, and is in a state of the high level during a period of time from the point of time 9.5 to the point of time 10. The synchronization signal A is in a state of the low level during a period of time from the point of time 10 to the point of time 10.5, and is in a state of the high level during a period of time from the point of time 10.5 to the point of time 11. The synchronization signal A is in a state of the low level during a period of time from the point of time 11 to the point of time 11.5, and is in a state of the high level during a period of time from the point of time 11.5 to the point of time 12. The synchronization signal A is in a state of the low level during a period of time from the point of time 12 to the point of time 12.5, and is in a state of the high level during a period of time from the point of time 12.5 to the point of time 13. The synchronization signal A is in a state of the low level during a period of time from the point of time 13 to the point of time 13.5, and is in a state of the high level during a period of time from the point of time 13.5 to the point of time 14.
The time slot associated with the voltage value Va(X) is TS2 during a period of time from the point of time 14 to the point of time 18; the synchronization signal A is in a state of the high level during a period of time from the point of time 14 to the point of time 14.5 and is in a state of the low level during a period of time from the point of time 14.5 to the point of time 15. The synchronization signal A is in a state of the high level during a period of time from the point of time 15 to the point of time 15.5 and is in a state of the low level during a period of time from the point of time 15.5 to the point of time 16. The synchronization signal A is in a state of the high level during a period of time from the point of time 16 to the point of time 16.5, and is in a state of the low level during a period of time from the point of time 16.5 to the point of time 17. The synchronization signal A is in a state of the high level during a period of time from the point of time 17 to the point of time 17.5, and is in a state of the low level during a period of time from the point of time 17.5 to the point of time 18. The time slot associated with the voltage value Va(X) is TS1 during a period of time from the point of time 18 to the point of time 20; the synchronization signal A is in a state of the high level during the period of time from the point of time 18 to the point of time 20. Namely, the driving waveform signal is separated from the time division multiplex signal based on the first sampling frequency, the second sampling frequency or the third sampling frequency corresponding to the respective periods of time. Each of during the period of time from the point of time 0 to the point of time 2.5, during the period of time from the point of time 13.5 to the point of time 14.5, and during the period of time from the point of time 18 to the point of time 20, the synchronization signal A is continuously in the state of the high level.
As depicted in the upper view of
The time slot associated with the voltage value Vb(X) is TS2 during a period of time from the point of time 5 to the point of time 15; the synchronization signal B is in a state of the high level during a period of time from the point of time 5 to the point of time 5.5, and is in a state of the low level during a period of time from the point of time 5.5 to the point of time 6. The synchronization signal B is in a state of the high level during a period of time from the point of time 6 to the point of time 6.5, and is in a state of the low level during a period of time from the point of time 6.5 to the point of time 7. The synchronization signal B is in a state of the high level during a period of time from the point of time 7 to the point of time 7.5, and is in a state of the low level during a period of time from the point of time 7.5 to the point of time 8. The synchronization signal B is in a state of the high level during a period of time from the point of time 8 to the point of time 8.5, and is in a state of the low level during a period of time from the point of time 8.5 to the point of time 9. The synchronization signal B is in a state of the high level during a period of time from the point of time 9 to the point of time 9.5, and is in a state of the low level during a period of time from the point of time 9.5 to the point of time 10. The synchronization signal B is in a state of the high level during a period of time from the point of time 10 to the point of time 10.5, and is in a state of the low level during a period of time from the point of time 10.5 to the point of time 11. The synchronization signal B is in a state of the high level during a period of time from the point of time 11 to the point of time 11.5, and is in a state of the low level during a period of time from the point of time 11.5 to the point of time 12. The synchronization signal B is in a state of the high level during a period of time from the point of time 12 to the point of time 12.5, and is in a state of the low level during a period of time from the point of time 12.5 to the point of time 13. The synchronization signal B is in a state of the high level during a period of time from the point of time 13 to the point of time 13.5, and is in a state of the low level during a period of time from the point of time 13.5 to the point of time 14. The synchronization signal B is in a state of the high level during a period of time from the point of time 14 to the point of time 14.5, and is in a state of the low level during a period of time from the point of time 14.5 to the point of time 15.
The time slot associated with the voltage value Vb(X) is TS3 during a period of time from the point of time 15 to the point of time 18; the synchronization signal B is in a state of the low level during a period of time from the point of time 15 to the point of time 15.5, and is in a state of the high level during a period of time from the point of time 15.5 to the point of time 16. The synchronization signal B is in a state of the low level during a period of time from the point of time 16 to the point of time 16.5, and is in a state of the high level during a period of time from the point of time 16.5 to the point of time 17. The synchronization signal B is in a state of the low level during a period of time from the point of time 17 to the point of time 17.5, and is in a state of the high level during a period of time from the point of time 17.5 to the point of time 18. The time slot associated with the voltage value Vb(X) is TS1 during a period of time from the point of time 18 to the point of time 20; and the synchronization signal B is in a state of the high level during the period of time from the point of time 18 to the point of time 20. Namely, the driving waveform signal is separated from the time division multiplex signal based on the first sampling frequency, the second sampling frequency, the third sampling frequency or the fourth sampling frequency corresponding to the respective periods of time. Each of during the period of time from the point of time 0 to the point of time 2 and during the period of time from the point of time 17.5 to the point of time 20, the synchronization signal B is continuously in the state of the high level.
As depicted in the middle view of
The time slot associated with the voltage value Vc(X) is TS2 during a period of time from the point of time 5 to the point of time 8; the synchronization signal C is in a state of the high level during a period of time from the point of time 5 to the point of time 5.5, and is in a state of the low level during a period of time from the point of time 5.5 to the point of time 6. The synchronization signal C is in a state of the high level during a period of time from the point of time 6 to the point of time 6.5, and is in a state of the low level during a period of time from the point of time 6.5 to the point of time 7. The synchronization signal C is in a state of the high level during a period of time from the point of time 7 to the point of time 7.5, and is in a state of the low level during a period of time from the point of time 7.5 to the point of time 8.
The time slot associated with the voltage value Vc(X) is TS3 during a period of time from the point of time 8 to the point of time 18; the synchronization signal C is in a state of the low level during a period of time from the point of time 8 to the point of time 8.5, and is in a state of the high level during a period of time from the point of time 8.5 to the point of time 9. The synchronization signal C is in a state of the low level during a period of time from the point of time 9 to the point of time 9.5, and is in a state of the high level during a period of time from the point of time 9.5 to the point of time 10. The synchronization signal C is in a state of the low level during a period of time from the point of time 10 to the point of time 10.5, and is in a state of the high level during a period of time from the point of time 10.5 to the point of time 11. The synchronization signal C is in a state of the low level during a period of time from the point of time 11 to the point of time 11.5, and is in a state of the high level during a period of time from the point of time 11.5 to the point of time 12. The synchronization signal C is in a state of the low level during a period of time from the point of time 12 to the point of time 12.5, and is in a state of the high level during a period of time from the point of time 12.5 to the point of time 13. The synchronization signal C is in a state of the low level during a period of time from the point of time 13 to the point of time 13.5, and is in a state of the high level during a period of time from the point of time 13.5 to the point of time 14. The synchronization signal C is in a state of the low level during a period of time from the point of time 14 to the point of time 14.5, and is in a state of the high level during a period of time from the point of time 14.5 to the point of time 15. The synchronization signal C is in a state of the low level during a period of time from the point of time 15 to the point of time 15.5, and is in a state of the high level during a period of time from the point of time 15.5 to the point of time 16. The synchronization signal C is in a state of the low level during a period of time from the point of time 16 to the point of time 16.5, and is in a state of the high level during a period of time from the point of time 16.5 to the point of time 17. The synchronization signal C is in a state of the low level during a period of time from the point of time 17 to the point of time 17.5, and is in a state of the high level during a period of time from the point of time 17.5 to the point of time 18.
The time slot associated with the voltage value Vc(X) is TS1 during a period of time from the point of time 18 to the point of time 20; the synchronization signal C is in a state of the high level during the period of time from the point of time 18 to the point of time 20. Namely, the driving waveform signal is separated from the time division multiplex signal based on the first sampling frequency, the second sampling frequency or the third sampling frequency corresponding to the respective periods of time. Each of during the period of time from the point of time 0 to the point of time 2.5 and during the period of time from the point of time 17.5 to the point of time 20, the synchronization signal C is continuously in the state of the high level.
As depicted in the lower view of
The time slot associated with the voltage value Vd(X) is TS2 during a period of time from the point of time 9 to the point of time 15; the synchronization signal D is in a state of the high level during a period of time from the point of time 9 to the point of time 9.5, and is in a state of the low level during a period of time from the point of time 9.5 to the point of time 10. The synchronization signal D is in a state of the high level during a period of time from the point of time 10 to the point of time 10.5, and is in a state of the low level during a period of time from the point of time 10.5 to the point of time 11. The synchronization signal D is in a state of the high level during a period of time from the point of time 11 to the point of time 11.5, and is in a state of the low level during a period of time from the point of time 11.5 to the point of time 12. The synchronization signal D is in a state of the high level during a period of time from the point of time 12 to the point of time 12.5, and is in a state of the low level during a period of time from the point of time 12.5 to the point of time 13. The synchronization signal D is in a state of the high level during a period of time from the point of time 13 to the point of time 13.5, and is in a state of the low level during a period of time from the point of time 13.5 to the point of time 14. The synchronization signal D is in a state of the high level during a period of time from the point of time 14 to the point of time 14.5, and is in a state of the low level during a period of time from the point of time 14.5 to the point of time 15.
The time slot associated with the voltage value Vd(X) is TS3 during a period of time from the point of time 15 to the point of time 18; the synchronization signal D is in a state of the low level during a period of time from the point of time 15 to the point of time 15.5, and is in a state of the high level during a period of time from the point of time 15.5 to the point of time 16. The synchronization signal D is in a state of the low level during a period of time from the point of time 16 to the point of time 16.5, and is in a state of the high level during a period of time from the point of time 16.5 to the point of time 17. The synchronization signal D is in a state of the low level during a period of time from the point of time 17 to the point of time 17.5, and is in a state of the high level during a period of time from the point of time 17.5 to the point of time 18. The time slot associated with the voltage value Vd(X) is TS1 during a period of time from the point of time 18 to the point of time 20; the synchronization signal D is in a state of the high level during the period of time from the point of time 18 to the point of time 20. Namely, the driving waveform signal is separated from the time division multiplex signal based on the first sampling frequency, the second sampling frequency or the third sampling frequency corresponding to the respective periods of time. Each of during the period of time from the point of time 0 to the point of time 2, during the period of time from the point of time 8.5 to the point of time 9.5, and during the period of time from the point of time 17.5 to the point of time 20, the synchronization signal D is continuously in the state of the high level.
The synchronization signal generating circuits 62a to 62d output, respectively, the synchronization signals A to D to the switch group 54 (an example of “separator”). As depicted in
The switch group 54 opens or closes the selected n-th switch 54(n) at an opening and closing timing indicated by the selected one of the synchronization signals A to D. As descried before, since the time division multiplex signal is inputted to each of the plurality of n-th switches 54(n), the n-th switch 54(n) is opened or closed to thereby input the driving waveform corresponding to one of the driving waveform data Da to Dd to the actuator 88.
In a case that the synchronization signal B is selected, the switch group 54 closes the n-th switch 54(n) in a case that the pulse of the synchronization signal B is of the high level, and opens the n-th switch 54(n) in a case that the pulse of the synchronization signal B is of the low level. The electric charge applied to the individual electrode 85 in the case that the n-th switch 54(n) is closed is maintained by the first capacitor 89a and the second capacitor 89b. Namely, a driving waveform signal WB is separated from the time division multiplex signal. As depicted in
In a case that the synchronization signal C is selected, the switch group 54 closes the n-th switch 54(n) in a case that the pulse of the synchronization signal C is of the high level, and opens the n-th switch 54(n) in a case that the pulse of the synchronization signal C is of the low level. The electric charge applied to the individual electrode 85 in a case that the n-th switch 54(n) is closed is maintained by the first capacitor 89a and the second capacitor 89b. Namely, a driving waveform signal WC is separated from the time division multiplex signal. As depicted in
In a case that the synchronization signal D is selected, the switch group 54 closes the n-th switch 54(n) in a case that the pulse of the synchronization signal D is of the high level, and opens the n-th switch 54(n) in a case that the pulse of the synchronization signal D is of the low level. The electric charge applied to the individual electrode 85 in a case that the n-th switch 54(n) is closed is maintained by the first capacitor 89a and the second capacitor 89b. Namely, a driving waveform signal WD is separated from the time division multiplex signal. As depicted in
In a case that the actuator 88 is driven by the driving waveform signal WA, the size of the ink discharged from the nozzle 80 is “medium”. In a case that the actuator 88 is driven by the driving waveform signal WB, the size of the ink discharged from the nozzle 80 is “large”. In each of a case that the actuator 88 is driven by the driving waveform signal WC and a case that the actuator 88 is driven by the driving waveform signal WD, the size of the ink discharged from the nozzle 80 is “small”. The timing of discharging the ink is different between the driving waveform WC and the driving waveform WD.
In the first embodiment, the comparing circuit 57 compares the voltage values inputted, respectively, from the voltage table Tva to Tvd, in a case that any one of the comparison timing signals Sa to Sd is inputted from the counters 56a to 56d to the comparing circuit 57. However, the timing at which the voltage values are compared is not limited to or restricted by this. For example, it is allowable that the frequency generating circuit 58 outputs the comparison timing signal having the reference frequency (24 MHz) to the comparing circuit 57 and that the comparing circuit 57 compares the voltage values inputted from the respective voltage table Tva to Tvd, at each of points of time at which one cycle of the reference frequency elapses. For example, as depicted in the upper view of
In the first embodiment, there are the three voltage values which are 0, V1 and V2; the four driving waveform data Da to Dd do not have or indicate mutually different voltages at a time. However, for example, in a case that there is the voltage value V3 which is greater than the voltage value V2, the voltage values, respectively, of the four driving waveform data Da to Dd may be 0, V1, V2 and V3, respectively, at a time, and may have or indicate mutually different voltage values. In such a case, the time slots which are applied are TS7 to TS10 (see
In the printing apparatus according to the first embodiment, the time division multiplex signal is generated from the plurality of pieces of the driving waveform data Da to Dd indicating, respectively, the mutually different driving waveforms. Each, of the driving waveform signals WA to WD, which corresponds to one of the mutually different driving waveforms is separated from the generated time division multiplex signal. The actuator 88 is driven by any one, of the driving waveform signal WA and WD, separated from the time division multiplex signal. By separating one of the driving waveform signals WA to WD, it is possible to adjust the shape of the driving waveform to be applied to the actuator 88. Further, the one cycle for printing one pixel includes only a cycle of any one of the driving waveforms, and does not include the cycle(s) of another or any other driving waveform(s). Accordingly, it is possible to reduce the waiting time of the nozzle 80.
In a case that the driving waveform data Da to Dd include such data wherein the voltage values have a same voltage value at a time, for example in a case that the voltage values of the driving waveform data Da to Dc are V2 during a period of time from the point of time 5 μs to 6 μs, as indicated by the middle view of
In the above embodiment, in a case that a voltage value indicated by one driving waveform and a voltage value indicated by another driving waveform are same as each other in a certain period of time, the time division multiplex signal during the certain period of time includes a signal collectively corresponds to one driving waveform and another driving waveform. Thus, regarding the certain period of time, a width (temporal width) of the signal is large. Accordingly, it is possible to separate one driving waveform and another driving waveform from the time division multiplex signal precisely even in a case that any error to some extent occurs in the synchronization signal to be used for the separation.
A second embodiment of the present disclosure will be explained below on the basis of the drawings which depict a printing apparatus 1 according to the second embodiment. Constitutive components according to the second embodiment, which are the same as or equivalent to the constitutive components according to the first embodiment, are designated by the same reference numerals as those of the first embodiment, any detailed explanation of which will be omitted.
As depicted by the upper view of
In the middle view of
A third embodiment of the present disclosure will be explained below on the basis of the drawings which depict a printing apparatus 1 according to the third embodiment. Constitutive components according to the third embodiment, which are the same as or equivalent to the constitutive components according to the first or second embodiment, are designated by the same reference numerals as those of the first or second embodiment, any detailed explanation of which will be omitted. A variety of kinds of a printing method are inputted from the external device 100 to the controller 50. The printing method includes, for example, low resolution printing, high resolution printing, overlapping printing, high speed printing and low speed printing. The overlapping printing is a printing method wherein first printing is performed with respect to a print medium, and then second printing is performed to be overlapped on a part of the print medium. the first printing having been performed on the part of the print medium. The controller 50 (specifically, for example, CPU 51a or the switching circuit 59. An example of “selector”.) selects a predetermined number of driving waveform data among the four driving waveform data Da to Dd, depending on the printing method inputted to the controller 50, and executes the printing based on the driving waveform data of the selected predetermined number.
A case of executing the low resolution printing will be explained.
In a case that a print job indicating the low resolution printing is inputted, the CPU 51a associates TS4 and the voltage value Va(X) with each other and outputs TS4 and the voltage value Va(X) which are associated with each other to the selector circuit 60; the CPU Ma associates TS5 and the voltage value Vb(X) with each other and outputs TS5 and the voltage value Vb(X) which are associated with each other to the selector circuit 60; and the CPU Ma associates TS6 and the voltage value Vc(X) with each other and outputs TS6 and the voltage value Vc(X) which are associated with each other to the selector circuit 60. As depicted in the middle view of
As depicted in the middle view of
As depicted in the middle view of
The CPU 51a outputs TS4 to the synchronization signal generating circuit 62a, outputs TS5 to the synchronization signal generating circuit 62b, and outputs TS6 to the synchronization signal generating circuit 62c. As depicted in the lower view of
In a case that the synchronization signal A is selected, the driving waveform signal WA is separated from the time division multiplex signal; the driving waveform signal WA is inputted to the actuator 88; and the actuator 88 is driven. In a case that the synchronization signal B is selected, the driving waveform signal WB is separated from the time division multiplex signal; the driving waveform signal WB is inputted to the actuator 88; and the actuator 88 is driven. In a case that the synchronization signal C is selected, the driving waveform signal WC is separated from the time division multiplex signal; the driving waveform signal WC is inputted to the actuator 88; and the actuator 88 is driven.
A case of executing the high speed printing will be explained.
In a case that a print job indicating the high speed printing is inputted, the CPU 51a associates TS2 and the voltage value Va(X) with each other and outputs TS2 and the voltage value Va(X) which are associated with each other to the selector circuit 60; and the CPU 51a associates TS3 and the voltage value Vd(X) with each other and outputs TS3 and the voltage value Vd(X) which are associated with each other to the selector circuit 60. As depicted in the second uppermost view of
As depicted in the second uppermost view of
The CPU 51a outputs TS2 to the synchronization signal generating circuit 62a, and outputs TS3 to the synchronization signal generating circuit 62d. As depicted in the third uppermost view of
In a case that the synchronization signal A is selected, the driving waveform signal WA is separated from the time division multiplex signal; the driving waveform signal WA is inputted to the actuator 88; and the actuator 88 is driven. In a case that the synchronization signal D is selected, the driving waveform signal WD is separated from the time division multiplex signal; the driving waveform signal WD is inputted to the actuator 88; and the actuator 88 is driven.
A case of executing a first printing in the overlapping printing will be explained.
In a case that a print job indicating the first printing is inputted, the CPU 51a associates TS1 and the voltage value Vb(X) with each other and outputs TS1 and the voltage value Vb(X) which are associated with each other to the selector circuit 60. As depicted in the middle view of
The CPU Ma outputs TS1 to the synchronization signal generating circuit 62b. As depicted in the lower view of
The CPU 51a executes one print task (step S7). A print task is a unit constructing the print job. Specifically, the print task is a liquid discharging processing which is performed during a period of time wherein the ink-jet head 8 is (being) moved rightward or leftward by a distance corresponding to a left-right width of the recording paper 200. Next, the CPU 51a determines whether or not abnormality is occurred during the print task (step S8). The abnormality is, for example, paper jam. In a case that abnormality is occurred during the print task (step S8: YES), the CPU 51a executes an abnormality processing (step S15). The details of the abnormality processing will be described later on.
In a case that abnormality is not occurred during the print task (step S8: NO), the CPU 51a determines whether or not the one print task is completed (step S9). Note that in the one print task, the carriage 6 performs one scanning (scans one time). In a case that the one print task is not completed (step S9: NO), the CPU 51a returns the process to step S8. In a case that the one print task is completed (step S9: YES), the CPU 51a determines whether or not the print job is completed (step S10). In a case that the print job is not completed (step S10: NO), the CPU 51a returns the process to step S7, and executes a next one print task. In a case that the print job is completed (step S10: YES), the CPU 51a completes the first multiplexing processing or a second multiplexing processing which will be described later on (step S11), and executes a flushing processing (step S12). The flushing processing is a processing in which the ink is discharged from the nozzles 80 for any purpose other than the purpose of the printing. The flushing process is executed, for example, at the flushing receiver 21. After executing the flushing processing, the CPU 51a ends the print processing.
In a case that the print job is not the second printing in step S2 (step S2: NO), namely, that the print job is the first printing, in a case that the print job is not the high resolution printing in step S3 (step S3: NO), namely, that the print job is the low resolution printing, or in a case that the print job is not the low speed printing in step S4 (step S4: NO), namely, that the print job is the high speed printing, the CPU 51a selects one piece to three pieces of the driving waveform data corresponding to the print method (step S13), and starts a second multiplexing processing (step S14). The second multiplexing processing is a generation processing of generating the time division multiplex signal and a separation processing of separating the driving waveform signal from the time division multiplex signal, as described in the third embodiment. After executing step S14, the CPU 51a proceeds the process to step S7.
In the printing apparatus 1 according to the third embodiment, the driving waveform data as mush as the number (quantity) depending on the print method is/are selected from the plurality of pieces of waveform driving data. Therefore, it is possible to reduce the number of the driving waveform data to be used for the printing, to reduce the number of the synchronization signal as compared with a case of using all of the plurality of pieces of the driving waveform data, to make the switching frequency in the switch group 54 to be small, and to suppress any generation of noise and any increase in the power consumption.
The embodiments disclosed herein are examples in all senses, and should be interpreted not restrictive or limiting in any way. The technical features described in the respective embodiments can be combined with each other, and the scope of the present invention is intended to encompass all the changes within the scope of the claims and a scope equivalent to the scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-161820 | Sep 2021 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20070146403 | Sayama et al. | Jun 2007 | A1 |
| 20070177169 | Han | Aug 2007 | A1 |
| 20080122888 | Suzuki | May 2008 | A1 |
| 20130083106 | Tsukamoto | Apr 2013 | A1 |
| 20130182025 | Yanaka | Jul 2013 | A1 |
| 20170113461 | Netsu et al. | Apr 2017 | A1 |
| 20180201012 | Miyagishi | Jul 2018 | A1 |
| 20180272705 | Ono | Sep 2018 | A1 |
| 20190126611 | Lahiri et al. | May 2019 | A1 |
| 20210060935 | Kashimura et al. | Mar 2021 | A1 |
| 20220314617 | Hiwada | Oct 2022 | A1 |
| Number | Date | Country |
|---|---|---|
| S5888469 | Jun 1983 | JP |
| 2001-54947 | Feb 2001 | JP |
| 2008-126612 | Jun 2008 | JP |
| 2010-64465 | Mar 2010 | JP |
| 2010142978 | Jul 2010 | JP |
| 2011-20330 | Feb 2011 | JP |
| 2017080891 | May 2017 | JP |
| 2017-113965 | Jun 2017 | JP |
| 2019-512413 | May 2019 | JP |
| Entry |
|---|
| EP Office Action dated Jun. 25, 2024 from application EP 22 155 761.4. |
| Related U.S. Appl. No. 17/693,614, filed Mar. 14, 2022. |
| Official Action dated Nov. 24, 2023 from related application, namely, U.S. Appl. No. 17/693,614, filed Mar. 14, 2022. |
| Extended European Search Report dated Jul. 22, 2022 of EP Patent Application No. 22155761.4. |
| Notice of Reasons for Refusal dated Jan. 9, 2024 of Japanese Patent Application No. 2021-143754 with computer generated translation. |
| Related U.S. Appl. No. 17/693,677, filed Mar. 14, 2022. |
| Notice of Reasons for Refusal dated Jan. 9, 2024 received from the Japanese Patent Office in related JP 2021-161820 together with English language translation. |
| Number | Date | Country | |
|---|---|---|---|
| 20230094405 A1 | Mar 2023 | US |
