"Analytical Power/Timing Optimization Technique for Digital System" by Ruehli et al., IEEE 14th Design Automation Conf., 1977, pp. 142-146. |
"Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits" by Lin et al., IEEE 1984 Conf. on Advanced Research in VLSI, M.I.T., pp. 93-99. |
J. Mavor et al., Introduction to MOS LSI Design, Chapter 3, Addison-Wesly Publication Company, 1983, pp. 79-85. |
"PHILO-A VLSI Design System" by R. Donze et al., IEEE 19th Design Automation Conf., 1982, pp. 163-169. |
"Tilos: A Posynomial Programming Approach to Transistor Sizing", Fishburn et al. |
"Optimization of Digital MOS VLSI Circuits", Matson, 1985. |
"Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits", Lin et al., 1984. |
"Timing Analysis for .eta.MOS VSI", Jouppi, 1983. |
"Processing for Selecting Circuits with Optimum Power and Area Requirements", Linville, et al., 1975. |
"Analytical Power/Timing Optimization Technique for Digital System", Ruehli, et al., 1977. |